cpldfit:  version J.36                              Xilinx Inc.
                                  Fitter Report
Design Name: ARepKey                             Date:  4-14-2009,  0:38AM
Device Used: XC2C256-6-VQ100
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
56 /256 ( 22%) 120 /896  ( 13%) 88  /640  ( 14%) 39 /256 ( 15%) 15 /80  ( 19%)

** Function Block Resources **

Function Mcells   FB Inps  Pterms   IO       CTC      CTR      CTS      CTE     
Block    Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot
FB1      16/16*    22/40    26/56     0/ 5    1/1*     1/1*     0/1      0/1
FB2      16/16*    20/40    48/56     6/ 6*   0/1      1/1*     0/1      0/1
FB3      16/16*    31/40    33/56     0/ 4    1/1*     1/1*     0/1      0/1
FB4       4/16     11/40     9/56     2/ 6    1/1*     1/1*     0/1      0/1
FB5       0/16      0/40     0/56     0/ 2    0/1      0/1      0/1      0/1
FB6       2/16      2/40     2/56     2/ 5    0/1      0/1      0/1      0/1
FB7       2/16      2/40     2/56     2/ 6    0/1      0/1      0/1      0/1
FB8       0/16      0/40     0/56     0/ 6    0/1      0/1      0/1      0/1
FB9       0/16      0/40     0/56     0/ 5    0/1      0/1      0/1      0/1
FB10      0/16      0/40     0/56     0/ 7    0/1      0/1      0/1      0/1
FB11      0/16      0/40     0/56     0/ 4    0/1      0/1      0/1      0/1
FB12      0/16      0/40     0/56     0/ 4    0/1      0/1      0/1      0/1
FB13      0/16      0/40     0/56     0/ 4    0/1      0/1      0/1      0/1
FB14      0/16      0/40     0/56     0/ 5    0/1      0/1      0/1      0/1
FB15      0/16      0/40     0/56     0/ 6    0/1      0/1      0/1      0/1
FB16      0/16      0/40     0/56     0/ 5    0/1      0/1      0/1      0/1
         -----    -------  -------   -----    ---      ---      ---      ---
Total    56/256    88/640  120/896   12/80    3/16     4/16     0/16     0/16

CTC - Control Term Clock
CTR - Control Term Reset
CTS - Control Term Set
CTE - Control Term Output Enable

* - Resource is exhausted

** Global Control Resources **

GCK         GSR         GTS         
Used/Tot    Used/Tot    Used/Tot    
1/3         0/1         0/4

Signal 'Clk' mapped onto global clock net GCK0.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :    2           2    |  I/O              :     8     70
Output        :   12          12    |  GCK/IO           :     2      3
Bidirectional :    0           0    |  GTS/IO           :     4      4
GCK           :    1           1    |  GSR/IO           :     0      1
GTS           :    0           0    |  CDR/IO           :     1      1
GSR           :    0           0    |  DGE/IO           :     0      1
                 ----        ----
        Total     15          15

End of Mapped Resource Summary
*************************  Summary of Mapped Logic  ************************

** 12 Outputs **

Signal                      Total Total Loc     Pin   Pin       Pin     I/O      I/O       Slew Reg     Reg Init
Name                        Pts   Inps          No.   Type      Use     STD      Style     Rate Use     State
Seg_K                       0     0     FB2_1   1     GTS/I/O   O       LVCMOS18           FAST         
Seg_G                       3     4     FB2_3   2     GTS/I/O   O       LVCMOS18           FAST         
Seg_F                       3     4     FB2_5   3     GTS/I/O   O       LVCMOS18           FAST         
Seg_E                       3     4     FB2_12  4     GTS/I/O   O       LVCMOS18           FAST         
Seg_D                       4     4     FB2_14  6     I/O       O       LVCMOS18           FAST         
Seg_C                       3     4     FB2_15  7     I/O       O       LVCMOS18           FAST         
Seg_A                       3     4     FB4_1   8     I/O       O       LVCMOS18           FAST         
Seg_B                       3     4     FB4_2   9     I/O       O       LVCMOS18           FAST         
DSel2                       1     2     FB6_2   24    CDR/I/O   O       LVCMOS18           FAST         
DSel3                       1     2     FB6_4   27    GCK/I/O   O       LVCMOS18           FAST         
DSel1                       1     2     FB7_5   19    I/O       O       LVCMOS18           FAST         
DSel0                       1     2     FB7_6   18    I/O       O       LVCMOS18           FAST         

** 44 Buried Nodes **

Signal                      Total Total Loc     Reg     Reg Init
Name                        Pts   Inps          Use     State
Cnt10<2>                    3     8     FB1_1   TFF     RESET
Cnt10<1>                    5     10    FB1_2   TFF     RESET
MuxDisplInstance/Tetr<0>    4     8     FB1_3           
Cnt10<3>                    4     10    FB1_4   TFF     RESET
Cnt100<0>                   3     10    FB1_5   TFF     RESET
Cnt1<2>                     3     4     FB1_6   TFF     RESET
Cnt100<2>                   3     12    FB1_7   TFF     RESET
Cnt100<1>                   5     14    FB1_8   TFF     RESET
Cnt100<3>                   4     14    FB1_9   TFF     RESET
Cnt1000<0>                  3     14    FB1_10  TFF     RESET
Cnt1000<2>                  3     16    FB1_11  TFF     RESET
Cnt1<1>                     4     6     FB1_12  TFF     RESET
Cnt1<3>                     4     6     FB1_13  TFF     RESET
Cnt10<0>                    3     6     FB1_14  TFF     RESET
Cnt1000<3>                  4     18    FB1_15  TFF     RESET
Cnt1000<1>                  5     18    FB1_16  TFF     RESET
AutomatState_FFd1           7     11    FB2_2   DFF     RESET
AutomatState_FFd3           6     11    FB2_4   TFF     RESET
AutomatState_FFd4           10    11    FB2_6   DFF     RESET
AutomatState_FFd2           4     10    FB2_7   DFF     RESET
DelayCntEnable              3     6     FB2_8   DFF     RESET
DelayCntClear               3     6     FB2_9   DFF     RESET
CntClk                      3     5     FB2_10  DFF     RESET
FClk                        2     3     FB2_11  TFF     RESET
FDivInstance/FDivCnt<1>     2     2     FB2_13  TFF     RESET
FDivInstance/FDivCnt<0>     1     1     FB2_16  TFF     RESET
MuxDisplInstance/SelCnt<0>  2     2     FB3_1   TFF     RESET
FDiv<5>                     3     7     FB3_2   TFF     RESET
FDiv<4>                     3     6     FB3_3   TFF     RESET
FDiv<3>                     3     5     FB3_4   TFF     RESET
DelayCnt<2>                 3     5     FB3_5   TFF     RESET
FDiv<2>                     3     4     FB3_6   TFF     RESET
FDiv<1>                     3     3     FB3_7   TFF     RESET
FDiv<0>                     2     2     FB3_8   TFF     RESET
Cnt1<0>                     2     2     FB3_9   TFF     RESET
N_PZ_406                    1     2     FB3_10          
MuxDisplInstance/Tetr<3>    4     8     FB3_11          
DelayCnt<1>                 3     4     FB3_12  TFF     RESET
MuxDisplInstance/Tetr<2>    4     8     FB3_13          
DelayCnt<0>                 3     3     FB3_14  TFF     RESET

Signal                      Total Total Loc     Reg     Reg Init
Name                        Pts   Inps          Use     State
MuxDisplInstance/Tetr<1>    4     8     FB3_15          
MuxDisplInstance/SelCnt<1>  3     3     FB3_16  TFF     RESET
DelayCnt<4>                 3     7     FB4_15  TFF     RESET
DelayCnt<3>                 3     6     FB4_16  TFF     RESET

** 3 Inputs **

Signal                      Loc     Pin   Pin       Pin     I/O      I/O
Name                                No.   Type      Use     STD      Style
Clk                         FB5_6   22    GCK/I/O   GCK     LVCMOS18 KPR
Reset                       FB12_15 65    I/O       I       LVCMOS18 KPR
KeyIn                       FB13_6  55    I/O       I       LVCMOS18 KPR

Legend:
Pin No.   - ~     - User Assigned
I/O Style - OD    - OpenDrain
          - PU    - Pullup
          - KPR   - Keeper
          - S     - SchmittTrigger
          - DG    - DataGate
Reg Use   - LATCH - Transparent latch
          - DFF   - D-flip-flop
          - DEFF  - D-flip-flop with clock enable
          - TFF   - T-flip-flop
          - TDFF  - Dual-edge-triggered T-flip-flop
          - DDFF  - Dual-edge-triggered flip-flop
          - DDEFF - Dual-edge-triggered flip-flop with clock enable
          /S (after any above flop/latch type) indicates initial state is Set
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
              VRF - Vref
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               22/18
Number of function block control terms used/remaining:        2/2
Number of PLA product terms used/remaining:                   26/30
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
Cnt10<2>                      3     FB1_1        (b)     (b)    +   +      
Cnt10<1>                      5     FB1_2        (b)     (b)    +   +      
MuxDisplInstance/Tetr<0>      4     FB1_3   99   GSR/I/O (b)               
Cnt10<3>                      4     FB1_4        (b)     (b)    +   +      
Cnt100<0>                     3     FB1_5        (b)     (b)    +   +      
Cnt1<2>                       3     FB1_6   97   I/O     (b)    +   +      
Cnt100<2>                     3     FB1_7        (b)     (b)    +   +      
Cnt100<1>                     5     FB1_8        (b)     (b)    +   +      
Cnt100<3>                     4     FB1_9        (b)     (b)    +   +      
Cnt1000<0>                    3     FB1_10       (b)     (b)    +   +      
Cnt1000<2>                    3     FB1_11       (b)     (b)    +   +      
Cnt1<1>                       4     FB1_12  96   I/O     (b)    +   +      
Cnt1<3>                       4     FB1_13  95   I/O     (b)    +   +      
Cnt10<0>                      3     FB1_14  94   I/O     (b)    +   +      
Cnt1000<3>                    4     FB1_15       (b)     (b)    +   +      
Cnt1000<1>                    5     FB1_16       (b)     (b)    +   +      

Signals Used by Logic in Function Block
  1: Cnt1000<0>         9: Cnt10<0>          16: Cnt1<3> 
  2: Cnt1000<1>        10: Cnt10<1>          17: CntClk 
  3: Cnt1000<2>        11: Cnt10<2>          18: DSel0 
  4: Cnt1000<3>        12: Cnt10<3>          19: DSel1 
  5: Cnt100<0>         13: Cnt1<0>           20: DSel2 
  6: Cnt100<1>         14: Cnt1<1>           21: DSel3 
  7: Cnt100<2>         15: Cnt1<2>           22: Reset 
  8: Cnt100<3>        

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
Cnt10<2>          ........XX..XXXXX....X.................. 8       
Cnt10<1>          ........XXXXXXXXX....X.................. 10      
MuxDisplInstance/Tetr<0> 
                  X...X...X...X....XXXX................... 8       
Cnt10<3>          ........XXXXXXXXX....X.................. 10      
Cnt100<0>         ........XXXXXXXXX....X.................. 10      
Cnt1<2>           ............XX..X....X.................. 4       
Cnt100<2>         ....XX..XXXXXXXXX....X.................. 12      
Cnt100<1>         ....XXXXXXXXXXXXX....X.................. 14      
Cnt100<3>         ....XXXXXXXXXXXXX....X.................. 14      
Cnt1000<0>        ....XXXXXXXXXXXXX....X.................. 14      
Cnt1000<2>        XX..XXXXXXXXXXXXX....X.................. 16      
Cnt1<1>           ............XXXXX....X.................. 6       
Cnt1<3>           ............XXXXX....X.................. 6       
Cnt10<0>          ............XXXXX....X.................. 6       
Cnt1000<3>        XXXXXXXXXXXXXXXXX....X.................. 18      
Cnt1000<1>        XXXXXXXXXXXXXXXXX....X.................. 18      
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB2  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               20/20
Number of function block control terms used/remaining:        1/3
Number of PLA product terms used/remaining:                   48/8
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
Seg_K                         0     FB2_1   1    GTS/I/O O                 
AutomatState_FFd1             7     FB2_2        (b)     (b)        +      
Seg_G                         3     FB2_3   2    GTS/I/O O                 
AutomatState_FFd3             6     FB2_4        (b)     (b)        +      
Seg_F                         3     FB2_5   3    GTS/I/O O                 
AutomatState_FFd4             10    FB2_6        (b)     (b)        +      
AutomatState_FFd2             4     FB2_7        (b)     (b)        +      
DelayCntEnable                3     FB2_8        (b)     (b)               
DelayCntClear                 3     FB2_9        (b)     (b)               
CntClk                        3     FB2_10       (b)     (b)               
FClk                          2     FB2_11       (b)     (b)        +      
Seg_E                         3     FB2_12  4    GTS/I/O O                 
FDivInstance/FDivCnt<1>       2     FB2_13       (b)     (b)        +      
Seg_D                         4     FB2_14  6    I/O     O                 
Seg_C                         3     FB2_15  7    I/O     O                 
FDivInstance/FDivCnt<0>       1     FB2_16       (b)     (b)        +      

Signals Used by Logic in Function Block
  1: AutomatState_FFd1   8: DelayCnt<2>              15: KeyIn 
  2: AutomatState_FFd2   9: DelayCnt<3>              16: MuxDisplInstance/Tetr<0> 
  3: AutomatState_FFd3  10: DelayCnt<4>              17: MuxDisplInstance/Tetr<1> 
  4: AutomatState_FFd4  11: DelayCntClear            18: MuxDisplInstance/Tetr<2> 
  5: CntClk             12: DelayCntEnable           19: MuxDisplInstance/Tetr<3> 
  6: DelayCnt<0>        13: FDivInstance/FDivCnt<0>  20: Reset 
  7: DelayCnt<1>        14: FDivInstance/FDivCnt<1> 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
Seg_K             ........................................ 0       
AutomatState_FFd1 
                  XXXX.XXXXX....X....X.................... 11      
Seg_G             ...............XXXX..................... 4       
AutomatState_FFd3 
                  XXXX.XXXXX....X....X.................... 11      
Seg_F             ...............XXXX..................... 4       
AutomatState_FFd4 
                  XXXX.XXXXX....X....X.................... 11      
AutomatState_FFd2 
                  XXXX.XXXXX.........X.................... 10      
DelayCntEnable    XXXX.......X.......X.................... 6       
DelayCntClear     XXXX......X........X.................... 6       
CntClk            .XXXX..............X.................... 5       
FClk              ............XX.....X.................... 3       
Seg_E             ...............XXXX..................... 4       
FDivInstance/FDivCnt<1> 
                  ............X......X.................... 2       
Seg_D             ...............XXXX..................... 4       
Seg_C             ...............XXXX..................... 4       
FDivInstance/FDivCnt<0> 
                  ...................X.................... 1       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB3  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               31/9
Number of function block control terms used/remaining:        2/2
Number of PLA product terms used/remaining:                   33/23
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
MuxDisplInstance/SelCnt<0>    2     FB3_1        (b)     (b)        +      
FDiv<5>                       3     FB3_2        (b)     (b)    +   +      
FDiv<4>                       3     FB3_3        (b)     (b)    +   +      
FDiv<3>                       3     FB3_4        (b)     (b)    +   +      
DelayCnt<2>                   3     FB3_5   93   I/O     (b)               
FDiv<2>                       3     FB3_6        (b)     (b)    +   +      
FDiv<1>                       3     FB3_7        (b)     (b)    +   +      
FDiv<0>                       2     FB3_8        (b)     (b)    +   +      
Cnt1<0>                       2     FB3_9        (b)     (b)        +      
N_PZ_406                      1     FB3_10       (b)     (b)               
MuxDisplInstance/Tetr<3>      4     FB3_11       (b)     (b)               
DelayCnt<1>                   3     FB3_12  92   I/O     (b)               
MuxDisplInstance/Tetr<2>      4     FB3_13       (b)     (b)               
DelayCnt<0>                   3     FB3_14  91   I/O     (b)               
MuxDisplInstance/Tetr<1>      4     FB3_15       (b)     (b)               
MuxDisplInstance/SelCnt<1>    3     FB3_16  90   I/O     (b)        +      

Signals Used by Logic in Function Block
  1: Cnt1000<1>        12: Cnt1<3>           22: FClk 
  2: Cnt1000<2>        13: CntClk            23: FDiv<0> 
  3: Cnt1000<3>        14: DSel0             24: FDiv<1> 
  4: Cnt100<1>         15: DSel1             25: FDiv<2> 
  5: Cnt100<2>         16: DSel2             26: FDiv<3> 
  6: Cnt100<3>         17: DSel3             27: FDiv<4> 
  7: Cnt10<1>          18: DelayCnt<0>       28: FDiv<5> 
  8: Cnt10<2>          19: DelayCnt<1>       29: MuxDisplInstance/SelCnt<0> 
  9: Cnt10<3>          20: DelayCntClear     30: N_PZ_406 
 10: Cnt1<1>           21: DelayCntEnable    31: Reset 
 11: Cnt1<2>          

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
MuxDisplInstance/SelCnt<0> 
                  ........................X.....X......... 2       
FDiv<5>           .....................XXXXXX...X......... 7       
FDiv<4>           .....................XXXXX....X......... 6       
FDiv<3>           .....................XXXX.....X......... 5       
DelayCnt<2>       .................XX.X......X.X.......... 5       
FDiv<2>           .....................XXX......X......... 4       
FDiv<1>           .....................XX.......X......... 3       
FDiv<0>           .....................X........X......... 2       
Cnt1<0>           ............X.................X......... 2       
N_PZ_406          ...................X..........X......... 2       
MuxDisplInstance/Tetr<3> 
                  ..X..X..X..X.XXXX....................... 8       
DelayCnt<1>       .................X..X......X.X.......... 4       
MuxDisplInstance/Tetr<2> 
                  .X..X..X..X..XXXX....................... 8       
DelayCnt<0>       ....................X......X.X.......... 3       
MuxDisplInstance/Tetr<1> 
                  X..X..X..X...XXXX....................... 8       
MuxDisplInstance/SelCnt<1> 
                  ........................X...X.X......... 3       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB4  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               11/29
Number of function block control terms used/remaining:        2/2
Number of PLA product terms used/remaining:                   9/47
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
Seg_A                         3     FB4_1   8    I/O     O                 
Seg_B                         3     FB4_2   9    I/O     O                 
(unused)                      0     FB4_3   10   I/O           
(unused)                      0     FB4_4        (b)           
(unused)                      0     FB4_5   11   I/O           
(unused)                      0     FB4_6   12   I/O           
(unused)                      0     FB4_7        (b)           
(unused)                      0     FB4_8        (b)           
(unused)                      0     FB4_9        (b)           
(unused)                      0     FB4_10       (b)           
(unused)                      0     FB4_11       (b)           
(unused)                      0     FB4_12       (b)           
(unused)                      0     FB4_13  13   I/O           
(unused)                      0     FB4_14       (b)           
DelayCnt<4>                   3     FB4_15       (b)     (b)    +   +      
DelayCnt<3>                   3     FB4_16       (b)     (b)    +   +      

Signals Used by Logic in Function Block
  1: DelayCnt<0>        5: DelayCntEnable             9: MuxDisplInstance/Tetr<2> 
  2: DelayCnt<1>        6: FDiv<5>                   10: MuxDisplInstance/Tetr<3> 
  3: DelayCnt<2>        7: MuxDisplInstance/Tetr<0>  11: N_PZ_406 
  4: DelayCnt<3>        8: MuxDisplInstance/Tetr<1> 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
Seg_A             ......XXXX.............................. 4       
Seg_B             ......XXXX.............................. 4       
DelayCnt<4>       XXXXXX....X............................. 7       
DelayCnt<3>       XXX.XX....X............................. 6       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB5  ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB5_1        (b)           
(unused)                      0     FB5_2        (b)           
(unused)                      0     FB5_3        (b)           
(unused)                      0     FB5_4   23   GCK/I/O       
(unused)                      0     FB5_5        (b)           
(unused)                      0     FB5_6   22   GCK/I/O GCK   
(unused)                      0     FB5_7        (b)           
(unused)                      0     FB5_8        (b)           
(unused)                      0     FB5_9        (b)           
(unused)                      0     FB5_10       (b)           
(unused)                      0     FB5_11       (b)           
(unused)                      0     FB5_12       (b)           
(unused)                      0     FB5_13       (b)           
(unused)                      0     FB5_14       (b)           
(unused)                      0     FB5_15       (b)           
(unused)                      0     FB5_16       (b)           
*********************************** FB6  ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               2/38
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   2/54
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB6_1        (b)           
DSel2                         1     FB6_2   24   CDR/I/O O                 
(unused)                      0     FB6_3        (b)           
DSel3                         1     FB6_4   27   GCK/I/O O                 
(unused)                      0     FB6_5        (b)           
(unused)                      0     FB6_6        (b)           
(unused)                      0     FB6_7        (b)           
(unused)                      0     FB6_8        (b)           
(unused)                      0     FB6_9        (b)           
(unused)                      0     FB6_10       (b)           
(unused)                      0     FB6_11       (b)           
(unused)                      0     FB6_12  28   DGE/I/O       
(unused)                      0     FB6_13       (b)           
(unused)                      0     FB6_14  29   I/O           
(unused)                      0     FB6_15       (b)           
(unused)                      0     FB6_16  30   I/O           

Signals Used by Logic in Function Block
  1: MuxDisplInstance/SelCnt<0>   2: MuxDisplInstance/SelCnt<1> 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
DSel2             XX...................................... 2       
DSel3             XX...................................... 2       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB7  ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               2/38
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   2/54
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB7_1        (b)           
(unused)                      0     FB7_2        (b)           
(unused)                      0     FB7_3        (b)           
(unused)                      0     FB7_4        (b)           
DSel1                         1     FB7_5   19   I/O     O                 
DSel0                         1     FB7_6   18   I/O     O                 
(unused)                      0     FB7_7        (b)           
(unused)                      0     FB7_8        (b)           
(unused)                      0     FB7_9        (b)           
(unused)                      0     FB7_10       (b)           
(unused)                      0     FB7_11  17   I/O           
(unused)                      0     FB7_12  16   I/O           
(unused)                      0     FB7_13  15   I/O           
(unused)                      0     FB7_14  14   I/O           
(unused)                      0     FB7_15       (b)           
(unused)                      0     FB7_16       (b)           

Signals Used by Logic in Function Block
  1: MuxDisplInstance/SelCnt<0>   2: MuxDisplInstance/SelCnt<1> 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
DSel1             XX...................................... 2       
DSel0             XX...................................... 2       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB8  ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB8_1        (b)           
(unused)                      0     FB8_2        (b)           
(unused)                      0     FB8_3        (b)           
(unused)                      0     FB8_4        (b)           
(unused)                      0     FB8_5        (b)           
(unused)                      0     FB8_6   32   I/O           
(unused)                      0     FB8_7        (b)           
(unused)                      0     FB8_8        (b)           
(unused)                      0     FB8_9        (b)           
(unused)                      0     FB8_10       (b)           
(unused)                      0     FB8_11  33   I/O           
(unused)                      0     FB8_12  34   I/O           
(unused)                      0     FB8_13  35   I/O           
(unused)                      0     FB8_14  36   I/O           
(unused)                      0     FB8_15  37   I/O           
(unused)                      0     FB8_16       (b)           
*********************************** FB9  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB9_1   78   I/O           
(unused)                      0     FB9_2   79   I/O           
(unused)                      0     FB9_3        (b)           
(unused)                      0     FB9_4   80   I/O           
(unused)                      0     FB9_5        (b)           
(unused)                      0     FB9_6   81   I/O           
(unused)                      0     FB9_7        (b)           
(unused)                      0     FB9_8        (b)           
(unused)                      0     FB9_9        (b)           
(unused)                      0     FB9_10       (b)           
(unused)                      0     FB9_11       (b)           
(unused)                      0     FB9_12  82   I/O           
(unused)                      0     FB9_13       (b)           
(unused)                      0     FB9_14       (b)           
(unused)                      0     FB9_15       (b)           
(unused)                      0     FB9_16       (b)           
*********************************** FB10 ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB10_1  77   I/O           
(unused)                      0     FB10_2  76   I/O           
(unused)                      0     FB10_3  74   I/O           
(unused)                      0     FB10_4  73   I/O           
(unused)                      0     FB10_5  72   I/O           
(unused)                      0     FB10_6  71   I/O           
(unused)                      0     FB10_7       (b)           
(unused)                      0     FB10_8       (b)           
(unused)                      0     FB10_9       (b)           
(unused)                      0     FB10_10      (b)           
(unused)                      0     FB10_11      (b)           
(unused)                      0     FB10_12 70   I/O           
(unused)                      0     FB10_13      (b)           
(unused)                      0     FB10_14      (b)           
(unused)                      0     FB10_15      (b)           
(unused)                      0     FB10_16      (b)           
*********************************** FB11 ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB11_1       (b)           
(unused)                      0     FB11_2       (b)           
(unused)                      0     FB11_3       (b)           
(unused)                      0     FB11_4       (b)           
(unused)                      0     FB11_5       (b)           
(unused)                      0     FB11_6       (b)           
(unused)                      0     FB11_7       (b)           
(unused)                      0     FB11_8       (b)           
(unused)                      0     FB11_9       (b)           
(unused)                      0     FB11_10      (b)           
(unused)                      0     FB11_11 85   I/O           
(unused)                      0     FB11_12 86   I/O           
(unused)                      0     FB11_13 87   I/O           
(unused)                      0     FB11_14 89   I/O           
(unused)                      0     FB11_15      (b)           
(unused)                      0     FB11_16      (b)           
*********************************** FB12 ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB12_1       (b)           
(unused)                      0     FB12_2       (b)           
(unused)                      0     FB12_3       (b)           
(unused)                      0     FB12_4       (b)           
(unused)                      0     FB12_5       (b)           
(unused)                      0     FB12_6       (b)           
(unused)                      0     FB12_7       (b)           
(unused)                      0     FB12_8       (b)           
(unused)                      0     FB12_9       (b)           
(unused)                      0     FB12_10      (b)           
(unused)                      0     FB12_11 68   I/O           
(unused)                      0     FB12_12      (b)           
(unused)                      0     FB12_13 67   I/O           
(unused)                      0     FB12_14 66   I/O           
(unused)                      0     FB12_15 65   I/O     I     
(unused)                      0     FB12_16      (b)           
*********************************** FB13 ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB13_1       (b)           
(unused)                      0     FB13_2  53   I/O           
(unused)                      0     FB13_3       (b)           
(unused)                      0     FB13_4  54   I/O           
(unused)                      0     FB13_5       (b)           
(unused)                      0     FB13_6  55   I/O     I     
(unused)                      0     FB13_7       (b)           
(unused)                      0     FB13_8       (b)           
(unused)                      0     FB13_9       (b)           
(unused)                      0     FB13_10      (b)           
(unused)                      0     FB13_11      (b)           
(unused)                      0     FB13_12      (b)           
(unused)                      0     FB13_13 56   I/O           
(unused)                      0     FB13_14      (b)           
(unused)                      0     FB13_15      (b)           
(unused)                      0     FB13_16      (b)           
*********************************** FB14 ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB14_1  52   I/O           
(unused)                      0     FB14_2       (b)           
(unused)                      0     FB14_3  50   I/O           
(unused)                      0     FB14_4       (b)           
(unused)                      0     FB14_5  49   I/O           
(unused)                      0     FB14_6       (b)           
(unused)                      0     FB14_7       (b)           
(unused)                      0     FB14_8       (b)           
(unused)                      0     FB14_9       (b)           
(unused)                      0     FB14_10      (b)           
(unused)                      0     FB14_11      (b)           
(unused)                      0     FB14_12      (b)           
(unused)                      0     FB14_13      (b)           
(unused)                      0     FB14_14 46   I/O           
(unused)                      0     FB14_15 44   I/O           
(unused)                      0     FB14_16      (b)           
*********************************** FB15 ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB15_1       (b)           
(unused)                      0     FB15_2       (b)           
(unused)                      0     FB15_3       (b)           
(unused)                      0     FB15_4       (b)           
(unused)                      0     FB15_5       (b)           
(unused)                      0     FB15_6       (b)           
(unused)                      0     FB15_7       (b)           
(unused)                      0     FB15_8       (b)           
(unused)                      0     FB15_9       (b)           
(unused)                      0     FB15_10      (b)           
(unused)                      0     FB15_11 58   I/O           
(unused)                      0     FB15_12 59   I/O           
(unused)                      0     FB15_13 60   I/O           
(unused)                      0     FB15_14 61   I/O           
(unused)                      0     FB15_15 63   I/O           
(unused)                      0     FB15_16 64   I/O           
*********************************** FB16 ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB16_1       (b)           
(unused)                      0     FB16_2       (b)           
(unused)                      0     FB16_3       (b)           
(unused)                      0     FB16_4       (b)           
(unused)                      0     FB16_5  43   I/O           
(unused)                      0     FB16_6  42   I/O           
(unused)                      0     FB16_7       (b)           
(unused)                      0     FB16_8       (b)           
(unused)                      0     FB16_9       (b)           
(unused)                      0     FB16_10      (b)           
(unused)                      0     FB16_11 41   I/O           
(unused)                      0     FB16_12 40   I/O           
(unused)                      0     FB16_13 39   I/O           
(unused)                      0     FB16_14      (b)           
(unused)                      0     FB16_15      (b)           
(unused)                      0     FB16_16      (b)           
*******************************  Equations  ********************************

********** Mapped Logic **********

FDCPE_AutomatState_FFd1: FDCPE port map (AutomatState_FFd1,AutomatState_FFd1_D,Clk,NOT Reset,'0','1');
AutomatState_FFd1_D <= ((AutomatState_FFd4 AND AutomatState_FFd2 AND 
	NOT AutomatState_FFd3)
	OR (NOT KeyIn AND AutomatState_FFd1 AND DelayCnt(0))
	OR (NOT KeyIn AND AutomatState_FFd1 AND DelayCnt(1))
	OR (NOT KeyIn AND AutomatState_FFd1 AND NOT DelayCnt(2))
	OR (NOT KeyIn AND AutomatState_FFd1 AND DelayCnt(3))
	OR (NOT KeyIn AND AutomatState_FFd1 AND DelayCnt(4)));

FDCPE_AutomatState_FFd2: FDCPE port map (AutomatState_FFd2,AutomatState_FFd2_D,Clk,NOT Reset,'0','1');
AutomatState_FFd2_D <= NOT (((AutomatState_FFd4 AND NOT AutomatState_FFd2 AND 
	NOT AutomatState_FFd1)
	OR (NOT AutomatState_FFd2 AND NOT AutomatState_FFd1 AND 
	NOT AutomatState_FFd3)
	OR (NOT AutomatState_FFd4 AND NOT AutomatState_FFd1 AND 
	NOT AutomatState_FFd3 AND DelayCnt(0) AND DelayCnt(1) AND NOT DelayCnt(2) AND 
	NOT DelayCnt(3) AND NOT DelayCnt(4))));

FTCPE_AutomatState_FFd3: FTCPE port map (AutomatState_FFd3,AutomatState_FFd3_T,Clk,NOT Reset,'0','1');
AutomatState_FFd3_T <= ((AutomatState_FFd4 AND NOT AutomatState_FFd2 AND 
	NOT AutomatState_FFd3)
	OR (KeyIn AND AutomatState_FFd1 AND NOT AutomatState_FFd3)
	OR (AutomatState_FFd4 AND KeyIn AND NOT AutomatState_FFd1 AND 
	AutomatState_FFd3)
	OR (AutomatState_FFd4 AND NOT KeyIn AND AutomatState_FFd2 AND 
	AutomatState_FFd3)
	OR (NOT KeyIn AND AutomatState_FFd2 AND AutomatState_FFd3 AND 
	NOT DelayCnt(0) AND NOT DelayCnt(1) AND DelayCnt(2) AND DelayCnt(3) AND 
	DelayCnt(4)));

FDCPE_AutomatState_FFd4: FDCPE port map (AutomatState_FFd4,AutomatState_FFd4_D,Clk,NOT Reset,'0','1');
AutomatState_FFd4_D <= (AutomatState_FFd4 AND NOT KeyIn AND NOT AutomatState_FFd2)
	XOR ((KeyIn AND AutomatState_FFd1)
	OR (AutomatState_FFd4 AND KeyIn AND NOT AutomatState_FFd2 AND 
	NOT AutomatState_FFd3)
	OR (NOT AutomatState_FFd4 AND KeyIn AND AutomatState_FFd2 AND 
	AutomatState_FFd3)
	OR (NOT AutomatState_FFd4 AND NOT KeyIn AND NOT AutomatState_FFd2 AND 
	NOT AutomatState_FFd3)
	OR (NOT AutomatState_FFd4 AND AutomatState_FFd1 AND 
	NOT DelayCnt(0) AND NOT DelayCnt(1) AND DelayCnt(2) AND NOT DelayCnt(3) AND 
	NOT DelayCnt(4))
	OR (AutomatState_FFd2 AND AutomatState_FFd1 AND 
	NOT DelayCnt(0) AND NOT DelayCnt(1) AND DelayCnt(2) AND NOT DelayCnt(3) AND 
	NOT DelayCnt(4))
	OR (NOT AutomatState_FFd4 AND AutomatState_FFd2 AND 
	AutomatState_FFd3 AND NOT DelayCnt(0) AND NOT DelayCnt(1) AND DelayCnt(2) AND 
	DelayCnt(3) AND DelayCnt(4))
	OR (AutomatState_FFd4 AND NOT KeyIn AND NOT AutomatState_FFd2 AND 
	AutomatState_FFd3 AND DelayCnt(0) AND DelayCnt(1) AND NOT DelayCnt(2) AND 
	NOT DelayCnt(3) AND NOT DelayCnt(4)));

FTCPE_Cnt10000: FTCPE port map (Cnt1000(0),Cnt1000_T(0),CntClk,NOT Reset,'0','1');
Cnt1000_T(0) <= (NOT Cnt100(1) AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND 
	NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND 
	Cnt10(3) AND NOT Cnt100(2) AND Cnt100(3));

FTCPE_Cnt10001: FTCPE port map (Cnt1000(1),Cnt1000_T(1),CntClk,NOT Reset,'0','1');
Cnt1000_T(1) <= ((NOT Cnt100(1) AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND 
	NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND 
	Cnt10(3) AND NOT Cnt100(2) AND Cnt100(3) AND Cnt1000(1) AND Cnt1000(0))
	OR (NOT Cnt100(1) AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND 
	NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND 
	Cnt10(3) AND NOT Cnt100(2) AND Cnt100(3) AND Cnt1000(0) AND Cnt1000(2))
	OR (NOT Cnt100(1) AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND 
	NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND 
	Cnt10(3) AND NOT Cnt100(2) AND Cnt100(3) AND Cnt1000(0) AND NOT Cnt1000(3)));

FTCPE_Cnt10002: FTCPE port map (Cnt1000(2),Cnt1000_T(2),CntClk,NOT Reset,'0','1');
Cnt1000_T(2) <= (NOT Cnt100(1) AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND 
	NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND 
	Cnt10(3) AND NOT Cnt100(2) AND Cnt100(3) AND Cnt1000(1) AND Cnt1000(0));

FTCPE_Cnt10003: FTCPE port map (Cnt1000(3),Cnt1000_T(3),CntClk,NOT Reset,'0','1');
Cnt1000_T(3) <= ((NOT Cnt100(1) AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND 
	NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND 
	Cnt10(3) AND NOT Cnt100(2) AND Cnt100(3) AND Cnt1000(1) AND Cnt1000(0) AND 
	Cnt1000(2))
	OR (NOT Cnt100(1) AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND 
	NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND 
	Cnt10(3) AND NOT Cnt100(2) AND Cnt100(3) AND NOT Cnt1000(1) AND Cnt1000(0) AND 
	NOT Cnt1000(2) AND Cnt1000(3)));

FTCPE_Cnt1000: FTCPE port map (Cnt100(0),Cnt100_T(0),CntClk,NOT Reset,'0','1');
Cnt100_T(0) <= (Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND 
	Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3));

FTCPE_Cnt1001: FTCPE port map (Cnt100(1),Cnt100_T(1),CntClk,NOT Reset,'0','1');
Cnt100_T(1) <= ((Cnt100(1) AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND 
	NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND 
	Cnt10(3))
	OR (Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND 
	NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3) AND 
	Cnt100(2))
	OR (Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND 
	NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3) AND 
	NOT Cnt100(3)));

FTCPE_Cnt1002: FTCPE port map (Cnt100(2),Cnt100_T(2),CntClk,NOT Reset,'0','1');
Cnt100_T(2) <= (Cnt100(1) AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND 
	NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND 
	Cnt10(3));

FTCPE_Cnt1003: FTCPE port map (Cnt100(3),Cnt100_T(3),CntClk,NOT Reset,'0','1');
Cnt100_T(3) <= ((Cnt100(1) AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND 
	NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND 
	Cnt10(3) AND Cnt100(2))
	OR (NOT Cnt100(1) AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND 
	NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND 
	Cnt10(3) AND NOT Cnt100(2) AND Cnt100(3)));

FTCPE_Cnt100: FTCPE port map (Cnt10(0),Cnt10_T(0),CntClk,NOT Reset,'0','1');
Cnt10_T(0) <= (Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3));

FTCPE_Cnt101: FTCPE port map (Cnt10(1),Cnt10_T(1),CntClk,NOT Reset,'0','1');
Cnt10_T(1) <= ((Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND 
	Cnt1(3) AND Cnt10(1))
	OR (Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND 
	Cnt1(3) AND Cnt10(2))
	OR (Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND 
	Cnt1(3) AND NOT Cnt10(3)));

FTCPE_Cnt102: FTCPE port map (Cnt10(2),Cnt10_T(2),CntClk,NOT Reset,'0','1');
Cnt10_T(2) <= (Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND 
	Cnt1(3) AND Cnt10(1));

FTCPE_Cnt103: FTCPE port map (Cnt10(3),Cnt10_T(3),CntClk,NOT Reset,'0','1');
Cnt10_T(3) <= ((Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND 
	Cnt1(3) AND Cnt10(1) AND Cnt10(2))
	OR (Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND 
	Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3)));

FTCPE_Cnt10: FTCPE port map (Cnt1(0),'0',CntClk,NOT Reset,'0','1');

FTCPE_Cnt11: FTCPE port map (Cnt1(1),Cnt1_T(1),CntClk,NOT Reset,'0','1');
Cnt1_T(1) <= NOT (((NOT Cnt1(0))
	OR (NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3))));

FTCPE_Cnt12: FTCPE port map (Cnt1(2),Cnt1_T(2),CntClk,NOT Reset,'0','1');
Cnt1_T(2) <= (Cnt1(0) AND Cnt1(1));

FTCPE_Cnt13: FTCPE port map (Cnt1(3),Cnt1_T(3),CntClk,NOT Reset,'0','1');
Cnt1_T(3) <= ((Cnt1(0) AND Cnt1(1) AND Cnt1(2))
	OR (Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3)));

FDCPE_CntClk: FDCPE port map (CntClk,CntClk_D,Clk,'0','0','1');
CntClk_D <= ((NOT Reset AND CntClk)
	OR (Reset AND AutomatState_FFd4 AND AutomatState_FFd2 AND 
	NOT AutomatState_FFd3)
	OR (Reset AND NOT AutomatState_FFd4 AND NOT AutomatState_FFd2 AND 
	AutomatState_FFd3));


DSel0 <= (NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1));


DSel1 <= (MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1));


DSel2 <= (NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1));


DSel3 <= (MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1));

FTCPE_DelayCnt0: FTCPE port map (DelayCnt(0),DelayCntEnable,FDiv(5),NOT N_PZ_406,'0','1');

FTCPE_DelayCnt1: FTCPE port map (DelayCnt(1),DelayCnt_T(1),FDiv(5),NOT N_PZ_406,'0','1');
DelayCnt_T(1) <= (DelayCnt(0) AND DelayCntEnable);

FTCPE_DelayCnt2: FTCPE port map (DelayCnt(2),DelayCnt_T(2),FDiv(5),NOT N_PZ_406,'0','1');
DelayCnt_T(2) <= (DelayCnt(0) AND DelayCntEnable AND DelayCnt(1));

FTCPE_DelayCnt3: FTCPE port map (DelayCnt(3),DelayCnt_T(3),FDiv(5),NOT N_PZ_406,'0','1');
DelayCnt_T(3) <= (DelayCnt(0) AND DelayCntEnable AND DelayCnt(1) AND 
	DelayCnt(2));

FTCPE_DelayCnt4: FTCPE port map (DelayCnt(4),DelayCnt_T(4),FDiv(5),NOT N_PZ_406,'0','1');
DelayCnt_T(4) <= (DelayCnt(0) AND DelayCntEnable AND DelayCnt(1) AND 
	DelayCnt(2) AND DelayCnt(3));

FDCPE_DelayCntClear: FDCPE port map (DelayCntClear,DelayCntClear_D,Clk,'0','0','1');
DelayCntClear_D <= NOT (((NOT Reset AND NOT DelayCntClear)
	OR (Reset AND AutomatState_FFd4 AND AutomatState_FFd2 AND 
	NOT AutomatState_FFd1)
	OR (Reset AND AutomatState_FFd4 AND NOT AutomatState_FFd1 AND 
	NOT AutomatState_FFd3)));

FDCPE_DelayCntEnable: FDCPE port map (DelayCntEnable,DelayCntEnable_D,Clk,'0','0','1');
DelayCntEnable_D <= NOT (((NOT Reset AND NOT DelayCntEnable)
	OR (Reset AND AutomatState_FFd4 AND AutomatState_FFd2 AND 
	NOT AutomatState_FFd1)
	OR (Reset AND NOT AutomatState_FFd2 AND NOT AutomatState_FFd1 AND 
	NOT AutomatState_FFd3)));

FTCPE_FClk: FTCPE port map (FClk,FClk_T,NOT Clk,NOT Reset,'0','1');
FClk_T <= (FDivInstance/FDivCnt(0) AND FDivInstance/FDivCnt(1));

FTCPE_FDiv0: FTCPE port map (FDiv(0),'0',FClk,NOT Reset,'0','1');

FTCPE_FDiv1: FTCPE port map (FDiv(1),FDiv(0),FClk,NOT Reset,'0','1');

FTCPE_FDiv2: FTCPE port map (FDiv(2),FDiv_T(2),FClk,NOT Reset,'0','1');
FDiv_T(2) <= (FDiv(0) AND FDiv(1));

FTCPE_FDiv3: FTCPE port map (FDiv(3),FDiv_T(3),FClk,NOT Reset,'0','1');
FDiv_T(3) <= (FDiv(2) AND FDiv(0) AND FDiv(1));

FTCPE_FDiv4: FTCPE port map (FDiv(4),FDiv_T(4),FClk,NOT Reset,'0','1');
FDiv_T(4) <= (FDiv(2) AND FDiv(0) AND FDiv(1) AND FDiv(3));

FTCPE_FDiv5: FTCPE port map (FDiv(5),FDiv_T(5),FClk,NOT Reset,'0','1');
FDiv_T(5) <= (FDiv(2) AND FDiv(0) AND FDiv(1) AND FDiv(3) AND 
	FDiv(4));

FTCPE_FDivInstance/FDivCnt0: FTCPE port map (FDivInstance/FDivCnt(0),'0',NOT Clk,NOT Reset,'0','1');

FTCPE_FDivInstance/FDivCnt1: FTCPE port map (FDivInstance/FDivCnt(1),FDivInstance/FDivCnt(0),NOT Clk,NOT Reset,'0','1');

FTCPE_MuxDisplInstance/SelCnt0: FTCPE port map (MuxDisplInstance/SelCnt(0),'0',FDiv(2),NOT Reset,'0','1');

FTCPE_MuxDisplInstance/SelCnt1: FTCPE port map (MuxDisplInstance/SelCnt(1),MuxDisplInstance/SelCnt(0),FDiv(2),NOT Reset,'0','1');


MuxDisplInstance/Tetr(0) <= ((Cnt100(0) AND DSel2)
	OR (Cnt10(0) AND DSel1)
	OR (Cnt1(0) AND DSel0)
	OR (Cnt1000(0) AND DSel3));


MuxDisplInstance/Tetr(1) <= ((Cnt100(1) AND DSel2)
	OR (Cnt1(1) AND DSel0)
	OR (Cnt10(1) AND DSel1)
	OR (Cnt1000(1) AND DSel3));


MuxDisplInstance/Tetr(2) <= ((Cnt1(2) AND DSel0)
	OR (Cnt10(2) AND DSel1)
	OR (Cnt100(2) AND DSel2)
	OR (Cnt1000(2) AND DSel3));


MuxDisplInstance/Tetr(3) <= ((Cnt1(3) AND DSel0)
	OR (Cnt10(3) AND DSel1)
	OR (Cnt100(3) AND DSel2)
	OR (Cnt1000(3) AND DSel3));


N_PZ_406 <= (Reset AND DelayCntClear);


Seg_A <= NOT ((NOT MuxDisplInstance/Tetr(1) AND 
	MuxDisplInstance/Tetr(0))
	XOR ((NOT MuxDisplInstance/Tetr(1) AND 
	MuxDisplInstance/Tetr(2) AND NOT MuxDisplInstance/Tetr(3))
	OR (MuxDisplInstance/Tetr(0) AND 
	NOT MuxDisplInstance/Tetr(2) AND MuxDisplInstance/Tetr(3))));


Seg_B <= NOT ((NOT MuxDisplInstance/Tetr(0) AND 
	MuxDisplInstance/Tetr(2))
	XOR ((MuxDisplInstance/Tetr(1) AND 
	MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(3))
	OR (NOT MuxDisplInstance/Tetr(1) AND 
	MuxDisplInstance/Tetr(2) AND NOT MuxDisplInstance/Tetr(3))));


Seg_C <= NOT (((MuxDisplInstance/Tetr(1) AND 
	MuxDisplInstance/Tetr(2) AND MuxDisplInstance/Tetr(3))
	OR (NOT MuxDisplInstance/Tetr(0) AND 
	MuxDisplInstance/Tetr(2) AND MuxDisplInstance/Tetr(3))
	OR (MuxDisplInstance/Tetr(1) AND 
	NOT MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(2) AND 
	NOT MuxDisplInstance/Tetr(3))));


Seg_D <= NOT (((MuxDisplInstance/Tetr(1) AND 
	MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(2))
	OR (MuxDisplInstance/Tetr(1) AND 
	NOT MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(2) AND 
	MuxDisplInstance/Tetr(3))
	OR (NOT MuxDisplInstance/Tetr(1) AND 
	MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(2) AND 
	NOT MuxDisplInstance/Tetr(3))
	OR (NOT MuxDisplInstance/Tetr(1) AND 
	NOT MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(2) AND 
	NOT MuxDisplInstance/Tetr(3))));


Seg_E <= NOT (((MuxDisplInstance/Tetr(0) AND 
	NOT MuxDisplInstance/Tetr(3))
	OR (NOT MuxDisplInstance/Tetr(1) AND 
	MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(2))
	OR (NOT MuxDisplInstance/Tetr(1) AND 
	MuxDisplInstance/Tetr(2) AND NOT MuxDisplInstance/Tetr(3))));


Seg_F <= NOT ((MuxDisplInstance/Tetr(0) AND 
	NOT MuxDisplInstance/Tetr(3))
	XOR ((NOT MuxDisplInstance/Tetr(1) AND 
	MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(2))
	OR (MuxDisplInstance/Tetr(1) AND 
	NOT MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(2) AND 
	NOT MuxDisplInstance/Tetr(3))));


Seg_G <= NOT (((NOT MuxDisplInstance/Tetr(1) AND 
	NOT MuxDisplInstance/Tetr(2) AND NOT MuxDisplInstance/Tetr(3))
	OR (MuxDisplInstance/Tetr(1) AND 
	MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(2) AND 
	NOT MuxDisplInstance/Tetr(3))
	OR (NOT MuxDisplInstance/Tetr(1) AND 
	NOT MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(2) AND 
	MuxDisplInstance/Tetr(3))));


Seg_K <= '0';


Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE); 
 FDDCPE (Q,D,C,CLR,PRE,CE); 
 FTCPE (Q,D,C,CLR,PRE,CE); 
 FTDCPE (Q,D,C,CLR,PRE,CE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC2C256-6-VQ100


   --------------------------------------------------  
  /100 98  96  94  92  90  88  86  84  82  80  78  76  \
 |   99  97  95  93  91  89  87  85  83  81  79  77    |
 | 1                                               75  | 
 | 2                                               74  | 
 | 3                                               73  | 
 | 4                                               72  | 
 | 5                                               71  | 
 | 6                                               70  | 
 | 7                                               69  | 
 | 8                                               68  | 
 | 9                                               67  | 
 | 10                                              66  | 
 | 11                                              65  | 
 | 12                                              64  | 
 | 13                XC2C256-6-VQ100               63  | 
 | 14                                              62  | 
 | 15                                              61  | 
 | 16                                              60  | 
 | 17                                              59  | 
 | 18                                              58  | 
 | 19                                              57  | 
 | 20                                              56  | 
 | 21                                              55  | 
 | 22                                              54  | 
 | 23                                              53  | 
 | 24                                              52  | 
 | 25                                              51  | 
 |   27  29  31  33  35  37  39  41  43  45  47  49    |
  \26  28  30  32  34  36  38  40  42  44  46  48  50  /
   --------------------------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 Seg_K                            51 VCCIO-1.8                     
  2 Seg_G                            52 KPR                           
  3 Seg_F                            53 KPR                           
  4 Seg_E                            54 KPR                           
  5 VCCAUX                           55 KeyIn                         
  6 Seg_D                            56 KPR                           
  7 Seg_C                            57 VCC                           
  8 Seg_A                            58 KPR                           
  9 Seg_B                            59 KPR                           
 10 KPR                              60 KPR                           
 11 KPR                              61 KPR                           
 12 KPR                              62 GND                           
 13 KPR                              63 KPR                           
 14 KPR                              64 KPR                           
 15 KPR                              65 Reset                         
 16 KPR                              66 KPR                           
 17 KPR                              67 KPR                           
 18 DSel0                            68 KPR                           
 19 DSel1                            69 GND                           
 20 VCCIO-1.8                        70 KPR                           
 21 GND                              71 KPR                           
 22 Clk                              72 KPR                           
 23 KPR                              73 KPR                           
 24 DSel2                            74 KPR                           
 25 GND                              75 GND                           
 26 VCC                              76 KPR                           
 27 DSel3                            77 KPR                           
 28 KPR                              78 KPR                           
 29 KPR                              79 KPR                           
 30 KPR                              80 KPR                           
 31 GND                              81 KPR                           
 32 KPR                              82 KPR                           
 33 KPR                              83 TDO                           
 34 KPR                              84 GND                           
 35 KPR                              85 KPR                           
 36 KPR                              86 KPR                           
 37 KPR                              87 KPR                           
 38 VCCIO-1.8                        88 VCCIO-1.8                     
 39 KPR                              89 KPR                           
 40 KPR                              90 KPR                           
 41 KPR                              91 KPR                           
 42 KPR                              92 KPR                           
 43 KPR                              93 KPR                           
 44 KPR                              94 KPR                           
 45 TDI                              95 KPR                           
 46 KPR                              96 KPR                           
 47 TMS                              97 KPR                           
 48 TCK                              98 VCCIO-1.8                     
 49 KPR                              99 KPR                           
 50 KPR                             100 GND                           


Legend :  NC  = Not Connected, unbonded pin
        PGND  = Unused I/O configured as additional Ground pin
         KPR  = Unused I/O with weak keeper (leave unconnected)
         WPU  = Unused I/O with weak pull up (leave unconnected)
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
      VCCAUX  = Power supply for JTAG pins
   VCCIO-3.3  = I/O supply voltage for LVTTL, LVCMOS33, SSTL3_I
   VCCIO-2.5  = I/O supply voltage for LVCMOS25, SSTL2_I
   VCCIO-1.8  = I/O supply voltage for LVCMOS18
   VCCIO-1.5  = I/O supply voltage for LVCMOS15, HSTL_I
        VREF  = Reference voltage for indicated input standard
       *VREF  = Reference voltage pin selected by software
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc2c256-6-VQ100
Optimization Method                         : DENSITY
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Set Unused I/O Pin Termination              : KEEPER
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
Enable Input Registers                      : ON
Function Block Fan-in Limit                 : 38
Use DATA_GATE Attribute                     : ON
Set Tristate Outputs to Termination Mode    : KEEPER
Default Voltage Standard for All Outputs    : LVCMOS18
Input Limit                                 : 32
Pterm Limit                                 : 28