Timing Report

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Design Name Clock
Device, Speed (SpeedFile Version) XC2C256, -6 (14.0 Advance Product Specification)
Date Created Sat May 16 21:43:15 2009
Created By Timing Report Generator: version J.36
Copyright Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.
Possible asynchronous logic: Clock pin 'FB5__ctinst/4' has multiple original clock nets 'ModeKeyStatus_MC.Q' 'Context_FFd1_MC.Q' 'Context_FFd2_MC.Q' 'F1Hz_MC.Q'.
Possible asynchronous logic: Clock pin 'Hrs<1>.CLKF' has multiple original clock nets 'ModeKeyStatus_MC.Q' 'Context_FFd1_MC.Q' 'Context_FFd2_MC.Q' 'F1Hz_MC.Q'.
Possible asynchronous logic: Clock pin 'Hrs1<0>.CLKF' has multiple original clock nets 'ModeKeyStatus_MC.Q' 'Context_FFd1_MC.Q' 'Context_FFd2_MC.Q' 'F1Hz_MC.Q'.
Possible asynchronous logic: Clock pin 'Hrs<2>.CLKF' has multiple original clock nets 'ModeKeyStatus_MC.Q' 'Context_FFd1_MC.Q' 'Context_FFd2_MC.Q' 'F1Hz_MC.Q'.
Possible asynchronous logic: Clock pin 'Hrs<3>.CLKF' has multiple original clock nets 'ModeKeyStatus_MC.Q' 'Context_FFd1_MC.Q' 'Context_FFd2_MC.Q' 'F1Hz_MC.Q'.
Possible asynchronous logic: Clock pin 'Hrs<4>.CLKF' has multiple original clock nets 'ModeKeyStatus_MC.Q' 'Context_FFd1_MC.Q' 'Context_FFd2_MC.Q' 'F1Hz_MC.Q'.
Possible asynchronous logic: Clock pin 'Hrs<5>.CLKF' has multiple original clock nets 'ModeKeyStatus_MC.Q' 'Context_FFd1_MC.Q' 'Context_FFd2_MC.Q' 'F1Hz_MC.Q'.
Possible asynchronous logic: Clock pin 'SetupKeyStatus.CLKF' has multiple original clock nets 'SetupKeyInstance/ShRegister<3>_MC.Q' 'SetupKeyInstance/ShRegister<2>_MC.Q' 'SetupKeyInstance/ShRegister<1>_MC.Q' 'SetupKeyInstance/ShRegister<0>_MC.Q'.
Possible asynchronous logic: Clock pin 'ModeKeyStatus.CLKF' has multiple original clock nets 'ModeKeyInstance/ShRegister<3>_MC.Q' 'ModeKeyInstance/ShRegister<2>_MC.Q' 'ModeKeyInstance/ShRegister<1>_MC.Q' 'ModeKeyInstance/ShRegister<0>_MC.Q'.

Performance Summary
Min. Clock Period 14.000 ns.
Max. Clock Frequency (fSYSTEM) 71.429 MHz.
Limited by Cycle Time for ModeKeyStatus_MC.Q
Clock to Setup (tCYC) 14.000 ns.
Setup to Clock at the Pad (tSU) 1.600 ns.
Clock Pad to Output Pad Delay (tCO) 39.500 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS1000 0.0 0.0 0 0
TS1001 0.0 0.0 0 0
TS1002 0.0 0.0 0 0
TS1003 0.0 0.0 0 0
TS1004 0.0 0.0 0 0
TS1005 0.0 0.0 0 0
TS1006 0.0 0.0 0 0
TS1007 0.0 0.0 0 0
TS1008 0.0 0.0 0 0
TS1009 0.0 0.0 0 0
TS1010 0.0 0.0 0 0
TS1011 0.0 0.0 0 0
TS1012 0.0 0.0 0 0
TS1013 0.0 0.0 0 0
TS1014 0.0 0.0 0 0
TS1015 0.0 0.0 0 0
AUTO_TS_F2F 0.0 14.0 358 358
AUTO_TS_P2P 0.0 39.5 12 12
AUTO_TS_P2F 0.0 5.1 3 3
AUTO_TS_F2P 0.0 20.7 160 160


Constraint: TS1000

Description: PERIOD:PERIOD_ModeKeyStatus_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1001

Description: PERIOD:PERIOD_Context_FFd1_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1002

Description: PERIOD:PERIOD_Context_FFd2_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1003

Description: PERIOD:PERIOD_SetupKeyInstance/ShRegister<3>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1004

Description: PERIOD:PERIOD_SetupKeyInstance/ShRegister<2>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1005

Description: PERIOD:PERIOD_SetupKeyInstance/ShRegister<1>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1006

Description: PERIOD:PERIOD_SetupKeyInstance/ShRegister<0>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1007

Description: PERIOD:PERIOD_FDiv<4>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1008

Description: PERIOD:PERIOD_ModeKeyInstance/ShRegister<3>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1009

Description: PERIOD:PERIOD_ModeKeyInstance/ShRegister<2>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1010

Description: PERIOD:PERIOD_ModeKeyInstance/ShRegister<1>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1011

Description: PERIOD:PERIOD_ModeKeyInstance/ShRegister<0>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1012

Description: PERIOD:PERIOD_F1Hz_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1013

Description: PERIOD:PERIOD_Clk:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1014

Description: PERIOD:PERIOD_FClk_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1015

Description: PERIOD:PERIOD_FDiv<3>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
Min<2>.Q to Min<2>.D 0.000 14.000 -14.000
Min<3>.Q to Min<2>.D 0.000 14.000 -14.000
Min<4>.Q to Min<2>.D 0.000 14.000 -14.000


Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
Clk to Seg_A 0.000 39.500 -39.500
Clk to Seg_B 0.000 39.500 -39.500
Clk to Seg_C 0.000 39.500 -39.500


Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
ModeKeyInp to ModeKeyInstance/ShRegister<0>.D 0.000 5.100 -5.100
SetupKeyInp to SetupKeyInstance/ShRegister<0>.D 0.000 5.100 -5.100
Clk to Clk.GCK 0.000 1.800 -1.800


Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
Min<2>.Q to Seg_A 0.000 20.700 -20.700
Min<2>.Q to Seg_B 0.000 20.700 -20.700
Min<2>.Q to Seg_C 0.000 20.700 -20.700



Number of constraints not met: 4

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
ModeKeyStatus_MC.Q 71.429 Limited by Cycle Time for ModeKeyStatus_MC.Q
Context_FFd1_MC.Q 71.429 Limited by Cycle Time for Context_FFd1_MC.Q
Context_FFd2_MC.Q 71.429 Limited by Cycle Time for Context_FFd2_MC.Q
SetupKeyInstance/ShRegister<3>_MC.Q 83.333 Limited by Clock Pulse Width for SetupKeyInstance/ShRegister<3>_MC.Q
SetupKeyInstance/ShRegister<2>_MC.Q 83.333 Limited by Clock Pulse Width for SetupKeyInstance/ShRegister<2>_MC.Q
SetupKeyInstance/ShRegister<1>_MC.Q 83.333 Limited by Clock Pulse Width for SetupKeyInstance/ShRegister<1>_MC.Q
SetupKeyInstance/ShRegister<0>_MC.Q 83.333 Limited by Clock Pulse Width for SetupKeyInstance/ShRegister<0>_MC.Q
FDiv<4>_MC.Q 212.766 Limited by Cycle Time for FDiv<4>_MC.Q
ModeKeyInstance/ShRegister<3>_MC.Q 83.333 Limited by Clock Pulse Width for ModeKeyInstance/ShRegister<3>_MC.Q
ModeKeyInstance/ShRegister<2>_MC.Q 83.333 Limited by Clock Pulse Width for ModeKeyInstance/ShRegister<2>_MC.Q
ModeKeyInstance/ShRegister<1>_MC.Q 83.333 Limited by Clock Pulse Width for ModeKeyInstance/ShRegister<1>_MC.Q
ModeKeyInstance/ShRegister<0>_MC.Q 83.333 Limited by Clock Pulse Width for ModeKeyInstance/ShRegister<0>_MC.Q
F1Hz_MC.Q 71.429 Limited by Cycle Time for F1Hz_MC.Q
Clk 232.558 Limited by Cycle Time for Clk
FClk_MC.Q 212.766 Limited by Cycle Time for FClk_MC.Q
FDiv<3>_MC.Q 83.333 Limited by Clock Pulse Width for FDiv<3>_MC.Q

Setup/Hold Times for Clocks

Setup/Hold Times for Clock FDiv<4>.Q
Source Pad Setup to clk (edge) Hold to clk (edge)
ModeKeyInp 1.600 0.000
SetupKeyInp 1.600 0.000


Clock to Pad Timing

Clock Clk to Pad
Destination Pad Clock (edge) to Pad
Seg_A 39.500
Seg_B 39.500
Seg_C 39.500
Seg_D 39.500
Seg_E 39.500
Seg_F 39.500
Seg_G 39.500
Seg_K 14.500
DSel0 14.200
DSel1 14.200
DSel2 14.200
DSel3 14.200


Clock to Setup Times for Clocks

Clock to Setup for clock ModeKeyStatus.Q
Source Destination Delay
Min<2>.Q Min<2>.D 14.000
Min<3>.Q Min<2>.D 14.000
Min<4>.Q Min<2>.D 14.000
Min<5>.Q Min<2>.D 14.000
Min1<0>.Q Hrs1<0>.D 8.000
Min1<0>.Q Hrs<1>.D 8.000
Min1<0>.Q Hrs<2>.D 8.000
Min1<0>.Q Hrs<3>.D 8.000
Min1<0>.Q Hrs<4>.D 8.000
Min1<0>.Q Hrs<5>.D 8.000
Min<1>.Q Hrs1<0>.D 8.000
Min<1>.Q Hrs<1>.D 8.000
Min<1>.Q Hrs<2>.D 8.000
Min<1>.Q Hrs<3>.D 8.000
Min<1>.Q Hrs<4>.D 8.000
Min<1>.Q Hrs<5>.D 8.000
Min<2>.Q Hrs1<0>.D 8.000
Min<2>.Q Hrs<1>.D 8.000
Min<2>.Q Hrs<2>.D 8.000
Min<2>.Q Hrs<3>.D 8.000
Min<2>.Q Hrs<4>.D 8.000
Min<2>.Q Hrs<5>.D 8.000
Min<3>.Q Hrs1<0>.D 8.000
Min<3>.Q Hrs<1>.D 8.000
Min<3>.Q Hrs<2>.D 8.000
Min<3>.Q Hrs<3>.D 8.000
Min<3>.Q Hrs<4>.D 8.000
Min<3>.Q Hrs<5>.D 8.000
Min<4>.Q Hrs1<0>.D 8.000
Min<4>.Q Hrs<1>.D 8.000
Min<4>.Q Hrs<2>.D 8.000
Min<4>.Q Hrs<3>.D 8.000
Min<4>.Q Hrs<4>.D 8.000
Min<4>.Q Hrs<5>.D 8.000
Min<5>.Q Hrs1<0>.D 8.000
Min<5>.Q Hrs<1>.D 8.000
Min<5>.Q Hrs<2>.D 8.000
Min<5>.Q Hrs<3>.D 8.000
Min<5>.Q Hrs<4>.D 8.000
Min<5>.Q Hrs<5>.D 8.000
Hrs1<0>.Q Hrs<1>.D 5.000
Hrs1<0>.Q Hrs<2>.D 5.000
Hrs1<0>.Q Hrs<3>.D 5.000
Hrs1<0>.Q Hrs<4>.D 5.000
Hrs1<0>.Q Hrs<5>.D 5.000
Hrs<1>.Q Hrs<2>.D 5.000
Hrs<1>.Q Hrs<3>.D 5.000
Hrs<1>.Q Hrs<4>.D 5.000
Hrs<1>.Q Hrs<5>.D 5.000
Hrs<2>.Q Hrs<3>.D 5.000
Hrs<2>.Q Hrs<4>.D 5.000
Hrs<2>.Q Hrs<5>.D 5.000
Hrs<3>.Q Hrs<3>.D 5.000
Hrs<3>.Q Hrs<4>.D 5.000
Hrs<3>.Q Hrs<5>.D 5.000
Hrs<4>.Q Hrs<3>.D 5.000
Hrs<4>.Q Hrs<4>.D 5.000
Hrs<4>.Q Hrs<5>.D 5.000
Hrs<5>.Q Hrs<3>.D 5.000
Hrs<5>.Q Hrs<4>.D 5.000
Min1<0>.Q Min<2>.D 5.000
Min1<0>.Q Min<3>.D 5.000
Min1<0>.Q Min<4>.D 5.000
Min1<0>.Q Min<5>.D 5.000
Min<1>.Q Min<2>.D 5.000
Min<1>.Q Min<3>.D 5.000
Min<1>.Q Min<4>.D 5.000
Min<1>.Q Min<5>.D 5.000
Min<2>.Q Min<3>.D 5.000
Min<2>.Q Min<4>.D 5.000
Min<2>.Q Min<5>.D 5.000
Min<3>.Q Min<3>.D 5.000
Min<3>.Q Min<4>.D 5.000
Min<3>.Q Min<5>.D 5.000
Min<4>.Q Min<3>.D 5.000
Min<4>.Q Min<4>.D 5.000
Min<4>.Q Min<5>.D 5.000
Min<5>.Q Min<3>.D 5.000
Min<5>.Q Min<4>.D 5.000
Min<5>.Q Min<5>.D 5.000
Min1<0>.Q Min<1>.D 4.700

Clock to Setup for clock Context_FFd1.Q
Source Destination Delay
Min<2>.Q Min<2>.D 14.000
Min<3>.Q Min<2>.D 14.000
Min<4>.Q Min<2>.D 14.000
Min<5>.Q Min<2>.D 14.000
Min1<0>.Q Hrs1<0>.D 8.000
Min1<0>.Q Hrs<1>.D 8.000
Min1<0>.Q Hrs<2>.D 8.000
Min1<0>.Q Hrs<3>.D 8.000
Min1<0>.Q Hrs<4>.D 8.000
Min1<0>.Q Hrs<5>.D 8.000
Min<1>.Q Hrs1<0>.D 8.000
Min<1>.Q Hrs<1>.D 8.000
Min<1>.Q Hrs<2>.D 8.000
Min<1>.Q Hrs<3>.D 8.000
Min<1>.Q Hrs<4>.D 8.000
Min<1>.Q Hrs<5>.D 8.000
Min<2>.Q Hrs1<0>.D 8.000
Min<2>.Q Hrs<1>.D 8.000
Min<2>.Q Hrs<2>.D 8.000
Min<2>.Q Hrs<3>.D 8.000
Min<2>.Q Hrs<4>.D 8.000
Min<2>.Q Hrs<5>.D 8.000
Min<3>.Q Hrs1<0>.D 8.000
Min<3>.Q Hrs<1>.D 8.000
Min<3>.Q Hrs<2>.D 8.000
Min<3>.Q Hrs<3>.D 8.000
Min<3>.Q Hrs<4>.D 8.000
Min<3>.Q Hrs<5>.D 8.000
Min<4>.Q Hrs1<0>.D 8.000
Min<4>.Q Hrs<1>.D 8.000
Min<4>.Q Hrs<2>.D 8.000
Min<4>.Q Hrs<3>.D 8.000
Min<4>.Q Hrs<4>.D 8.000
Min<4>.Q Hrs<5>.D 8.000
Min<5>.Q Hrs1<0>.D 8.000
Min<5>.Q Hrs<1>.D 8.000
Min<5>.Q Hrs<2>.D 8.000
Min<5>.Q Hrs<3>.D 8.000
Min<5>.Q Hrs<4>.D 8.000
Min<5>.Q Hrs<5>.D 8.000
Hrs1<0>.Q Hrs<1>.D 5.000
Hrs1<0>.Q Hrs<2>.D 5.000
Hrs1<0>.Q Hrs<3>.D 5.000
Hrs1<0>.Q Hrs<4>.D 5.000
Hrs1<0>.Q Hrs<5>.D 5.000
Hrs<1>.Q Hrs<2>.D 5.000
Hrs<1>.Q Hrs<3>.D 5.000
Hrs<1>.Q Hrs<4>.D 5.000
Hrs<1>.Q Hrs<5>.D 5.000
Hrs<2>.Q Hrs<3>.D 5.000
Hrs<2>.Q Hrs<4>.D 5.000
Hrs<2>.Q Hrs<5>.D 5.000
Hrs<3>.Q Hrs<3>.D 5.000
Hrs<3>.Q Hrs<4>.D 5.000
Hrs<3>.Q Hrs<5>.D 5.000
Hrs<4>.Q Hrs<3>.D 5.000
Hrs<4>.Q Hrs<4>.D 5.000
Hrs<4>.Q Hrs<5>.D 5.000
Hrs<5>.Q Hrs<3>.D 5.000
Hrs<5>.Q Hrs<4>.D 5.000
Min1<0>.Q Min<2>.D 5.000
Min1<0>.Q Min<3>.D 5.000
Min1<0>.Q Min<4>.D 5.000
Min1<0>.Q Min<5>.D 5.000
Min<1>.Q Min<2>.D 5.000
Min<1>.Q Min<3>.D 5.000
Min<1>.Q Min<4>.D 5.000
Min<1>.Q Min<5>.D 5.000
Min<2>.Q Min<3>.D 5.000
Min<2>.Q Min<4>.D 5.000
Min<2>.Q Min<5>.D 5.000
Min<3>.Q Min<3>.D 5.000
Min<3>.Q Min<4>.D 5.000
Min<3>.Q Min<5>.D 5.000
Min<4>.Q Min<3>.D 5.000
Min<4>.Q Min<4>.D 5.000
Min<4>.Q Min<5>.D 5.000
Min<5>.Q Min<3>.D 5.000
Min<5>.Q Min<4>.D 5.000
Min<5>.Q Min<5>.D 5.000
Min1<0>.Q Min<1>.D 4.700

Clock to Setup for clock Context_FFd2.Q
Source Destination Delay
Min<2>.Q Min<2>.D 14.000
Min<3>.Q Min<2>.D 14.000
Min<4>.Q Min<2>.D 14.000
Min<5>.Q Min<2>.D 14.000
Min1<0>.Q Hrs1<0>.D 8.000
Min1<0>.Q Hrs<1>.D 8.000
Min1<0>.Q Hrs<2>.D 8.000
Min1<0>.Q Hrs<3>.D 8.000
Min1<0>.Q Hrs<4>.D 8.000
Min1<0>.Q Hrs<5>.D 8.000
Min<1>.Q Hrs1<0>.D 8.000
Min<1>.Q Hrs<1>.D 8.000
Min<1>.Q Hrs<2>.D 8.000
Min<1>.Q Hrs<3>.D 8.000
Min<1>.Q Hrs<4>.D 8.000
Min<1>.Q Hrs<5>.D 8.000
Min<2>.Q Hrs1<0>.D 8.000
Min<2>.Q Hrs<1>.D 8.000
Min<2>.Q Hrs<2>.D 8.000
Min<2>.Q Hrs<3>.D 8.000
Min<2>.Q Hrs<4>.D 8.000
Min<2>.Q Hrs<5>.D 8.000
Min<3>.Q Hrs1<0>.D 8.000
Min<3>.Q Hrs<1>.D 8.000
Min<3>.Q Hrs<2>.D 8.000
Min<3>.Q Hrs<3>.D 8.000
Min<3>.Q Hrs<4>.D 8.000
Min<3>.Q Hrs<5>.D 8.000
Min<4>.Q Hrs1<0>.D 8.000
Min<4>.Q Hrs<1>.D 8.000
Min<4>.Q Hrs<2>.D 8.000
Min<4>.Q Hrs<3>.D 8.000
Min<4>.Q Hrs<4>.D 8.000
Min<4>.Q Hrs<5>.D 8.000
Min<5>.Q Hrs1<0>.D 8.000
Min<5>.Q Hrs<1>.D 8.000
Min<5>.Q Hrs<2>.D 8.000
Min<5>.Q Hrs<3>.D 8.000
Min<5>.Q Hrs<4>.D 8.000
Min<5>.Q Hrs<5>.D 8.000
Hrs1<0>.Q Hrs<1>.D 5.000
Hrs1<0>.Q Hrs<2>.D 5.000
Hrs1<0>.Q Hrs<3>.D 5.000
Hrs1<0>.Q Hrs<4>.D 5.000
Hrs1<0>.Q Hrs<5>.D 5.000
Hrs<1>.Q Hrs<2>.D 5.000
Hrs<1>.Q Hrs<3>.D 5.000
Hrs<1>.Q Hrs<4>.D 5.000
Hrs<1>.Q Hrs<5>.D 5.000
Hrs<2>.Q Hrs<3>.D 5.000
Hrs<2>.Q Hrs<4>.D 5.000
Hrs<2>.Q Hrs<5>.D 5.000
Hrs<3>.Q Hrs<3>.D 5.000
Hrs<3>.Q Hrs<4>.D 5.000
Hrs<3>.Q Hrs<5>.D 5.000
Hrs<4>.Q Hrs<3>.D 5.000
Hrs<4>.Q Hrs<4>.D 5.000
Hrs<4>.Q Hrs<5>.D 5.000
Hrs<5>.Q Hrs<3>.D 5.000
Hrs<5>.Q Hrs<4>.D 5.000
Min1<0>.Q Min<2>.D 5.000
Min1<0>.Q Min<3>.D 5.000
Min1<0>.Q Min<4>.D 5.000
Min1<0>.Q Min<5>.D 5.000
Min<1>.Q Min<2>.D 5.000
Min<1>.Q Min<3>.D 5.000
Min<1>.Q Min<4>.D 5.000
Min<1>.Q Min<5>.D 5.000
Min<2>.Q Min<3>.D 5.000
Min<2>.Q Min<4>.D 5.000
Min<2>.Q Min<5>.D 5.000
Min<3>.Q Min<3>.D 5.000
Min<3>.Q Min<4>.D 5.000
Min<3>.Q Min<5>.D 5.000
Min<4>.Q Min<3>.D 5.000
Min<4>.Q Min<4>.D 5.000
Min<4>.Q Min<5>.D 5.000
Min<5>.Q Min<3>.D 5.000
Min<5>.Q Min<4>.D 5.000
Min<5>.Q Min<5>.D 5.000
Min1<0>.Q Min<1>.D 4.700

Clock to Setup for clock FDiv<4>.Q
Source Destination Delay
ModeKeyInstance/ShRegister<0>.Q ModeKeyInstance/ShRegister<1>.D 4.700
ModeKeyInstance/ShRegister<1>.Q ModeKeyInstance/ShRegister<2>.D 4.700
ModeKeyInstance/ShRegister<2>.Q ModeKeyInstance/ShRegister<3>.D 4.700
SetupKeyInstance/ShRegister<0>.Q SetupKeyInstance/ShRegister<1>.D 4.700
SetupKeyInstance/ShRegister<1>.Q SetupKeyInstance/ShRegister<2>.D 4.700
SetupKeyInstance/ShRegister<2>.Q SetupKeyInstance/ShRegister<3>.D 4.700

Clock to Setup for clock F1Hz.Q
Source Destination Delay
Min<2>.Q Min<2>.D 14.000
Min<3>.Q Min<2>.D 14.000
Min<4>.Q Min<2>.D 14.000
Min<5>.Q Min<2>.D 14.000
Min1<0>.Q Hrs1<0>.D 8.000
Min1<0>.Q Hrs<1>.D 8.000
Min1<0>.Q Hrs<2>.D 8.000
Min1<0>.Q Hrs<3>.D 8.000
Min1<0>.Q Hrs<4>.D 8.000
Min1<0>.Q Hrs<5>.D 8.000
Min<1>.Q Hrs1<0>.D 8.000
Min<1>.Q Hrs<1>.D 8.000
Min<1>.Q Hrs<2>.D 8.000
Min<1>.Q Hrs<3>.D 8.000
Min<1>.Q Hrs<4>.D 8.000
Min<1>.Q Hrs<5>.D 8.000
Min<2>.Q Hrs1<0>.D 8.000
Min<2>.Q Hrs<1>.D 8.000
Min<2>.Q Hrs<2>.D 8.000
Min<2>.Q Hrs<3>.D 8.000
Min<2>.Q Hrs<4>.D 8.000
Min<2>.Q Hrs<5>.D 8.000
Min<3>.Q Hrs1<0>.D 8.000
Min<3>.Q Hrs<1>.D 8.000
Min<3>.Q Hrs<2>.D 8.000
Min<3>.Q Hrs<3>.D 8.000
Min<3>.Q Hrs<4>.D 8.000
Min<3>.Q Hrs<5>.D 8.000
Min<4>.Q Hrs1<0>.D 8.000
Min<4>.Q Hrs<1>.D 8.000
Min<4>.Q Hrs<2>.D 8.000
Min<4>.Q Hrs<3>.D 8.000
Min<4>.Q Hrs<4>.D 8.000
Min<4>.Q Hrs<5>.D 8.000
Min<5>.Q Hrs1<0>.D 8.000
Min<5>.Q Hrs<1>.D 8.000
Min<5>.Q Hrs<2>.D 8.000
Min<5>.Q Hrs<3>.D 8.000
Min<5>.Q Hrs<4>.D 8.000
Min<5>.Q Hrs<5>.D 8.000
Sec1<0>.Q Hrs1<0>.D 8.000
Sec1<0>.Q Hrs<1>.D 8.000
Sec1<0>.Q Hrs<2>.D 8.000
Sec1<0>.Q Hrs<3>.D 8.000
Sec1<0>.Q Hrs<4>.D 8.000
Sec1<0>.Q Hrs<5>.D 8.000
Sec1<0>.Q Min<2>.D 8.000
Sec1<0>.Q Min<3>.D 8.000
Sec1<0>.Q Min<4>.D 8.000
Sec1<0>.Q Min<5>.D 8.000
Sec<1>.Q Hrs1<0>.D 8.000
Sec<1>.Q Hrs<1>.D 8.000
Sec<1>.Q Hrs<2>.D 8.000
Sec<1>.Q Hrs<3>.D 8.000
Sec<1>.Q Hrs<4>.D 8.000
Sec<1>.Q Hrs<5>.D 8.000
Sec<1>.Q Min<2>.D 8.000
Sec<1>.Q Min<3>.D 8.000
Sec<1>.Q Min<4>.D 8.000
Sec<1>.Q Min<5>.D 8.000
Sec<2>.Q Hrs1<0>.D 8.000
Sec<2>.Q Hrs<1>.D 8.000
Sec<2>.Q Hrs<2>.D 8.000
Sec<2>.Q Hrs<3>.D 8.000
Sec<2>.Q Hrs<4>.D 8.000
Sec<2>.Q Hrs<5>.D 8.000
Sec<2>.Q Min<2>.D 8.000
Sec<2>.Q Min<3>.D 8.000
Sec<2>.Q Min<4>.D 8.000
Sec<2>.Q Min<5>.D 8.000
Sec<2>.Q Sec<2>.D 8.000
Sec<3>.Q Hrs1<0>.D 8.000
Sec<3>.Q Hrs<1>.D 8.000
Sec<3>.Q Hrs<2>.D 8.000
Sec<3>.Q Hrs<3>.D 8.000
Sec<3>.Q Hrs<4>.D 8.000
Sec<3>.Q Hrs<5>.D 8.000
Sec<3>.Q Min<2>.D 8.000
Sec<3>.Q Min<3>.D 8.000
Sec<3>.Q Min<4>.D 8.000
Sec<3>.Q Min<5>.D 8.000
Sec<3>.Q Sec<2>.D 8.000
Sec<4>.Q Hrs1<0>.D 8.000
Sec<4>.Q Hrs<1>.D 8.000
Sec<4>.Q Hrs<2>.D 8.000
Sec<4>.Q Hrs<3>.D 8.000
Sec<4>.Q Hrs<4>.D 8.000
Sec<4>.Q Hrs<5>.D 8.000
Sec<4>.Q Min<2>.D 8.000
Sec<4>.Q Min<3>.D 8.000
Sec<4>.Q Min<4>.D 8.000
Sec<4>.Q Min<5>.D 8.000
Sec<4>.Q Sec<2>.D 8.000
Sec<5>.Q Hrs1<0>.D 8.000
Sec<5>.Q Hrs<1>.D 8.000
Sec<5>.Q Hrs<2>.D 8.000
Sec<5>.Q Hrs<3>.D 8.000
Sec<5>.Q Hrs<4>.D 8.000
Sec<5>.Q Hrs<5>.D 8.000
Sec<5>.Q Min<2>.D 8.000
Sec<5>.Q Min<3>.D 8.000
Sec<5>.Q Min<4>.D 8.000
Sec<5>.Q Min<5>.D 8.000
Sec<5>.Q Sec<2>.D 8.000
Sec1<0>.Q Min1<0>.D 7.700
Sec1<0>.Q Min<1>.D 7.700
Sec<1>.Q Min1<0>.D 7.700
Sec<1>.Q Min<1>.D 7.700
Sec<2>.Q Min1<0>.D 7.700
Sec<2>.Q Min<1>.D 7.700
Sec<3>.Q Min1<0>.D 7.700
Sec<3>.Q Min<1>.D 7.700
Sec<4>.Q Min1<0>.D 7.700
Sec<4>.Q Min<1>.D 7.700
Sec<5>.Q Min1<0>.D 7.700
Sec<5>.Q Min<1>.D 7.700
Hrs1<0>.Q Hrs<1>.D 5.000
Hrs1<0>.Q Hrs<2>.D 5.000
Hrs1<0>.Q Hrs<3>.D 5.000
Hrs1<0>.Q Hrs<4>.D 5.000
Hrs1<0>.Q Hrs<5>.D 5.000
Hrs<1>.Q Hrs<2>.D 5.000
Hrs<1>.Q Hrs<3>.D 5.000
Hrs<1>.Q Hrs<4>.D 5.000
Hrs<1>.Q Hrs<5>.D 5.000
Hrs<2>.Q Hrs<3>.D 5.000
Hrs<2>.Q Hrs<4>.D 5.000
Hrs<2>.Q Hrs<5>.D 5.000
Hrs<3>.Q Hrs<3>.D 5.000
Hrs<3>.Q Hrs<4>.D 5.000
Hrs<3>.Q Hrs<5>.D 5.000
Hrs<4>.Q Hrs<3>.D 5.000
Hrs<4>.Q Hrs<4>.D 5.000
Hrs<4>.Q Hrs<5>.D 5.000
Hrs<5>.Q Hrs<3>.D 5.000
Hrs<5>.Q Hrs<4>.D 5.000
Min1<0>.Q Min<2>.D 5.000
Min1<0>.Q Min<3>.D 5.000
Min1<0>.Q Min<4>.D 5.000
Min1<0>.Q Min<5>.D 5.000
Min<1>.Q Min<2>.D 5.000
Min<1>.Q Min<3>.D 5.000
Min<1>.Q Min<4>.D 5.000
Min<1>.Q Min<5>.D 5.000
Min<2>.Q Min<3>.D 5.000
Min<2>.Q Min<4>.D 5.000
Min<2>.Q Min<5>.D 5.000
Min<3>.Q Min<3>.D 5.000
Min<3>.Q Min<4>.D 5.000
Min<3>.Q Min<5>.D 5.000
Min<4>.Q Min<3>.D 5.000
Min<4>.Q Min<4>.D 5.000
Min<4>.Q Min<5>.D 5.000
Min<5>.Q Min<3>.D 5.000
Min<5>.Q Min<4>.D 5.000
Min<5>.Q Min<5>.D 5.000
Sec1<0>.Q Sec<2>.D 5.000
Sec1<0>.Q Sec<3>.D 5.000
Sec1<0>.Q Sec<4>.D 5.000
Sec1<0>.Q Sec<5>.D 5.000
Sec<1>.Q Sec<2>.D 5.000
Sec<1>.Q Sec<3>.D 5.000
Sec<1>.Q Sec<4>.D 5.000
Sec<1>.Q Sec<5>.D 5.000
Sec<2>.Q Sec<3>.D 5.000
Sec<2>.Q Sec<4>.D 5.000
Sec<2>.Q Sec<5>.D 5.000
Sec<3>.Q Sec<3>.D 5.000
Sec<3>.Q Sec<4>.D 5.000
Sec<3>.Q Sec<5>.D 5.000
Sec<4>.Q Sec<3>.D 5.000
Sec<4>.Q Sec<4>.D 5.000
Sec<4>.Q Sec<5>.D 5.000
Sec<5>.Q Sec<3>.D 5.000
Sec<5>.Q Sec<4>.D 5.000
Sec<5>.Q Sec<5>.D 5.000
Min1<0>.Q Min<1>.D 4.700
Sec1<0>.Q Sec<1>.D 4.700

Clock to Setup for clock Clk
Source Destination Delay
MachineState_FFd1.Q Context_FFd1.CE 4.300
MachineState_FFd1.Q Context_FFd2.CE 4.300
MachineState_FFd2.Q Context_FFd1.CE 4.300
MachineState_FFd2.Q Context_FFd2.CE 4.300
Context_FFd1.Q Context_FFd2.D 4.200
Context_FFd1.Q DispMode.D 4.200
Context_FFd2.Q Context_FFd1.D 4.200
Context_FFd2.Q DispMode.D 4.200
DispMode.Q DispMode.D 4.200
MachineState_FFd1.Q DispMode.D 4.200
MachineState_FFd1.Q MachineState_FFd1.D 4.200
MachineState_FFd1.Q MachineState_FFd2.D 4.200
MachineState_FFd2.Q DispMode.D 4.200
MachineState_FFd2.Q MachineState_FFd1.D 4.200
MachineState_FFd2.Q MachineState_FFd2.D 4.200
F1HzDivInstance/FDivCnt<0>.Q F1Hz.D 3.900
F1HzDivInstance/FDivCnt<0>.Q F1HzDivInstance/FDivCnt<10>.D 3.900
F1HzDivInstance/FDivCnt<0>.Q F1HzDivInstance/FDivCnt<11>.D 3.900
F1HzDivInstance/FDivCnt<0>.Q F1HzDivInstance/FDivCnt<12>.D 3.900
F1HzDivInstance/FDivCnt<0>.Q F1HzDivInstance/FDivCnt<13>.D 3.900
F1HzDivInstance/FDivCnt<0>.Q F1HzDivInstance/FDivCnt<1>.D 3.900
F1HzDivInstance/FDivCnt<0>.Q F1HzDivInstance/FDivCnt<2>.D 3.900
F1HzDivInstance/FDivCnt<0>.Q F1HzDivInstance/FDivCnt<3>.D 3.900
F1HzDivInstance/FDivCnt<0>.Q F1HzDivInstance/FDivCnt<4>.D 3.900
F1HzDivInstance/FDivCnt<0>.Q F1HzDivInstance/FDivCnt<5>.D 3.900
F1HzDivInstance/FDivCnt<0>.Q F1HzDivInstance/FDivCnt<6>.D 3.900
F1HzDivInstance/FDivCnt<0>.Q F1HzDivInstance/FDivCnt<7>.D 3.900
F1HzDivInstance/FDivCnt<0>.Q F1HzDivInstance/FDivCnt<8>.D 3.900
F1HzDivInstance/FDivCnt<0>.Q F1HzDivInstance/FDivCnt<9>.D 3.900
F1HzDivInstance/FDivCnt<10>.Q F1Hz.D 3.900
F1HzDivInstance/FDivCnt<10>.Q F1HzDivInstance/FDivCnt<11>.D 3.900
F1HzDivInstance/FDivCnt<10>.Q F1HzDivInstance/FDivCnt<12>.D 3.900
F1HzDivInstance/FDivCnt<10>.Q F1HzDivInstance/FDivCnt<13>.D 3.900
F1HzDivInstance/FDivCnt<11>.Q F1Hz.D 3.900
F1HzDivInstance/FDivCnt<11>.Q F1HzDivInstance/FDivCnt<12>.D 3.900
F1HzDivInstance/FDivCnt<11>.Q F1HzDivInstance/FDivCnt<13>.D 3.900
F1HzDivInstance/FDivCnt<12>.Q F1Hz.D 3.900
F1HzDivInstance/FDivCnt<12>.Q F1HzDivInstance/FDivCnt<13>.D 3.900
F1HzDivInstance/FDivCnt<13>.Q F1Hz.D 3.900
F1HzDivInstance/FDivCnt<1>.Q F1Hz.D 3.900
F1HzDivInstance/FDivCnt<1>.Q F1HzDivInstance/FDivCnt<10>.D 3.900
F1HzDivInstance/FDivCnt<1>.Q F1HzDivInstance/FDivCnt<11>.D 3.900
F1HzDivInstance/FDivCnt<1>.Q F1HzDivInstance/FDivCnt<12>.D 3.900
F1HzDivInstance/FDivCnt<1>.Q F1HzDivInstance/FDivCnt<13>.D 3.900
F1HzDivInstance/FDivCnt<1>.Q F1HzDivInstance/FDivCnt<2>.D 3.900
F1HzDivInstance/FDivCnt<1>.Q F1HzDivInstance/FDivCnt<3>.D 3.900
F1HzDivInstance/FDivCnt<1>.Q F1HzDivInstance/FDivCnt<4>.D 3.900
F1HzDivInstance/FDivCnt<1>.Q F1HzDivInstance/FDivCnt<5>.D 3.900
F1HzDivInstance/FDivCnt<1>.Q F1HzDivInstance/FDivCnt<6>.D 3.900
F1HzDivInstance/FDivCnt<1>.Q F1HzDivInstance/FDivCnt<7>.D 3.900
F1HzDivInstance/FDivCnt<1>.Q F1HzDivInstance/FDivCnt<8>.D 3.900
F1HzDivInstance/FDivCnt<1>.Q F1HzDivInstance/FDivCnt<9>.D 3.900
F1HzDivInstance/FDivCnt<2>.Q F1Hz.D 3.900
F1HzDivInstance/FDivCnt<2>.Q F1HzDivInstance/FDivCnt<10>.D 3.900
F1HzDivInstance/FDivCnt<2>.Q F1HzDivInstance/FDivCnt<11>.D 3.900
F1HzDivInstance/FDivCnt<2>.Q F1HzDivInstance/FDivCnt<12>.D 3.900
F1HzDivInstance/FDivCnt<2>.Q F1HzDivInstance/FDivCnt<13>.D 3.900
F1HzDivInstance/FDivCnt<2>.Q F1HzDivInstance/FDivCnt<3>.D 3.900
F1HzDivInstance/FDivCnt<2>.Q F1HzDivInstance/FDivCnt<4>.D 3.900
F1HzDivInstance/FDivCnt<2>.Q F1HzDivInstance/FDivCnt<5>.D 3.900
F1HzDivInstance/FDivCnt<2>.Q F1HzDivInstance/FDivCnt<6>.D 3.900
F1HzDivInstance/FDivCnt<2>.Q F1HzDivInstance/FDivCnt<7>.D 3.900
F1HzDivInstance/FDivCnt<2>.Q F1HzDivInstance/FDivCnt<8>.D 3.900
F1HzDivInstance/FDivCnt<2>.Q F1HzDivInstance/FDivCnt<9>.D 3.900
F1HzDivInstance/FDivCnt<3>.Q F1Hz.D 3.900
F1HzDivInstance/FDivCnt<3>.Q F1HzDivInstance/FDivCnt<10>.D 3.900
F1HzDivInstance/FDivCnt<3>.Q F1HzDivInstance/FDivCnt<11>.D 3.900
F1HzDivInstance/FDivCnt<3>.Q F1HzDivInstance/FDivCnt<12>.D 3.900
F1HzDivInstance/FDivCnt<3>.Q F1HzDivInstance/FDivCnt<13>.D 3.900
F1HzDivInstance/FDivCnt<3>.Q F1HzDivInstance/FDivCnt<4>.D 3.900
F1HzDivInstance/FDivCnt<3>.Q F1HzDivInstance/FDivCnt<5>.D 3.900
F1HzDivInstance/FDivCnt<3>.Q F1HzDivInstance/FDivCnt<6>.D 3.900
F1HzDivInstance/FDivCnt<3>.Q F1HzDivInstance/FDivCnt<7>.D 3.900
F1HzDivInstance/FDivCnt<3>.Q F1HzDivInstance/FDivCnt<8>.D 3.900
F1HzDivInstance/FDivCnt<3>.Q F1HzDivInstance/FDivCnt<9>.D 3.900
F1HzDivInstance/FDivCnt<4>.Q F1Hz.D 3.900
F1HzDivInstance/FDivCnt<4>.Q F1HzDivInstance/FDivCnt<10>.D 3.900
F1HzDivInstance/FDivCnt<4>.Q F1HzDivInstance/FDivCnt<11>.D 3.900
F1HzDivInstance/FDivCnt<4>.Q F1HzDivInstance/FDivCnt<12>.D 3.900
F1HzDivInstance/FDivCnt<4>.Q F1HzDivInstance/FDivCnt<13>.D 3.900
F1HzDivInstance/FDivCnt<4>.Q F1HzDivInstance/FDivCnt<5>.D 3.900
F1HzDivInstance/FDivCnt<4>.Q F1HzDivInstance/FDivCnt<6>.D 3.900
F1HzDivInstance/FDivCnt<4>.Q F1HzDivInstance/FDivCnt<7>.D 3.900
F1HzDivInstance/FDivCnt<4>.Q F1HzDivInstance/FDivCnt<8>.D 3.900
F1HzDivInstance/FDivCnt<4>.Q F1HzDivInstance/FDivCnt<9>.D 3.900
F1HzDivInstance/FDivCnt<5>.Q F1Hz.D 3.900
F1HzDivInstance/FDivCnt<5>.Q F1HzDivInstance/FDivCnt<10>.D 3.900
F1HzDivInstance/FDivCnt<5>.Q F1HzDivInstance/FDivCnt<11>.D 3.900
F1HzDivInstance/FDivCnt<5>.Q F1HzDivInstance/FDivCnt<12>.D 3.900
F1HzDivInstance/FDivCnt<5>.Q F1HzDivInstance/FDivCnt<13>.D 3.900
F1HzDivInstance/FDivCnt<5>.Q F1HzDivInstance/FDivCnt<6>.D 3.900
F1HzDivInstance/FDivCnt<5>.Q F1HzDivInstance/FDivCnt<7>.D 3.900
F1HzDivInstance/FDivCnt<5>.Q F1HzDivInstance/FDivCnt<8>.D 3.900
F1HzDivInstance/FDivCnt<5>.Q F1HzDivInstance/FDivCnt<9>.D 3.900
F1HzDivInstance/FDivCnt<6>.Q F1Hz.D 3.900
F1HzDivInstance/FDivCnt<6>.Q F1HzDivInstance/FDivCnt<10>.D 3.900
F1HzDivInstance/FDivCnt<6>.Q F1HzDivInstance/FDivCnt<11>.D 3.900
F1HzDivInstance/FDivCnt<6>.Q F1HzDivInstance/FDivCnt<12>.D 3.900
F1HzDivInstance/FDivCnt<6>.Q F1HzDivInstance/FDivCnt<13>.D 3.900
F1HzDivInstance/FDivCnt<6>.Q F1HzDivInstance/FDivCnt<7>.D 3.900
F1HzDivInstance/FDivCnt<6>.Q F1HzDivInstance/FDivCnt<8>.D 3.900
F1HzDivInstance/FDivCnt<6>.Q F1HzDivInstance/FDivCnt<9>.D 3.900
F1HzDivInstance/FDivCnt<7>.Q F1Hz.D 3.900
F1HzDivInstance/FDivCnt<7>.Q F1HzDivInstance/FDivCnt<10>.D 3.900
F1HzDivInstance/FDivCnt<7>.Q F1HzDivInstance/FDivCnt<11>.D 3.900
F1HzDivInstance/FDivCnt<7>.Q F1HzDivInstance/FDivCnt<12>.D 3.900
F1HzDivInstance/FDivCnt<7>.Q F1HzDivInstance/FDivCnt<13>.D 3.900
F1HzDivInstance/FDivCnt<7>.Q F1HzDivInstance/FDivCnt<8>.D 3.900
F1HzDivInstance/FDivCnt<7>.Q F1HzDivInstance/FDivCnt<9>.D 3.900
F1HzDivInstance/FDivCnt<8>.Q F1Hz.D 3.900
F1HzDivInstance/FDivCnt<8>.Q F1HzDivInstance/FDivCnt<10>.D 3.900
F1HzDivInstance/FDivCnt<8>.Q F1HzDivInstance/FDivCnt<11>.D 3.900
F1HzDivInstance/FDivCnt<8>.Q F1HzDivInstance/FDivCnt<12>.D 3.900
F1HzDivInstance/FDivCnt<8>.Q F1HzDivInstance/FDivCnt<13>.D 3.900
F1HzDivInstance/FDivCnt<8>.Q F1HzDivInstance/FDivCnt<9>.D 3.900
F1HzDivInstance/FDivCnt<9>.Q F1Hz.D 3.900
F1HzDivInstance/FDivCnt<9>.Q F1HzDivInstance/FDivCnt<10>.D 3.900
F1HzDivInstance/FDivCnt<9>.Q F1HzDivInstance/FDivCnt<11>.D 3.900
F1HzDivInstance/FDivCnt<9>.Q F1HzDivInstance/FDivCnt<12>.D 3.900
F1HzDivInstance/FDivCnt<9>.Q F1HzDivInstance/FDivCnt<13>.D 3.900
FDivInstance/FDivCnt<0>.Q FClk.D 3.900
FDivInstance/FDivCnt<0>.Q FDivInstance/FDivCnt<1>.D 3.900
FDivInstance/FDivCnt<1>.Q FClk.D 3.900

Clock to Setup for clock FClk.Q
Source Destination Delay
FDiv<0>.Q FDiv<1>.D 4.700
FDiv<0>.Q FDiv<2>.D 4.700
FDiv<0>.Q FDiv<3>.D 4.700
FDiv<0>.Q FDiv<4>.D 4.700
FDiv<1>.Q FDiv<2>.D 4.700
FDiv<1>.Q FDiv<3>.D 4.700
FDiv<1>.Q FDiv<4>.D 4.700
FDiv<2>.Q FDiv<3>.D 4.700
FDiv<2>.Q FDiv<4>.D 4.700
FDiv<3>.Q FDiv<4>.D 4.700

Clock to Setup for clock FDiv<3>.Q
Source Destination Delay
MuxDisplInstance/SelCnt<0>.Q MuxDisplInstance/SelCnt<1>.D 5.000


Pad to Pad List

Source Pad Destination Pad Delay



Number of paths analyzed: 533
Number of Timing errors: 533
Analysis Completed: Sat May 16 21:43:15 2009