Timing Report

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Design Name Stoper
Device, Speed (SpeedFile Version) XC2C256, -6 (14.0 Advance Product Specification)
Date Created Sat May 16 21:34:28 2009
Created By Timing Report Generator: version J.36
Copyright Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.
Possible asynchronous logic: Clock pin 'FB14__ctinst/4' has multiple original clock nets 'Key0Instance/ShRegister<3>_MC.Q' 'Key0Instance/ShRegister<2>_MC.Q' 'Key0Instance/ShRegister<1>_MC.Q' 'Key0Instance/ShRegister<0>_MC.Q'.

Performance Summary
Min. Clock Period 12.000 ns.
Max. Clock Frequency (fSYSTEM) 83.333 MHz.
Limited by Clock Pulse Width for FClk_MC.Q
Clock to Setup (tCYC) 6.900 ns.
Setup to Clock at the Pad (tSU) 2.800 ns.
Clock Pad to Output Pad Delay (tCO) 20.200 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS1000 0.0 0.0 0 0
TS1001 0.0 0.0 0 0
TS1002 0.0 0.0 0 0
TS1003 0.0 0.0 0 0
TS1004 0.0 0.0 0 0
TS1005 0.0 0.0 0 0
TS1006 0.0 0.0 0 0
TS1007 0.0 0.0 0 0
TS1008 0.0 0.0 0 0
AUTO_TS_F2F 0.0 6.9 338 338
AUTO_TS_P2P 0.0 20.2 14 14
AUTO_TS_P2F 0.0 5.1 4 4
AUTO_TS_F2P 0.0 11.4 138 138


Constraint: TS1000

Description: PERIOD:PERIOD_TimeDiv<13>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1001

Description: PERIOD:PERIOD_FDiv<2>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1002

Description: PERIOD:PERIOD_Key0Instance/ShRegister<3>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1003

Description: PERIOD:PERIOD_Key0Instance/ShRegister<2>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1004

Description: PERIOD:PERIOD_Key0Instance/ShRegister<1>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1005

Description: PERIOD:PERIOD_Key0Instance/ShRegister<0>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1006

Description: PERIOD:PERIOD_Clk:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1007

Description: PERIOD:PERIOD_FClk_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1008

Description: PERIOD:PERIOD_FDiv<3>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
RunStatusLed.Q to TimeDiv<10>.D 0.000 6.900 -6.900
RunStatusLed.Q to TimeDiv<13>.D 0.000 6.900 -6.900
RunStatusLed.Q to TimeDiv<8>.D 0.000 6.900 -6.900


Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
Clk to Seg_A 0.000 20.200 -20.200
Clk to Seg_B 0.000 20.200 -20.200
Clk to Seg_C 0.000 20.200 -20.200


Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
PushKeyIn to Key0Instance/ShRegister<0>.D 0.000 5.100 -5.100
Reset to RunStatusLed.CE 0.000 4.600 -4.600
Reset to Clear.D 0.000 4.500 -4.500
Clk to Clk.GCK 0.000 1.800 -1.800


Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
MuxDisplInstance/SelCnt<0>.Q to Seg_A 0.000 11.400 -11.400
MuxDisplInstance/SelCnt<0>.Q to Seg_B 0.000 11.400 -11.400
MuxDisplInstance/SelCnt<0>.Q to Seg_C 0.000 11.400 -11.400



Number of constraints not met: 4

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
TimeDiv<13>_MC.Q 200.000 Limited by Cycle Time for TimeDiv<13>_MC.Q
FDiv<2>_MC.Q 212.766 Limited by Cycle Time for FDiv<2>_MC.Q
Key0Instance/ShRegister<3>_MC.Q 454.545 Limited by Clock Pulse Width for Key0Instance/ShRegister<3>_MC.Q
Key0Instance/ShRegister<2>_MC.Q 454.545 Limited by Clock Pulse Width for Key0Instance/ShRegister<2>_MC.Q
Key0Instance/ShRegister<1>_MC.Q 454.545 Limited by Clock Pulse Width for Key0Instance/ShRegister<1>_MC.Q
Key0Instance/ShRegister<0>_MC.Q 454.545 Limited by Clock Pulse Width for Key0Instance/ShRegister<0>_MC.Q
Clk 144.928 Limited by Cycle Time for Clk
FClk_MC.Q 83.333 Limited by Clock Pulse Width for FClk_MC.Q
FDiv<3>_MC.Q 83.333 Limited by Clock Pulse Width for FDiv<3>_MC.Q

Setup/Hold Times for Clocks

Setup/Hold Times for Clock FDiv<2>.Q
Source Pad Setup to clk (edge) Hold to clk (edge)
PushKeyIn 1.600 0.000

Setup/Hold Times for Clock Clk
Source Pad Setup to clk (edge) Hold to clk (edge)
Reset 2.800 0.000


Clock to Pad Timing

Clock Clk to Pad
Destination Pad Clock (edge) to Pad
Seg_A 20.200
Seg_B 20.200
Seg_C 20.200
Seg_D 20.200
Seg_E 20.200
Seg_F 20.200
Seg_G 20.200
KeyLed 15.000
DSel0 14.200
DSel1 14.200
DSel2 14.200
DSel3 14.200
Seg_K 14.200
RunStatusLed 4.500


Clock to Setup Times for Clocks

Clock to Setup for clock TimeDiv<13>.Q
Source Destination Delay
Cnt1000<0>.Q Cnt1000<1>.D 5.000
Cnt1000<0>.Q Cnt1000<3>.D 5.000
Cnt1000<1>.Q Cnt1000<1>.D 5.000
Cnt1000<1>.Q Cnt1000<3>.D 5.000
Cnt1000<2>.Q Cnt1000<1>.D 5.000
Cnt1000<2>.Q Cnt1000<3>.D 5.000
Cnt1000<3>.Q Cnt1000<1>.D 5.000
Cnt1000<3>.Q Cnt1000<3>.D 5.000
Cnt100<0>.Q Cnt1000<1>.D 5.000
Cnt100<0>.Q Cnt1000<3>.D 5.000
Cnt100<0>.Q Cnt100<1>.D 5.000
Cnt100<0>.Q Cnt100<3>.D 5.000
Cnt100<1>.Q Cnt1000<1>.D 5.000
Cnt100<1>.Q Cnt1000<3>.D 5.000
Cnt100<1>.Q Cnt100<1>.D 5.000
Cnt100<1>.Q Cnt100<3>.D 5.000
Cnt100<2>.Q Cnt1000<1>.D 5.000
Cnt100<2>.Q Cnt1000<3>.D 5.000
Cnt100<2>.Q Cnt100<1>.D 5.000
Cnt100<2>.Q Cnt100<3>.D 5.000
Cnt100<3>.Q Cnt1000<1>.D 5.000
Cnt100<3>.Q Cnt1000<3>.D 5.000
Cnt100<3>.Q Cnt100<1>.D 5.000
Cnt100<3>.Q Cnt100<3>.D 5.000
Cnt10<0>.Q Cnt1000<1>.D 5.000
Cnt10<0>.Q Cnt1000<3>.D 5.000
Cnt10<0>.Q Cnt100<1>.D 5.000
Cnt10<0>.Q Cnt100<3>.D 5.000
Cnt10<0>.Q Cnt10<1>.D 5.000
Cnt10<0>.Q Cnt10<3>.D 5.000
Cnt10<1>.Q Cnt1000<1>.D 5.000
Cnt10<1>.Q Cnt1000<3>.D 5.000
Cnt10<1>.Q Cnt100<1>.D 5.000
Cnt10<1>.Q Cnt100<3>.D 5.000
Cnt10<1>.Q Cnt10<1>.D 5.000
Cnt10<1>.Q Cnt10<3>.D 5.000
Cnt10<2>.Q Cnt1000<1>.D 5.000
Cnt10<2>.Q Cnt1000<3>.D 5.000
Cnt10<2>.Q Cnt100<1>.D 5.000
Cnt10<2>.Q Cnt100<3>.D 5.000
Cnt10<2>.Q Cnt10<1>.D 5.000
Cnt10<2>.Q Cnt10<3>.D 5.000
Cnt10<3>.Q Cnt1000<1>.D 5.000
Cnt10<3>.Q Cnt1000<3>.D 5.000
Cnt10<3>.Q Cnt100<1>.D 5.000
Cnt10<3>.Q Cnt100<3>.D 5.000
Cnt10<3>.Q Cnt10<1>.D 5.000
Cnt10<3>.Q Cnt10<3>.D 5.000
Cnt1<0>.Q Cnt1000<1>.D 5.000
Cnt1<0>.Q Cnt1000<3>.D 5.000
Cnt1<0>.Q Cnt100<1>.D 5.000
Cnt1<0>.Q Cnt100<3>.D 5.000
Cnt1<0>.Q Cnt10<1>.D 5.000
Cnt1<0>.Q Cnt10<3>.D 5.000
Cnt1<0>.Q Cnt1<1>.D 5.000
Cnt1<0>.Q Cnt1<3>.D 5.000
Cnt1<1>.Q Cnt1000<1>.D 5.000
Cnt1<1>.Q Cnt1000<3>.D 5.000
Cnt1<1>.Q Cnt100<1>.D 5.000
Cnt1<1>.Q Cnt100<3>.D 5.000
Cnt1<1>.Q Cnt10<1>.D 5.000
Cnt1<1>.Q Cnt10<3>.D 5.000
Cnt1<1>.Q Cnt1<1>.D 5.000
Cnt1<1>.Q Cnt1<3>.D 5.000
Cnt1<2>.Q Cnt1000<1>.D 5.000
Cnt1<2>.Q Cnt1000<3>.D 5.000
Cnt1<2>.Q Cnt100<1>.D 5.000
Cnt1<2>.Q Cnt100<3>.D 5.000
Cnt1<2>.Q Cnt10<1>.D 5.000
Cnt1<2>.Q Cnt10<3>.D 5.000
Cnt1<2>.Q Cnt1<1>.D 5.000
Cnt1<2>.Q Cnt1<3>.D 5.000
Cnt1<3>.Q Cnt1000<1>.D 5.000
Cnt1<3>.Q Cnt1000<3>.D 5.000
Cnt1<3>.Q Cnt100<1>.D 5.000
Cnt1<3>.Q Cnt100<3>.D 5.000
Cnt1<3>.Q Cnt10<1>.D 5.000
Cnt1<3>.Q Cnt10<3>.D 5.000
Cnt1<3>.Q Cnt1<1>.D 5.000
Cnt1<3>.Q Cnt1<3>.D 5.000
Cnt1000<0>.Q Cnt1000<2>.D 4.700
Cnt1000<1>.Q Cnt1000<2>.D 4.700
Cnt100<0>.Q Cnt1000<0>.D 4.700
Cnt100<0>.Q Cnt1000<2>.D 4.700
Cnt100<0>.Q Cnt100<2>.D 4.700
Cnt100<1>.Q Cnt1000<0>.D 4.700
Cnt100<1>.Q Cnt1000<2>.D 4.700
Cnt100<1>.Q Cnt100<2>.D 4.700
Cnt100<2>.Q Cnt1000<0>.D 4.700
Cnt100<2>.Q Cnt1000<2>.D 4.700
Cnt100<3>.Q Cnt1000<0>.D 4.700
Cnt100<3>.Q Cnt1000<2>.D 4.700
Cnt10<0>.Q Cnt1000<0>.D 4.700
Cnt10<0>.Q Cnt1000<2>.D 4.700
Cnt10<0>.Q Cnt100<0>.D 4.700
Cnt10<0>.Q Cnt100<2>.D 4.700
Cnt10<0>.Q Cnt10<2>.D 4.700
Cnt10<1>.Q Cnt1000<0>.D 4.700
Cnt10<1>.Q Cnt1000<2>.D 4.700
Cnt10<1>.Q Cnt100<0>.D 4.700
Cnt10<1>.Q Cnt100<2>.D 4.700
Cnt10<1>.Q Cnt10<2>.D 4.700
Cnt10<2>.Q Cnt1000<0>.D 4.700
Cnt10<2>.Q Cnt1000<2>.D 4.700
Cnt10<2>.Q Cnt100<0>.D 4.700
Cnt10<2>.Q Cnt100<2>.D 4.700
Cnt10<3>.Q Cnt1000<0>.D 4.700
Cnt10<3>.Q Cnt1000<2>.D 4.700
Cnt10<3>.Q Cnt100<0>.D 4.700
Cnt10<3>.Q Cnt100<2>.D 4.700
Cnt1<0>.Q Cnt1000<0>.D 4.700
Cnt1<0>.Q Cnt1000<2>.D 4.700
Cnt1<0>.Q Cnt100<0>.D 4.700
Cnt1<0>.Q Cnt100<2>.D 4.700
Cnt1<0>.Q Cnt10<0>.D 4.700
Cnt1<0>.Q Cnt10<2>.D 4.700
Cnt1<0>.Q Cnt1<2>.D 4.700
Cnt1<1>.Q Cnt1000<0>.D 4.700
Cnt1<1>.Q Cnt1000<2>.D 4.700
Cnt1<1>.Q Cnt100<0>.D 4.700
Cnt1<1>.Q Cnt100<2>.D 4.700
Cnt1<1>.Q Cnt10<0>.D 4.700
Cnt1<1>.Q Cnt10<2>.D 4.700
Cnt1<1>.Q Cnt1<2>.D 4.700
Cnt1<2>.Q Cnt1000<0>.D 4.700
Cnt1<2>.Q Cnt1000<2>.D 4.700
Cnt1<2>.Q Cnt100<0>.D 4.700
Cnt1<2>.Q Cnt100<2>.D 4.700
Cnt1<2>.Q Cnt10<0>.D 4.700
Cnt1<2>.Q Cnt10<2>.D 4.700
Cnt1<3>.Q Cnt1000<0>.D 4.700
Cnt1<3>.Q Cnt1000<2>.D 4.700
Cnt1<3>.Q Cnt100<0>.D 4.700
Cnt1<3>.Q Cnt100<2>.D 4.700
Cnt1<3>.Q Cnt10<0>.D 4.700
Cnt1<3>.Q Cnt10<2>.D 4.700

Clock to Setup for clock FDiv<2>.Q
Source Destination Delay
Key0Instance/ShRegister<0>.Q Key0Instance/ShRegister<1>.D 4.700
Key0Instance/ShRegister<1>.Q Key0Instance/ShRegister<2>.D 4.700
Key0Instance/ShRegister<2>.Q Key0Instance/ShRegister<3>.D 4.700

Clock to Setup for clock Clk
Source Destination Delay
RunStatusLed.Q TimeDiv<10>.D 6.900
RunStatusLed.Q TimeDiv<13>.D 6.900
RunStatusLed.Q TimeDiv<8>.D 6.900
RunStatusLed.Q TimeDiv<9>.D 6.900
TimeDiv<0>.Q TimeDiv<10>.D 6.900
TimeDiv<0>.Q TimeDiv<13>.D 6.900
TimeDiv<0>.Q TimeDiv<8>.D 6.900
TimeDiv<0>.Q TimeDiv<9>.D 6.900
TimeDiv<1>.Q TimeDiv<10>.D 6.900
TimeDiv<1>.Q TimeDiv<13>.D 6.900
TimeDiv<1>.Q TimeDiv<8>.D 6.900
TimeDiv<1>.Q TimeDiv<9>.D 6.900
TimeDiv<2>.Q TimeDiv<10>.D 6.900
TimeDiv<2>.Q TimeDiv<13>.D 6.900
TimeDiv<2>.Q TimeDiv<8>.D 6.900
TimeDiv<2>.Q TimeDiv<9>.D 6.900
TimeDiv<3>.Q TimeDiv<10>.D 6.900
TimeDiv<3>.Q TimeDiv<13>.D 6.900
TimeDiv<3>.Q TimeDiv<8>.D 6.900
TimeDiv<3>.Q TimeDiv<9>.D 6.900
TimeDiv<4>.Q TimeDiv<10>.D 6.900
TimeDiv<4>.Q TimeDiv<13>.D 6.900
TimeDiv<4>.Q TimeDiv<8>.D 6.900
TimeDiv<4>.Q TimeDiv<9>.D 6.900
TimeDiv<5>.Q TimeDiv<10>.D 6.900
TimeDiv<5>.Q TimeDiv<13>.D 6.900
TimeDiv<5>.Q TimeDiv<8>.D 6.900
TimeDiv<5>.Q TimeDiv<9>.D 6.900
TimeDiv<6>.Q TimeDiv<10>.D 6.900
TimeDiv<6>.Q TimeDiv<13>.D 6.900
TimeDiv<6>.Q TimeDiv<8>.D 6.900
TimeDiv<6>.Q TimeDiv<9>.D 6.900
TimeDiv<7>.Q TimeDiv<10>.D 6.900
TimeDiv<7>.Q TimeDiv<13>.D 6.900
TimeDiv<7>.Q TimeDiv<8>.D 6.900
TimeDiv<7>.Q TimeDiv<9>.D 6.900
RunStatusLed.Q TimeDiv<11>.D 6.600
RunStatusLed.Q TimeDiv<12>.D 6.600
TimeDiv<0>.Q TimeDiv<11>.D 6.600
TimeDiv<0>.Q TimeDiv<12>.D 6.600
TimeDiv<1>.Q TimeDiv<11>.D 6.600
TimeDiv<1>.Q TimeDiv<12>.D 6.600
TimeDiv<2>.Q TimeDiv<11>.D 6.600
TimeDiv<2>.Q TimeDiv<12>.D 6.600
TimeDiv<3>.Q TimeDiv<11>.D 6.600
TimeDiv<3>.Q TimeDiv<12>.D 6.600
TimeDiv<4>.Q TimeDiv<11>.D 6.600
TimeDiv<4>.Q TimeDiv<12>.D 6.600
TimeDiv<5>.Q TimeDiv<11>.D 6.600
TimeDiv<5>.Q TimeDiv<12>.D 6.600
TimeDiv<6>.Q TimeDiv<11>.D 6.600
TimeDiv<6>.Q TimeDiv<12>.D 6.600
TimeDiv<7>.Q TimeDiv<11>.D 6.600
TimeDiv<7>.Q TimeDiv<12>.D 6.600
AutomatState_FFd1.Q AutomatState_FFd1.D 4.200
AutomatState_FFd1.Q AutomatState_FFd2.D 4.200
AutomatState_FFd1.Q AutomatState_FFd3.D 4.200
AutomatState_FFd1.Q Clear.D 4.200
AutomatState_FFd2.Q AutomatState_FFd1.D 4.200
AutomatState_FFd2.Q AutomatState_FFd2.D 4.200
AutomatState_FFd2.Q AutomatState_FFd3.D 4.200
AutomatState_FFd2.Q Clear.D 4.200
AutomatState_FFd2.Q RunStatusLed.D 4.200
AutomatState_FFd3.Q AutomatState_FFd1.D 4.200
AutomatState_FFd3.Q AutomatState_FFd2.D 4.200
AutomatState_FFd3.Q AutomatState_FFd3.D 4.200
AutomatState_FFd3.Q Clear.D 4.200
Clear.Q Clear.D 4.200
RunStatusLed.Q TimeDiv<4>.D 4.200
TimeDiv<0>.Q TimeDiv<4>.D 4.200
TimeDiv<10>.Q TimeDiv<10>.D 4.200
TimeDiv<10>.Q TimeDiv<13>.D 4.200
TimeDiv<10>.Q TimeDiv<4>.D 4.200
TimeDiv<10>.Q TimeDiv<8>.D 4.200
TimeDiv<10>.Q TimeDiv<9>.D 4.200
TimeDiv<11>.Q TimeDiv<10>.D 4.200
TimeDiv<11>.Q TimeDiv<13>.D 4.200
TimeDiv<11>.Q TimeDiv<4>.D 4.200
TimeDiv<11>.Q TimeDiv<8>.D 4.200
TimeDiv<11>.Q TimeDiv<9>.D 4.200
TimeDiv<12>.Q TimeDiv<10>.D 4.200
TimeDiv<12>.Q TimeDiv<13>.D 4.200
TimeDiv<12>.Q TimeDiv<4>.D 4.200
TimeDiv<12>.Q TimeDiv<8>.D 4.200
TimeDiv<12>.Q TimeDiv<9>.D 4.200
TimeDiv<13>.Q TimeDiv<10>.D 4.200
TimeDiv<13>.Q TimeDiv<13>.D 4.200
TimeDiv<13>.Q TimeDiv<4>.D 4.200
TimeDiv<13>.Q TimeDiv<8>.D 4.200
TimeDiv<13>.Q TimeDiv<9>.D 4.200
TimeDiv<1>.Q TimeDiv<4>.D 4.200
TimeDiv<2>.Q TimeDiv<4>.D 4.200
TimeDiv<3>.Q TimeDiv<4>.D 4.200
TimeDiv<4>.Q TimeDiv<4>.D 4.200
TimeDiv<5>.Q TimeDiv<4>.D 4.200
TimeDiv<6>.Q TimeDiv<4>.D 4.200
TimeDiv<7>.Q TimeDiv<4>.D 4.200
TimeDiv<8>.Q TimeDiv<10>.D 4.200
TimeDiv<8>.Q TimeDiv<13>.D 4.200
TimeDiv<8>.Q TimeDiv<4>.D 4.200
TimeDiv<8>.Q TimeDiv<8>.D 4.200
TimeDiv<8>.Q TimeDiv<9>.D 4.200
TimeDiv<9>.Q TimeDiv<10>.D 4.200
TimeDiv<9>.Q TimeDiv<13>.D 4.200
TimeDiv<9>.Q TimeDiv<4>.D 4.200
TimeDiv<9>.Q TimeDiv<8>.D 4.200
TimeDiv<9>.Q TimeDiv<9>.D 4.200
FDivInstance/FDivCnt<0>.Q FClk.D 3.900
FDivInstance/FDivCnt<0>.Q FDivInstance/FDivCnt<1>.D 3.900
FDivInstance/FDivCnt<0>.Q FDivInstance/FDivCnt<2>.D 3.900
FDivInstance/FDivCnt<0>.Q FDivInstance/FDivCnt<3>.D 3.900
FDivInstance/FDivCnt<0>.Q FDivInstance/FDivCnt<4>.D 3.900
FDivInstance/FDivCnt<0>.Q FDivInstance/FDivCnt<5>.D 3.900
FDivInstance/FDivCnt<0>.Q FDivInstance/FDivCnt<6>.D 3.900
FDivInstance/FDivCnt<1>.Q FClk.D 3.900
FDivInstance/FDivCnt<1>.Q FDivInstance/FDivCnt<2>.D 3.900
FDivInstance/FDivCnt<1>.Q FDivInstance/FDivCnt<3>.D 3.900
FDivInstance/FDivCnt<1>.Q FDivInstance/FDivCnt<4>.D 3.900
FDivInstance/FDivCnt<1>.Q FDivInstance/FDivCnt<5>.D 3.900
FDivInstance/FDivCnt<1>.Q FDivInstance/FDivCnt<6>.D 3.900
FDivInstance/FDivCnt<2>.Q FClk.D 3.900
FDivInstance/FDivCnt<2>.Q FDivInstance/FDivCnt<3>.D 3.900
FDivInstance/FDivCnt<2>.Q FDivInstance/FDivCnt<4>.D 3.900
FDivInstance/FDivCnt<2>.Q FDivInstance/FDivCnt<5>.D 3.900
FDivInstance/FDivCnt<2>.Q FDivInstance/FDivCnt<6>.D 3.900
FDivInstance/FDivCnt<3>.Q FClk.D 3.900
FDivInstance/FDivCnt<3>.Q FDivInstance/FDivCnt<4>.D 3.900
FDivInstance/FDivCnt<3>.Q FDivInstance/FDivCnt<5>.D 3.900
FDivInstance/FDivCnt<3>.Q FDivInstance/FDivCnt<6>.D 3.900
FDivInstance/FDivCnt<4>.Q FClk.D 3.900
FDivInstance/FDivCnt<4>.Q FDivInstance/FDivCnt<5>.D 3.900
FDivInstance/FDivCnt<4>.Q FDivInstance/FDivCnt<6>.D 3.900
FDivInstance/FDivCnt<5>.Q FClk.D 3.900
FDivInstance/FDivCnt<5>.Q FDivInstance/FDivCnt<6>.D 3.900
FDivInstance/FDivCnt<6>.Q FClk.D 3.900
RunStatusLed.Q TimeDiv<0>.D 3.900
RunStatusLed.Q TimeDiv<1>.D 3.900
RunStatusLed.Q TimeDiv<2>.D 3.900
RunStatusLed.Q TimeDiv<3>.D 3.900
RunStatusLed.Q TimeDiv<5>.D 3.900
RunStatusLed.Q TimeDiv<6>.D 3.900
RunStatusLed.Q TimeDiv<7>.D 3.900
TimeDiv<0>.Q TimeDiv<1>.D 3.900
TimeDiv<0>.Q TimeDiv<2>.D 3.900
TimeDiv<0>.Q TimeDiv<3>.D 3.900
TimeDiv<0>.Q TimeDiv<5>.D 3.900
TimeDiv<0>.Q TimeDiv<6>.D 3.900
TimeDiv<0>.Q TimeDiv<7>.D 3.900
TimeDiv<10>.Q TimeDiv<11>.D 3.900
TimeDiv<10>.Q TimeDiv<12>.D 3.900
TimeDiv<11>.Q TimeDiv<12>.D 3.900
TimeDiv<1>.Q TimeDiv<2>.D 3.900
TimeDiv<1>.Q TimeDiv<3>.D 3.900
TimeDiv<1>.Q TimeDiv<5>.D 3.900
TimeDiv<1>.Q TimeDiv<6>.D 3.900
TimeDiv<1>.Q TimeDiv<7>.D 3.900
TimeDiv<2>.Q TimeDiv<3>.D 3.900
TimeDiv<2>.Q TimeDiv<5>.D 3.900
TimeDiv<2>.Q TimeDiv<6>.D 3.900
TimeDiv<2>.Q TimeDiv<7>.D 3.900
TimeDiv<3>.Q TimeDiv<5>.D 3.900
TimeDiv<3>.Q TimeDiv<6>.D 3.900
TimeDiv<3>.Q TimeDiv<7>.D 3.900
TimeDiv<4>.Q TimeDiv<5>.D 3.900
TimeDiv<4>.Q TimeDiv<6>.D 3.900
TimeDiv<4>.Q TimeDiv<7>.D 3.900
TimeDiv<5>.Q TimeDiv<6>.D 3.900
TimeDiv<5>.Q TimeDiv<7>.D 3.900
TimeDiv<6>.Q TimeDiv<7>.D 3.900
TimeDiv<8>.Q TimeDiv<11>.D 3.900
TimeDiv<8>.Q TimeDiv<12>.D 3.900
TimeDiv<9>.Q TimeDiv<11>.D 3.900
TimeDiv<9>.Q TimeDiv<12>.D 3.900

Clock to Setup for clock FClk.Q
Source Destination Delay
FDiv<0>.Q FDiv<3>.D 5.000
FDiv<1>.Q FDiv<3>.D 5.000
FDiv<2>.Q FDiv<3>.D 5.000
FDiv<0>.Q FDiv<1>.D 4.700
FDiv<0>.Q FDiv<2>.D 4.700
FDiv<1>.Q FDiv<2>.D 4.700

Clock to Setup for clock FDiv<3>.Q
Source Destination Delay
MuxDisplInstance/SelCnt<0>.Q MuxDisplInstance/SelCnt<1>.D 5.000


Pad to Pad List

Source Pad Destination Pad Delay



Number of paths analyzed: 494
Number of Timing errors: 494
Analysis Completed: Sat May 16 21:34:28 2009