Timing Report

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Design Name TMeas
Device, Speed (SpeedFile Version) XC2C256, -6 (14.0 Advance Product Specification)
Date Created Mon Mar 22 14:00:39 2010
Created By Timing Report Generator: version J.36
Copyright Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.
Possible asynchronous logic: Clock pin 'GoKeyStatus.CLKF' has multiple original clock nets 'Key0Instance/ShRegister<3>_MC.Q' 'Key0Instance/ShRegister<2>_MC.Q' 'Key0Instance/ShRegister<1>_MC.Q' 'Key0Instance/ShRegister<0>_MC.Q'.

Performance Summary
Min. Clock Period 12.000 ns.
Max. Clock Frequency (fSYSTEM) 83.333 MHz.
Limited by Clock Pulse Width for Key0Instance/ShRegister<3>_MC.Q
Clock to Setup (tCYC) 5.000 ns.
Pad to Pad Delay (tPD) 5.700 ns.
Setup to Clock at the Pad (tSU) 2.700 ns.
Clock Pad to Output Pad Delay (tCO) 16.700 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS1000 0.0 0.0 0 0
TS1001 0.0 0.0 0 0
TS1002 0.0 0.0 0 0
TS1003 0.0 0.0 0 0
TS1004 0.0 0.0 0 0
TS1005 0.0 0.0 0 0
TS1006 0.0 0.0 0 0
TS1007 0.0 0.0 0 0
AUTO_TS_F2F 0.0 5.0 320 320
AUTO_TS_P2P 0.0 16.7 15 15
AUTO_TS_P2F 0.0 5.1 8 8
AUTO_TS_F2P 0.0 11.4 138 138


Constraint: TS1000

Description: PERIOD:PERIOD_TimeDiv<9>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1001

Description: PERIOD:PERIOD_FDiv<11>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1002

Description: PERIOD:PERIOD_Key0Instance/ShRegister<3>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1003

Description: PERIOD:PERIOD_Key0Instance/ShRegister<2>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1004

Description: PERIOD:PERIOD_Key0Instance/ShRegister<1>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1005

Description: PERIOD:PERIOD_Key0Instance/ShRegister<0>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1006

Description: PERIOD:PERIOD_Clk:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1007

Description: PERIOD:PERIOD_FDiv<9>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
Cnt1000<0>.Q to Cnt1000<1>.D 0.000 5.000 -5.000
Cnt1000<0>.Q to Cnt1000<3>.D 0.000 5.000 -5.000
Cnt1000<1>.Q to Cnt1000<1>.D 0.000 5.000 -5.000


Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
Clk to Seg_A 0.000 16.700 -16.700
Clk to Seg_B 0.000 16.700 -16.700
Clk to Seg_C 0.000 16.700 -16.700


Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
GoKey to Key0Instance/ShRegister<0>.D 0.000 5.100 -5.100
InpSignal to AutomatState_FFd1.D 0.000 4.500 -4.500
InpSignal to AutomatState_FFd2.D 0.000 4.500 -4.500


Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
MuxDisplInstance/SelCnt<0>.Q to Seg_A 0.000 11.400 -11.400
MuxDisplInstance/SelCnt<0>.Q to Seg_B 0.000 11.400 -11.400
MuxDisplInstance/SelCnt<0>.Q to Seg_C 0.000 11.400 -11.400



Number of constraints not met: 4

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
TimeDiv<9>_MC.Q 200.000 Limited by Cycle Time for TimeDiv<9>_MC.Q
FDiv<11>_MC.Q 212.766 Limited by Cycle Time for FDiv<11>_MC.Q
Key0Instance/ShRegister<3>_MC.Q 83.333 Limited by Clock Pulse Width for Key0Instance/ShRegister<3>_MC.Q
Key0Instance/ShRegister<2>_MC.Q 83.333 Limited by Clock Pulse Width for Key0Instance/ShRegister<2>_MC.Q
Key0Instance/ShRegister<1>_MC.Q 83.333 Limited by Clock Pulse Width for Key0Instance/ShRegister<1>_MC.Q
Key0Instance/ShRegister<0>_MC.Q 83.333 Limited by Clock Pulse Width for Key0Instance/ShRegister<0>_MC.Q
Clk 238.095 Limited by Cycle Time for Clk
FDiv<9>_MC.Q 212.766 Limited by Cycle Time for FDiv<9>_MC.Q

Setup/Hold Times for Clocks

Setup/Hold Times for Clock FDiv<11>.Q
Source Pad Setup to clk (edge) Hold to clk (edge)
GoKey 1.600 0.000

Setup/Hold Times for Clock Clk
Source Pad Setup to clk (edge) Hold to clk (edge)
InpSignal 2.700 0.000
Reset 2.700 0.000


Clock to Pad Timing

Clock Clk to Pad
Destination Pad Clock (edge) to Pad
Seg_A 16.700
Seg_B 16.700
Seg_C 16.700
Seg_D 16.700
Seg_E 16.700
Seg_F 16.700
Seg_G 16.700
DSel0 10.700
DSel1 10.700
DSel2 10.700
DSel3 10.700
Seg_K 10.700
MeasLed 4.500
RunStatusLed 4.500


Clock to Setup Times for Clocks

Clock to Setup for clock TimeDiv<9>.Q
Source Destination Delay
Cnt1000<0>.Q Cnt1000<1>.D 5.000
Cnt1000<0>.Q Cnt1000<3>.D 5.000
Cnt1000<1>.Q Cnt1000<1>.D 5.000
Cnt1000<1>.Q Cnt1000<3>.D 5.000
Cnt1000<2>.Q Cnt1000<1>.D 5.000
Cnt1000<2>.Q Cnt1000<3>.D 5.000
Cnt1000<3>.Q Cnt1000<1>.D 5.000
Cnt1000<3>.Q Cnt1000<3>.D 5.000
Cnt100<0>.Q Cnt1000<1>.D 5.000
Cnt100<0>.Q Cnt1000<3>.D 5.000
Cnt100<0>.Q Cnt100<1>.D 5.000
Cnt100<0>.Q Cnt100<3>.D 5.000
Cnt100<1>.Q Cnt1000<1>.D 5.000
Cnt100<1>.Q Cnt1000<3>.D 5.000
Cnt100<1>.Q Cnt100<1>.D 5.000
Cnt100<1>.Q Cnt100<3>.D 5.000
Cnt100<2>.Q Cnt1000<1>.D 5.000
Cnt100<2>.Q Cnt1000<3>.D 5.000
Cnt100<2>.Q Cnt100<1>.D 5.000
Cnt100<2>.Q Cnt100<3>.D 5.000
Cnt100<3>.Q Cnt1000<1>.D 5.000
Cnt100<3>.Q Cnt1000<3>.D 5.000
Cnt100<3>.Q Cnt100<1>.D 5.000
Cnt100<3>.Q Cnt100<3>.D 5.000
Cnt10<0>.Q Cnt1000<1>.D 5.000
Cnt10<0>.Q Cnt1000<3>.D 5.000
Cnt10<0>.Q Cnt100<1>.D 5.000
Cnt10<0>.Q Cnt100<3>.D 5.000
Cnt10<0>.Q Cnt10<1>.D 5.000
Cnt10<0>.Q Cnt10<3>.D 5.000
Cnt10<1>.Q Cnt1000<1>.D 5.000
Cnt10<1>.Q Cnt1000<3>.D 5.000
Cnt10<1>.Q Cnt100<1>.D 5.000
Cnt10<1>.Q Cnt100<3>.D 5.000
Cnt10<1>.Q Cnt10<1>.D 5.000
Cnt10<1>.Q Cnt10<3>.D 5.000
Cnt10<2>.Q Cnt1000<1>.D 5.000
Cnt10<2>.Q Cnt1000<3>.D 5.000
Cnt10<2>.Q Cnt100<1>.D 5.000
Cnt10<2>.Q Cnt100<3>.D 5.000
Cnt10<2>.Q Cnt10<1>.D 5.000
Cnt10<2>.Q Cnt10<3>.D 5.000
Cnt10<3>.Q Cnt1000<1>.D 5.000
Cnt10<3>.Q Cnt1000<3>.D 5.000
Cnt10<3>.Q Cnt100<1>.D 5.000
Cnt10<3>.Q Cnt100<3>.D 5.000
Cnt10<3>.Q Cnt10<1>.D 5.000
Cnt10<3>.Q Cnt10<3>.D 5.000
Cnt1<0>.Q Cnt1000<1>.D 5.000
Cnt1<0>.Q Cnt1000<3>.D 5.000
Cnt1<0>.Q Cnt100<1>.D 5.000
Cnt1<0>.Q Cnt100<3>.D 5.000
Cnt1<0>.Q Cnt10<1>.D 5.000
Cnt1<0>.Q Cnt10<3>.D 5.000
Cnt1<0>.Q Cnt1<1>.D 5.000
Cnt1<0>.Q Cnt1<3>.D 5.000
Cnt1<1>.Q Cnt1000<1>.D 5.000
Cnt1<1>.Q Cnt1000<3>.D 5.000
Cnt1<1>.Q Cnt100<1>.D 5.000
Cnt1<1>.Q Cnt100<3>.D 5.000
Cnt1<1>.Q Cnt10<1>.D 5.000
Cnt1<1>.Q Cnt10<3>.D 5.000
Cnt1<1>.Q Cnt1<1>.D 5.000
Cnt1<1>.Q Cnt1<3>.D 5.000
Cnt1<2>.Q Cnt1000<1>.D 5.000
Cnt1<2>.Q Cnt1000<3>.D 5.000
Cnt1<2>.Q Cnt100<1>.D 5.000
Cnt1<2>.Q Cnt100<3>.D 5.000
Cnt1<2>.Q Cnt10<1>.D 5.000
Cnt1<2>.Q Cnt10<3>.D 5.000
Cnt1<2>.Q Cnt1<1>.D 5.000
Cnt1<2>.Q Cnt1<3>.D 5.000
Cnt1<3>.Q Cnt1000<1>.D 5.000
Cnt1<3>.Q Cnt1000<3>.D 5.000
Cnt1<3>.Q Cnt100<1>.D 5.000
Cnt1<3>.Q Cnt100<3>.D 5.000
Cnt1<3>.Q Cnt10<1>.D 5.000
Cnt1<3>.Q Cnt10<3>.D 5.000
Cnt1<3>.Q Cnt1<1>.D 5.000
Cnt1<3>.Q Cnt1<3>.D 5.000
Cnt1000<0>.Q Cnt1000<2>.D 4.700
Cnt1000<1>.Q Cnt1000<2>.D 4.700
Cnt100<0>.Q Cnt1000<0>.D 4.700
Cnt100<0>.Q Cnt1000<2>.D 4.700
Cnt100<0>.Q Cnt100<2>.D 4.700
Cnt100<1>.Q Cnt1000<0>.D 4.700
Cnt100<1>.Q Cnt1000<2>.D 4.700
Cnt100<1>.Q Cnt100<2>.D 4.700
Cnt100<2>.Q Cnt1000<0>.D 4.700
Cnt100<2>.Q Cnt1000<2>.D 4.700
Cnt100<3>.Q Cnt1000<0>.D 4.700
Cnt100<3>.Q Cnt1000<2>.D 4.700
Cnt10<0>.Q Cnt1000<0>.D 4.700
Cnt10<0>.Q Cnt1000<2>.D 4.700
Cnt10<0>.Q Cnt100<0>.D 4.700
Cnt10<0>.Q Cnt100<2>.D 4.700
Cnt10<0>.Q Cnt10<2>.D 4.700
Cnt10<1>.Q Cnt1000<0>.D 4.700
Cnt10<1>.Q Cnt1000<2>.D 4.700
Cnt10<1>.Q Cnt100<0>.D 4.700
Cnt10<1>.Q Cnt100<2>.D 4.700
Cnt10<1>.Q Cnt10<2>.D 4.700
Cnt10<2>.Q Cnt1000<0>.D 4.700
Cnt10<2>.Q Cnt1000<2>.D 4.700
Cnt10<2>.Q Cnt100<0>.D 4.700
Cnt10<2>.Q Cnt100<2>.D 4.700
Cnt10<3>.Q Cnt1000<0>.D 4.700
Cnt10<3>.Q Cnt1000<2>.D 4.700
Cnt10<3>.Q Cnt100<0>.D 4.700
Cnt10<3>.Q Cnt100<2>.D 4.700
Cnt1<0>.Q Cnt1000<0>.D 4.700
Cnt1<0>.Q Cnt1000<2>.D 4.700
Cnt1<0>.Q Cnt100<0>.D 4.700
Cnt1<0>.Q Cnt100<2>.D 4.700
Cnt1<0>.Q Cnt10<0>.D 4.700
Cnt1<0>.Q Cnt10<2>.D 4.700
Cnt1<0>.Q Cnt1<2>.D 4.700
Cnt1<1>.Q Cnt1000<0>.D 4.700
Cnt1<1>.Q Cnt1000<2>.D 4.700
Cnt1<1>.Q Cnt100<0>.D 4.700
Cnt1<1>.Q Cnt100<2>.D 4.700
Cnt1<1>.Q Cnt10<0>.D 4.700
Cnt1<1>.Q Cnt10<2>.D 4.700
Cnt1<1>.Q Cnt1<2>.D 4.700
Cnt1<2>.Q Cnt1000<0>.D 4.700
Cnt1<2>.Q Cnt1000<2>.D 4.700
Cnt1<2>.Q Cnt100<0>.D 4.700
Cnt1<2>.Q Cnt100<2>.D 4.700
Cnt1<2>.Q Cnt10<0>.D 4.700
Cnt1<2>.Q Cnt10<2>.D 4.700
Cnt1<3>.Q Cnt1000<0>.D 4.700
Cnt1<3>.Q Cnt1000<2>.D 4.700
Cnt1<3>.Q Cnt100<0>.D 4.700
Cnt1<3>.Q Cnt100<2>.D 4.700
Cnt1<3>.Q Cnt10<0>.D 4.700
Cnt1<3>.Q Cnt10<2>.D 4.700

Clock to Setup for clock FDiv<11>.Q
Source Destination Delay
Key0Instance/ShRegister<0>.Q Key0Instance/ShRegister<1>.D 4.700
Key0Instance/ShRegister<1>.Q Key0Instance/ShRegister<2>.D 4.700
Key0Instance/ShRegister<2>.Q Key0Instance/ShRegister<3>.D 4.700

Clock to Setup for clock Clk
Source Destination Delay
AutomatState_FFd1.Q AutomatState_FFd1.D 4.200
AutomatState_FFd1.Q AutomatState_FFd2.D 4.200
AutomatState_FFd1.Q AutomatState_FFd3.D 4.200
AutomatState_FFd1.Q Clear.D 4.200
AutomatState_FFd1.Q MeasLed.D 4.200
AutomatState_FFd1.Q RunStatusLed.D 4.200
AutomatState_FFd2.Q AutomatState_FFd1.D 4.200
AutomatState_FFd2.Q AutomatState_FFd2.D 4.200
AutomatState_FFd2.Q AutomatState_FFd3.D 4.200
AutomatState_FFd2.Q RunStatusLed.D 4.200
AutomatState_FFd3.Q AutomatState_FFd1.D 4.200
AutomatState_FFd3.Q AutomatState_FFd2.D 4.200
AutomatState_FFd3.Q AutomatState_FFd3.D 4.200
AutomatState_FFd3.Q Clear.D 4.200
AutomatState_FFd3.Q MeasLed.D 4.200
AutomatState_FFd3.Q RunStatusLed.D 4.200
Clear.Q Clear.D 4.200
MeasLed.Q MeasLed.D 4.200
MeasLed.Q TimeDiv<3>.D 4.200
MeasLed.Q TimeDiv<5>.D 4.200
MeasLed.Q TimeDiv<6>.D 4.200
MeasLed.Q TimeDiv<7>.D 4.200
MeasLed.Q TimeDiv<8>.D 4.200
MeasLed.Q TimeDiv<9>.D 4.200
RunStatusLed.Q RunStatusLed.D 4.200
TimeDiv<0>.Q TimeDiv<3>.D 4.200
TimeDiv<0>.Q TimeDiv<5>.D 4.200
TimeDiv<0>.Q TimeDiv<6>.D 4.200
TimeDiv<0>.Q TimeDiv<7>.D 4.200
TimeDiv<0>.Q TimeDiv<8>.D 4.200
TimeDiv<0>.Q TimeDiv<9>.D 4.200
TimeDiv<1>.Q TimeDiv<3>.D 4.200
TimeDiv<1>.Q TimeDiv<5>.D 4.200
TimeDiv<1>.Q TimeDiv<6>.D 4.200
TimeDiv<1>.Q TimeDiv<7>.D 4.200
TimeDiv<1>.Q TimeDiv<8>.D 4.200
TimeDiv<1>.Q TimeDiv<9>.D 4.200
TimeDiv<2>.Q TimeDiv<3>.D 4.200
TimeDiv<2>.Q TimeDiv<5>.D 4.200
TimeDiv<2>.Q TimeDiv<6>.D 4.200
TimeDiv<2>.Q TimeDiv<7>.D 4.200
TimeDiv<2>.Q TimeDiv<8>.D 4.200
TimeDiv<2>.Q TimeDiv<9>.D 4.200
TimeDiv<3>.Q TimeDiv<3>.D 4.200
TimeDiv<3>.Q TimeDiv<5>.D 4.200
TimeDiv<3>.Q TimeDiv<6>.D 4.200
TimeDiv<3>.Q TimeDiv<7>.D 4.200
TimeDiv<3>.Q TimeDiv<8>.D 4.200
TimeDiv<3>.Q TimeDiv<9>.D 4.200
TimeDiv<4>.Q TimeDiv<3>.D 4.200
TimeDiv<4>.Q TimeDiv<5>.D 4.200
TimeDiv<4>.Q TimeDiv<6>.D 4.200
TimeDiv<4>.Q TimeDiv<7>.D 4.200
TimeDiv<4>.Q TimeDiv<8>.D 4.200
TimeDiv<4>.Q TimeDiv<9>.D 4.200
TimeDiv<5>.Q TimeDiv<3>.D 4.200
TimeDiv<5>.Q TimeDiv<5>.D 4.200
TimeDiv<5>.Q TimeDiv<6>.D 4.200
TimeDiv<5>.Q TimeDiv<7>.D 4.200
TimeDiv<5>.Q TimeDiv<8>.D 4.200
TimeDiv<5>.Q TimeDiv<9>.D 4.200
TimeDiv<6>.Q TimeDiv<3>.D 4.200
TimeDiv<6>.Q TimeDiv<5>.D 4.200
TimeDiv<6>.Q TimeDiv<6>.D 4.200
TimeDiv<6>.Q TimeDiv<7>.D 4.200
TimeDiv<6>.Q TimeDiv<8>.D 4.200
TimeDiv<6>.Q TimeDiv<9>.D 4.200
TimeDiv<7>.Q TimeDiv<3>.D 4.200
TimeDiv<7>.Q TimeDiv<5>.D 4.200
TimeDiv<7>.Q TimeDiv<6>.D 4.200
TimeDiv<7>.Q TimeDiv<7>.D 4.200
TimeDiv<7>.Q TimeDiv<8>.D 4.200
TimeDiv<7>.Q TimeDiv<9>.D 4.200
TimeDiv<8>.Q TimeDiv<3>.D 4.200
TimeDiv<8>.Q TimeDiv<5>.D 4.200
TimeDiv<8>.Q TimeDiv<6>.D 4.200
TimeDiv<8>.Q TimeDiv<7>.D 4.200
TimeDiv<8>.Q TimeDiv<8>.D 4.200
TimeDiv<8>.Q TimeDiv<9>.D 4.200
TimeDiv<9>.Q TimeDiv<3>.D 4.200
TimeDiv<9>.Q TimeDiv<5>.D 4.200
TimeDiv<9>.Q TimeDiv<6>.D 4.200
TimeDiv<9>.Q TimeDiv<7>.D 4.200
TimeDiv<9>.Q TimeDiv<8>.D 4.200
TimeDiv<9>.Q TimeDiv<9>.D 4.200
FDiv<0>.Q FDiv<10>.D 3.900
FDiv<0>.Q FDiv<11>.D 3.900
FDiv<0>.Q FDiv<1>.D 3.900
FDiv<0>.Q FDiv<2>.D 3.900
FDiv<0>.Q FDiv<3>.D 3.900
FDiv<0>.Q FDiv<4>.D 3.900
FDiv<0>.Q FDiv<5>.D 3.900
FDiv<0>.Q FDiv<6>.D 3.900
FDiv<0>.Q FDiv<7>.D 3.900
FDiv<0>.Q FDiv<8>.D 3.900
FDiv<0>.Q FDiv<9>.D 3.900
FDiv<10>.Q FDiv<11>.D 3.900
FDiv<1>.Q FDiv<10>.D 3.900
FDiv<1>.Q FDiv<11>.D 3.900
FDiv<1>.Q FDiv<2>.D 3.900
FDiv<1>.Q FDiv<3>.D 3.900
FDiv<1>.Q FDiv<4>.D 3.900
FDiv<1>.Q FDiv<5>.D 3.900
FDiv<1>.Q FDiv<6>.D 3.900
FDiv<1>.Q FDiv<7>.D 3.900
FDiv<1>.Q FDiv<8>.D 3.900
FDiv<1>.Q FDiv<9>.D 3.900
FDiv<2>.Q FDiv<10>.D 3.900
FDiv<2>.Q FDiv<11>.D 3.900
FDiv<2>.Q FDiv<3>.D 3.900
FDiv<2>.Q FDiv<4>.D 3.900
FDiv<2>.Q FDiv<5>.D 3.900
FDiv<2>.Q FDiv<6>.D 3.900
FDiv<2>.Q FDiv<7>.D 3.900
FDiv<2>.Q FDiv<8>.D 3.900
FDiv<2>.Q FDiv<9>.D 3.900
FDiv<3>.Q FDiv<10>.D 3.900
FDiv<3>.Q FDiv<11>.D 3.900
FDiv<3>.Q FDiv<4>.D 3.900
FDiv<3>.Q FDiv<5>.D 3.900
FDiv<3>.Q FDiv<6>.D 3.900
FDiv<3>.Q FDiv<7>.D 3.900
FDiv<3>.Q FDiv<8>.D 3.900
FDiv<3>.Q FDiv<9>.D 3.900
FDiv<4>.Q FDiv<10>.D 3.900
FDiv<4>.Q FDiv<11>.D 3.900
FDiv<4>.Q FDiv<5>.D 3.900
FDiv<4>.Q FDiv<6>.D 3.900
FDiv<4>.Q FDiv<7>.D 3.900
FDiv<4>.Q FDiv<8>.D 3.900
FDiv<4>.Q FDiv<9>.D 3.900
FDiv<5>.Q FDiv<10>.D 3.900
FDiv<5>.Q FDiv<11>.D 3.900
FDiv<5>.Q FDiv<6>.D 3.900
FDiv<5>.Q FDiv<7>.D 3.900
FDiv<5>.Q FDiv<8>.D 3.900
FDiv<5>.Q FDiv<9>.D 3.900
FDiv<6>.Q FDiv<10>.D 3.900
FDiv<6>.Q FDiv<11>.D 3.900
FDiv<6>.Q FDiv<7>.D 3.900
FDiv<6>.Q FDiv<8>.D 3.900
FDiv<6>.Q FDiv<9>.D 3.900
FDiv<7>.Q FDiv<10>.D 3.900
FDiv<7>.Q FDiv<11>.D 3.900
FDiv<7>.Q FDiv<8>.D 3.900
FDiv<7>.Q FDiv<9>.D 3.900
FDiv<8>.Q FDiv<10>.D 3.900
FDiv<8>.Q FDiv<11>.D 3.900
FDiv<8>.Q FDiv<9>.D 3.900
FDiv<9>.Q FDiv<10>.D 3.900
FDiv<9>.Q FDiv<11>.D 3.900
MeasLed.Q TimeDiv<0>.D 3.900
MeasLed.Q TimeDiv<1>.D 3.900
MeasLed.Q TimeDiv<2>.D 3.900
MeasLed.Q TimeDiv<4>.D 3.900
TimeDiv<0>.Q TimeDiv<1>.D 3.900
TimeDiv<0>.Q TimeDiv<2>.D 3.900
TimeDiv<0>.Q TimeDiv<4>.D 3.900
TimeDiv<1>.Q TimeDiv<2>.D 3.900
TimeDiv<1>.Q TimeDiv<4>.D 3.900
TimeDiv<2>.Q TimeDiv<4>.D 3.900
TimeDiv<3>.Q TimeDiv<4>.D 3.900

Clock to Setup for clock FDiv<9>.Q
Source Destination Delay
MuxDisplInstance/SelCnt<0>.Q MuxDisplInstance/SelCnt<1>.D 4.700


Pad to Pad List

Source Pad Destination Pad Delay
InpSignal SignalEcho 5.700



Number of paths analyzed: 481
Number of Timing errors: 481
Analysis Completed: Mon Mar 22 14:00:39 2010