Equations

********** Mapped Logic **********
FTCPE_Cnt10000: FTCPE port map (Cnt1000(0),Cnt1000_T(0),FDiv(11),NOT Reset,'0','1');
     Cnt1000_T(0) <= (NOT Cnt100(1) AND Enable AND Cnt100(0) AND Cnt10(0) AND
      Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND
      NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(2) AND Cnt100(3));
FTCPE_Cnt10001: FTCPE port map (Cnt1000(1),Cnt1000_T(1),FDiv(11),NOT Reset,'0','1');
     Cnt1000_T(1) <= ((NOT Cnt100(1) AND Enable AND Cnt100(0) AND Cnt10(0) AND
      Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND
      NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(2) AND Cnt100(3) AND Cnt1000(1) AND
      Cnt1000(0))
      OR (NOT Cnt100(1) AND Enable AND Cnt100(0) AND Cnt10(0) AND
      Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND
      NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(2) AND Cnt100(3) AND Cnt1000(0) AND
      Cnt1000(2))
      OR (NOT Cnt100(1) AND Enable AND Cnt100(0) AND Cnt10(0) AND
      Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND
      NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(2) AND Cnt100(3) AND Cnt1000(0) AND
      NOT Cnt1000(3)));
FTCPE_Cnt10002: FTCPE port map (Cnt1000(2),Cnt1000_T(2),FDiv(11),NOT Reset,'0','1');
     Cnt1000_T(2) <= (NOT Cnt100(1) AND Enable AND Cnt100(0) AND Cnt10(0) AND
      Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND
      NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(2) AND Cnt100(3) AND Cnt1000(1) AND
      Cnt1000(0));
FTCPE_Cnt10003: FTCPE port map (Cnt1000(3),Cnt1000_T(3),FDiv(11),NOT Reset,'0','1');
     Cnt1000_T(3) <= ((NOT Cnt100(1) AND Enable AND Cnt100(0) AND Cnt10(0) AND
      Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND
      NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(2) AND Cnt100(3) AND Cnt1000(1) AND
      Cnt1000(0) AND Cnt1000(2))
      OR (NOT Cnt100(1) AND Enable AND Cnt100(0) AND Cnt10(0) AND
      Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND
      NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(2) AND Cnt100(3) AND NOT Cnt1000(1) AND
      Cnt1000(0) AND NOT Cnt1000(2) AND Cnt1000(3)));
FTCPE_Cnt1000: FTCPE port map (Cnt100(0),Cnt100_T(0),FDiv(11),NOT Reset,'0','1');
     Cnt100_T(0) <= (Enable AND Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND
      NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3));
FTCPE_Cnt1001: FTCPE port map (Cnt100(1),Cnt100_T(1),FDiv(11),NOT Reset,'0','1');
     Cnt100_T(1) <= ((Cnt100(1) AND Enable AND Cnt100(0) AND Cnt10(0) AND
      Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND
      NOT Cnt10(2) AND Cnt10(3))
      OR (Enable AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND
      NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND
      Cnt10(3) AND Cnt100(2))
      OR (Enable AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND
      NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND
      Cnt10(3) AND NOT Cnt100(3)));
FTCPE_Cnt1002: FTCPE port map (Cnt100(2),Cnt100_T(2),FDiv(11),NOT Reset,'0','1');
     Cnt100_T(2) <= (Cnt100(1) AND Enable AND Cnt100(0) AND Cnt10(0) AND
      Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND
      NOT Cnt10(2) AND Cnt10(3));
FTCPE_Cnt1003: FTCPE port map (Cnt100(3),Cnt100_T(3),FDiv(11),NOT Reset,'0','1');
     Cnt100_T(3) <= ((Cnt100(1) AND Enable AND Cnt100(0) AND Cnt10(0) AND
      Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND
      NOT Cnt10(2) AND Cnt10(3) AND Cnt100(2))
      OR (NOT Cnt100(1) AND Enable AND Cnt100(0) AND Cnt10(0) AND
      Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND
      NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(2) AND Cnt100(3)));
FTCPE_Cnt100: FTCPE port map (Cnt10(0),Cnt10_T(0),FDiv(11),NOT Reset,'0','1');
     Cnt10_T(0) <= (Enable AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3));
FTCPE_Cnt101: FTCPE port map (Cnt10(1),Cnt10_T(1),FDiv(11),NOT Reset,'0','1');
     Cnt10_T(1) <= ((Enable AND Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND
      NOT Cnt1(2) AND Cnt1(3) AND Cnt10(1))
      OR (Enable AND Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND
      NOT Cnt1(2) AND Cnt1(3) AND Cnt10(2))
      OR (Enable AND Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND
      NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(3)));
FTCPE_Cnt102: FTCPE port map (Cnt10(2),Cnt10_T(2),FDiv(11),NOT Reset,'0','1');
     Cnt10_T(2) <= (Enable AND Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND
      NOT Cnt1(2) AND Cnt1(3) AND Cnt10(1));
FTCPE_Cnt103: FTCPE port map (Cnt10(3),Cnt10_T(3),FDiv(11),NOT Reset,'0','1');
     Cnt10_T(3) <= ((Enable AND Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND
      NOT Cnt1(2) AND Cnt1(3) AND Cnt10(1) AND Cnt10(2))
      OR (Enable AND Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND
      NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3)));
FDCPE_Cnt10: FDCPE port map (Cnt1(0),Enable,FDiv(11),NOT Reset,'0','1');
FTCPE_Cnt11: FTCPE port map (Cnt1(1),Cnt1_T(1),FDiv(11),NOT Reset,'0','1');
     Cnt1_T(1) <= (Enable AND Cnt1(0))
      XOR (Enable AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3));
FTCPE_Cnt12: FTCPE port map (Cnt1(2),Cnt1_T(2),FDiv(11),NOT Reset,'0','1');
     Cnt1_T(2) <= (Enable AND Cnt1(0) AND Cnt1(1));
FTCPE_Cnt13: FTCPE port map (Cnt1(3),Cnt1_T(3),FDiv(11),NOT Reset,'0','1');
     Cnt1_T(3) <= ((Enable AND Cnt1(0) AND Cnt1(1) AND Cnt1(2))
      OR (Enable AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3)));
DSel0 <= NOT ((NOT MuxDisplInstance/SelCnt(0) AND
      NOT MuxDisplInstance/SelCnt(1)));
DSel1 <= NOT ((MuxDisplInstance/SelCnt(0) AND
      NOT MuxDisplInstance/SelCnt(1)));
DSel2 <= NOT ((NOT MuxDisplInstance/SelCnt(0) AND
      MuxDisplInstance/SelCnt(1)));
DSel3 <= NOT ((MuxDisplInstance/SelCnt(0) AND
      MuxDisplInstance/SelCnt(1)));
FTCPE_FClk: FTCPE port map (FClk,FClk_T,NOT Clk,NOT Reset,'0','1');
     FClk_T <= (FDivInstance/FDivCnt(0) AND FDivInstance/FDivCnt(1) AND
      FDivInstance/FDivCnt(2) AND FDivInstance/FDivCnt(3) AND FDivInstance/FDivCnt(4) AND
      FDivInstance/FDivCnt(5) AND FDivInstance/FDivCnt(6));
FTCPE_FDiv0: FTCPE port map (FDiv(0),'0',FClk,NOT Reset,'0','1');
FTCPE_FDiv1: FTCPE port map (FDiv(1),FDiv(0),FClk,NOT Reset,'0','1');
FTCPE_FDiv2: FTCPE port map (FDiv(2),FDiv_T(2),FClk,NOT Reset,'0','1');
     FDiv_T(2) <= (FDiv(0) AND FDiv(1));
FTCPE_FDiv3: FTCPE port map (FDiv(3),FDiv_T(3),FClk,NOT Reset,'0','1');
     FDiv_T(3) <= (FDiv(0) AND FDiv(1) AND FDiv(2));
FTCPE_FDiv4: FTCPE port map (FDiv(4),FDiv_T(4),FClk,NOT Reset,'0','1');
     FDiv_T(4) <= (FDiv(3) AND FDiv(0) AND FDiv(1) AND FDiv(2));
FTCPE_FDiv5: FTCPE port map (FDiv(5),FDiv_T(5),FClk,NOT Reset,'0','1');
     FDiv_T(5) <= (FDiv(3) AND FDiv(0) AND FDiv(1) AND FDiv(2) AND
      FDiv(4));
FTCPE_FDiv6: FTCPE port map (FDiv(6),FDiv_T(6),FClk,NOT Reset,'0','1');
     FDiv_T(6) <= (FDiv(3) AND FDiv(0) AND FDiv(1) AND FDiv(2) AND
      FDiv(4) AND FDiv(5));
FTCPE_FDiv7: FTCPE port map (FDiv(7),FDiv_T(7),FClk,NOT Reset,'0','1');
     FDiv_T(7) <= (FDiv(3) AND FDiv(0) AND FDiv(1) AND FDiv(2) AND
      FDiv(4) AND FDiv(5) AND FDiv(6));
FTCPE_FDiv8: FTCPE port map (FDiv(8),FDiv_T(8),FClk,NOT Reset,'0','1');
     FDiv_T(8) <= (FDiv(3) AND FDiv(0) AND FDiv(1) AND FDiv(2) AND
      FDiv(4) AND FDiv(5) AND FDiv(6) AND FDiv(7));
FTCPE_FDiv9: FTCPE port map (FDiv(9),FDiv_T(9),FClk,NOT Reset,'0','1');
     FDiv_T(9) <= (FDiv(3) AND FDiv(0) AND FDiv(1) AND FDiv(2) AND
      FDiv(4) AND FDiv(5) AND FDiv(6) AND FDiv(7) AND FDiv(8));
FTCPE_FDiv10: FTCPE port map (FDiv(10),FDiv_T(10),FClk,NOT Reset,'0','1');
     FDiv_T(10) <= (FDiv(3) AND FDiv(0) AND FDiv(1) AND FDiv(2) AND
      FDiv(4) AND FDiv(5) AND FDiv(6) AND FDiv(7) AND FDiv(8) AND
      FDiv(9));
FTCPE_FDiv11: FTCPE port map (FDiv(11),FDiv_T(11),FClk,NOT Reset,'0','1');
     FDiv_T(11) <= (FDiv(3) AND FDiv(0) AND FDiv(1) AND FDiv(2) AND
      FDiv(10) AND FDiv(4) AND FDiv(5) AND FDiv(6) AND FDiv(7) AND
      FDiv(8) AND FDiv(9));
FTCPE_FDivInstance/FDivCnt0: FTCPE port map (FDivInstance/FDivCnt(0),'0',NOT Clk,NOT Reset,'0','1');
FTCPE_FDivInstance/FDivCnt1: FTCPE port map (FDivInstance/FDivCnt(1),FDivInstance/FDivCnt(0),NOT Clk,NOT Reset,'0','1');
FTCPE_FDivInstance/FDivCnt2: FTCPE port map (FDivInstance/FDivCnt(2),FDivInstance/FDivCnt_T(2),NOT Clk,NOT Reset,'0','1');
     FDivInstance/FDivCnt_T(2) <= (FDivInstance/FDivCnt(0) AND FDivInstance/FDivCnt(1));
FTCPE_FDivInstance/FDivCnt3: FTCPE port map (FDivInstance/FDivCnt(3),FDivInstance/FDivCnt_T(3),NOT Clk,NOT Reset,'0','1');
     FDivInstance/FDivCnt_T(3) <= (FDivInstance/FDivCnt(0) AND FDivInstance/FDivCnt(1) AND
      FDivInstance/FDivCnt(2));
FTCPE_FDivInstance/FDivCnt4: FTCPE port map (FDivInstance/FDivCnt(4),FDivInstance/FDivCnt_T(4),NOT Clk,NOT Reset,'0','1');
     FDivInstance/FDivCnt_T(4) <= (FDivInstance/FDivCnt(0) AND FDivInstance/FDivCnt(1) AND
      FDivInstance/FDivCnt(2) AND FDivInstance/FDivCnt(3));
FTCPE_FDivInstance/FDivCnt5: FTCPE port map (FDivInstance/FDivCnt(5),FDivInstance/FDivCnt_T(5),NOT Clk,NOT Reset,'0','1');
     FDivInstance/FDivCnt_T(5) <= (FDivInstance/FDivCnt(0) AND FDivInstance/FDivCnt(1) AND
      FDivInstance/FDivCnt(2) AND FDivInstance/FDivCnt(3) AND FDivInstance/FDivCnt(4));
FTCPE_FDivInstance/FDivCnt6: FTCPE port map (FDivInstance/FDivCnt(6),FDivInstance/FDivCnt_T(6),NOT Clk,NOT Reset,'0','1');
     FDivInstance/FDivCnt_T(6) <= (FDivInstance/FDivCnt(0) AND FDivInstance/FDivCnt(1) AND
      FDivInstance/FDivCnt(2) AND FDivInstance/FDivCnt(3) AND FDivInstance/FDivCnt(4) AND
      FDivInstance/FDivCnt(5));
FTCPE_MuxDisplInstance/SelCnt0: FTCPE port map (MuxDisplInstance/SelCnt(0),'0',FDiv(3),NOT Reset,'0','1');
FTCPE_MuxDisplInstance/SelCnt1: FTCPE port map (MuxDisplInstance/SelCnt(1),MuxDisplInstance/SelCnt(0),FDiv(3),NOT Reset,'0','1');
MuxDisplInstance/Tetr(0) <= ((Cnt100(0) AND NOT DSel2)
      OR (Cnt10(0) AND NOT DSel1)
      OR (Cnt1(0) AND NOT DSel0)
      OR (Cnt1000(0) AND NOT DSel3));
MuxDisplInstance/Tetr(1) <= ((Cnt100(1) AND NOT DSel2)
      OR (Cnt1(1) AND NOT DSel0)
      OR (Cnt10(1) AND NOT DSel1)
      OR (Cnt1000(1) AND NOT DSel3));
MuxDisplInstance/Tetr(2) <= ((Cnt1(2) AND NOT DSel0)
      OR (Cnt10(2) AND NOT DSel1)
      OR (Cnt100(2) AND NOT DSel2)
      OR (Cnt1000(2) AND NOT DSel3));
MuxDisplInstance/Tetr(3) <= ((Cnt1(3) AND NOT DSel0)
      OR (Cnt10(3) AND NOT DSel1)
      OR (Cnt100(3) AND NOT DSel2)
      OR (Cnt1000(3) AND NOT DSel3));
Seg_A <= (NOT MuxDisplInstance/Tetr(1) AND
      MuxDisplInstance/Tetr(0))
      XOR ((NOT MuxDisplInstance/Tetr(1) AND
      NOT MuxDisplInstance/Tetr(3) AND MuxDisplInstance/Tetr(2))
      OR (MuxDisplInstance/Tetr(0) AND
      MuxDisplInstance/Tetr(3) AND NOT MuxDisplInstance/Tetr(2)));
Seg_B <= (NOT MuxDisplInstance/Tetr(0) AND
      MuxDisplInstance/Tetr(2))
      XOR ((MuxDisplInstance/Tetr(1) AND
      MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(3))
      OR (NOT MuxDisplInstance/Tetr(1) AND
      NOT MuxDisplInstance/Tetr(3) AND MuxDisplInstance/Tetr(2)));
Seg_C <= ((MuxDisplInstance/Tetr(1) AND
      MuxDisplInstance/Tetr(3) AND MuxDisplInstance/Tetr(2))
      OR (NOT MuxDisplInstance/Tetr(0) AND
      MuxDisplInstance/Tetr(3) AND MuxDisplInstance/Tetr(2))
      OR (MuxDisplInstance/Tetr(1) AND
      NOT MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(3) AND
      NOT MuxDisplInstance/Tetr(2)));
Seg_D <= ((MuxDisplInstance/Tetr(1) AND
      MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(2))
      OR (MuxDisplInstance/Tetr(1) AND
      NOT MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(3) AND
      NOT MuxDisplInstance/Tetr(2))
      OR (NOT MuxDisplInstance/Tetr(1) AND
      MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(3) AND
      NOT MuxDisplInstance/Tetr(2))
      OR (NOT MuxDisplInstance/Tetr(1) AND
      NOT MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(3) AND
      MuxDisplInstance/Tetr(2)));
Seg_E <= ((MuxDisplInstance/Tetr(0) AND
      NOT MuxDisplInstance/Tetr(3))
      OR (NOT MuxDisplInstance/Tetr(1) AND
      MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(2))
      OR (NOT MuxDisplInstance/Tetr(1) AND
      NOT MuxDisplInstance/Tetr(3) AND MuxDisplInstance/Tetr(2)));
Seg_F <= (MuxDisplInstance/Tetr(0) AND
      NOT MuxDisplInstance/Tetr(3))
      XOR ((NOT MuxDisplInstance/Tetr(1) AND
      MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(2))
      OR (MuxDisplInstance/Tetr(1) AND
      NOT MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(3) AND
      NOT MuxDisplInstance/Tetr(2)));
Seg_G <= ((NOT MuxDisplInstance/Tetr(1) AND
      NOT MuxDisplInstance/Tetr(3) AND NOT MuxDisplInstance/Tetr(2))
      OR (MuxDisplInstance/Tetr(1) AND
      MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(3) AND
      MuxDisplInstance/Tetr(2))
      OR (NOT MuxDisplInstance/Tetr(1) AND
      NOT MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(3) AND
      MuxDisplInstance/Tetr(2)));
Seg_K <= NOT ('0');
Register Legend:
      FDCPE (Q,D,C,CLR,PRE,CE);
      FDDCPE (Q,D,C,CLR,PRE,CE);
      FTCPE (Q,D,C,CLR,PRE,CE);
      FTDCPE (Q,D,C,CLR,PRE,CE);
      LDCP (Q,D,G,CLR,PRE);