cpldfit:  version J.36                              Xilinx Inc.
                                  Fitter Report
Design Name: ARepKey                             Date:  4-14-2009,  0:26AM
Device Used: XC2C256-6-TQ144
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
61 /256 ( 24%) 121 /896  ( 13%) 91  /640  ( 14%) 44 /256 ( 17%) 15 /118 ( 13%)

** Function Block Resources **

Function Mcells   FB Inps  Pterms   IO       CTC      CTR      CTS      CTE     
Block    Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot
FB1      16/16*    23/40    41/56     0/ 6    1/1*     1/1*     0/1      0/1
FB2      16/16*    21/40    25/56     0/ 8    1/1*     0/1      0/1      0/1
FB3      16/16*    31/40    30/56     0/ 6    1/1*     1/1*     0/1      0/1
FB4       1/16      6/40     3/56     0/ 8    1/1*     1/1*     0/1      0/1
FB5       0/16      0/40     0/56     0/ 5    0/1      0/1      0/1      0/1
FB6       0/16      0/40     0/56     0/ 8    0/1      0/1      0/1      0/1
FB7       0/16      0/40     0/56     0/ 8    0/1      0/1      0/1      0/1
FB8       0/16      0/40     0/56     0/ 8    0/1      0/1      0/1      0/1
FB9       0/16      0/40     0/56     0/ 8    0/1      0/1      0/1      0/1
FB10      0/16      0/40     0/56     0/ 9    0/1      0/1      0/1      0/1
FB11      4/16      2/40     4/56     4/ 8    0/1      0/1      0/1      0/1
FB12      0/16      0/40     0/56     0/ 6    0/1      0/1      0/1      0/1
FB13      0/16      0/40     0/56     0/ 8    0/1      0/1      0/1      0/1
FB14      1/16      4/40     3/56     1/ 8    0/1      0/1      0/1      0/1
FB15      0/16      0/40     0/56     0/ 7    0/1      0/1      0/1      0/1
FB16      7/16      4/40    15/56     7/ 7*   0/1      0/1      0/1      0/1
         -----    -------  -------   -----    ---      ---      ---      ---
Total    61/256    91/640  121/896   12/118   4/16     3/16     0/16     0/16

CTC - Control Term Clock
CTR - Control Term Reset
CTS - Control Term Set
CTE - Control Term Output Enable

* - Resource is exhausted

** Global Control Resources **

GCK         GSR         GTS         
Used/Tot    Used/Tot    Used/Tot    
1/3         1/1         0/4

Signal 'Clk' mapped onto global clock net GCK2.
Signal 'Reset' mapped onto global set/reset net GSR.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :    1           1    |  I/O              :    13    108
Output        :   12          12    |  GCK/IO           :     1      3
Bidirectional :    0           0    |  GTS/IO           :     0      4
GCK           :    1           1    |  GSR/IO           :     1      1
GTS           :    0           0    |  CDR/IO           :     0      1
GSR           :    1           1    |  DGE/IO           :     0      1
                 ----        ----
        Total     15          15

End of Mapped Resource Summary
*************************  Summary of Mapped Logic  ************************

** 12 Outputs **

Signal                      Total Total Loc     Pin   Pin       Pin     I/O      I/O       Slew Reg     Reg Init
Name                        Pts   Inps          No.   Type      Use     STD      Style     Rate Use     State
DSel0                       1     2     FB11_13 126   I/O       O       LVCMOS18           FAST         
DSel1                       1     2     FB11_14 128   I/O       O       LVCMOS18           FAST         
DSel2                       1     2     FB11_15 129   I/O       O       LVCMOS18           FAST         
DSel3                       1     2     FB11_16 130   I/O       O       LVCMOS18           FAST         
Seg_G                       3     4     FB14_16 61    I/O       O       LVCMOS18           FAST         
Seg_C                       3     4     FB16_5  60    I/O       O       LVCMOS18           FAST         
Seg_K                       0     0     FB16_6  59    I/O       O       LVCMOS18           FAST         
Seg_D                       4     4     FB16_11 58    I/O       O       LVCMOS18           FAST         
Seg_E                       3     4     FB16_12 57    I/O       O       LVCMOS18           FAST         
Seg_A                       3     4     FB16_13 56    I/O       O       LVCMOS18           FAST         
Seg_F                       3     4     FB16_15 54    I/O       O       LVCMOS18           FAST         
Seg_B                       3     4     FB16_16 53    I/O       O       LVCMOS18           FAST         

** 49 Buried Nodes **

Signal                      Total Total Loc     Reg     Reg Init
Name                        Pts   Inps          Use     State
AutomatState_FFd4           9     10    FB1_1   DFF     RESET
AutomatState_FFd2           3     9     FB1_2   DFF     RESET
DelayCnt<4>                 3     7     FB1_3   TFF     RESET
CntClk                      3     5     FB1_4   DFF     RESET
FClk                        1     7     FB1_5   TFF     RESET
DelayCntEnable              3     6     FB1_6   DFF     RESET
FDivInstance/FDivCnt<6>     1     6     FB1_7   TFF     RESET
FDivInstance/FDivCnt<5>     1     5     FB1_8   TFF     RESET
FDivInstance/FDivCnt<4>     1     4     FB1_9   TFF     RESET
FDivInstance/FDivCnt<3>     1     3     FB1_10  TFF     RESET
FDivInstance/FDivCnt<2>     1     2     FB1_11  TFF     RESET
DelayCntClear               3     6     FB1_12  DFF     RESET
AutomatState_FFd1           6     10    FB1_13  DFF     RESET
AutomatState_FFd3           5     10    FB1_14  TFF     RESET
FDivInstance/FDivCnt<1>     1     1     FB1_15  TFF     RESET
FDivInstance/FDivCnt<0>     0     0     FB1_16  TFF     RESET
MuxDisplInstance/Tetr<0>    4     8     FB2_1           
Cnt100<0>                   2     9     FB2_2   TFF     RESET
Cnt1<2>                     2     3     FB2_3   TFF     RESET
Cnt1<1>                     3     5     FB2_4   TFF     RESET
Cnt1<3>                     3     5     FB2_5   TFF     RESET
Cnt100<2>                   2     11    FB2_6   TFF     RESET
Cnt100<1>                   4     13    FB2_7   TFF     RESET
Cnt100<3>                   3     13    FB2_8   TFF     RESET
Cnt1000<0>                  2     13    FB2_9   TFF     RESET
Cnt1000<2>                  2     15    FB2_10  TFF     RESET
Cnt1000<3>                  3     17    FB2_11  TFF     RESET
Cnt10<0>                    2     5     FB2_12  TFF     RESET
Cnt10<2>                    2     7     FB2_13  TFF     RESET
Cnt10<1>                    4     9     FB2_14  TFF     RESET
Cnt10<3>                    3     9     FB2_15  TFF     RESET
Cnt1000<1>                  4     17    FB2_16  TFF     RESET
DelayCnt<2>                 3     5     FB3_1   TFF     RESET
DelayCnt<1>                 3     4     FB3_2   TFF     RESET
DelayCnt<0>                 3     3     FB3_3   TFF     RESET
FDiv<5>                     2     6     FB3_4   TFF     RESET
N_PZ_459                    1     2     FB3_5           
FDiv<4>                     2     5     FB3_6   TFF     RESET
FDiv<3>                     2     4     FB3_7   TFF     RESET
FDiv<2>                     2     3     FB3_8   TFF     RESET

Signal                      Total Total Loc     Reg     Reg Init
Name                        Pts   Inps          Use     State
FDiv<1>                     2     2     FB3_9   TFF     RESET
FDiv<0>                     1     1     FB3_10  TFF     RESET
Cnt1<0>                     1     1     FB3_11  TFF     RESET
MuxDisplInstance/Tetr<3>    4     8     FB3_12          
MuxDisplInstance/Tetr<2>    4     8     FB3_13          
MuxDisplInstance/SelCnt<1>  2     2     FB3_14  TFF     RESET
MuxDisplInstance/Tetr<1>    4     8     FB3_15          
MuxDisplInstance/SelCnt<0>  1     1     FB3_16  TFF     RESET
DelayCnt<3>                 3     6     FB4_16  TFF     RESET

** 3 Inputs **

Signal                      Loc     Pin   Pin       Pin     I/O      I/O
Name                                No.   Type      Use     STD      Style
Reset                       FB1_3   143   GSR/I/O   GSR/I   LVCMOS18 KPR
Clk                         FB6_4   38    GCK/I/O   GCK     LVCMOS18 KPR
KeyIn                       FB12_15 94    I/O       I       LVCMOS18 KPR

Legend:
Pin No.   - ~     - User Assigned
I/O Style - OD    - OpenDrain
          - PU    - Pullup
          - KPR   - Keeper
          - S     - SchmittTrigger
          - DG    - DataGate
Reg Use   - LATCH - Transparent latch
          - DFF   - D-flip-flop
          - DEFF  - D-flip-flop with clock enable
          - TFF   - T-flip-flop
          - TDFF  - Dual-edge-triggered T-flip-flop
          - DDFF  - Dual-edge-triggered flip-flop
          - DDEFF - Dual-edge-triggered flip-flop with clock enable
          /S (after any above flop/latch type) indicates initial state is Set
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
              VRF - Vref
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               23/17
Number of function block control terms used/remaining:        2/2
Number of PLA product terms used/remaining:                   41/15
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
AutomatState_FFd4             9     FB1_1        (b)     (b)               
AutomatState_FFd2             3     FB1_2        (b)     (b)               
DelayCnt<4>                   3     FB1_3   143  GSR/I/O GSR/I  +   +      
CntClk                        3     FB1_4   142  I/O     (b)               
FClk                          1     FB1_5        (b)     (b)               
DelayCntEnable                3     FB1_6   140  I/O     (b)               
FDivInstance/FDivCnt<6>       1     FB1_7        (b)     (b)               
FDivInstance/FDivCnt<5>       1     FB1_8        (b)     (b)               
FDivInstance/FDivCnt<4>       1     FB1_9        (b)     (b)               
FDivInstance/FDivCnt<3>       1     FB1_10       (b)     (b)               
FDivInstance/FDivCnt<2>       1     FB1_11       (b)     (b)               
DelayCntClear                 3     FB1_12  139  I/O     (b)               
AutomatState_FFd1             6     FB1_13  138  I/O     (b)               
AutomatState_FFd3             5     FB1_14  137  I/O     (b)               
FDivInstance/FDivCnt<1>       1     FB1_15       (b)     (b)               
FDivInstance/FDivCnt<0>       0     FB1_16       (b)     (b)               

Signals Used by Logic in Function Block
  1: AutomatState_FFd1   9: DelayCnt<3>              17: FDivInstance/FDivCnt<3> 
  2: AutomatState_FFd2  10: DelayCnt<4>              18: FDivInstance/FDivCnt<4> 
  3: AutomatState_FFd3  11: DelayCntClear            19: FDivInstance/FDivCnt<5> 
  4: AutomatState_FFd4  12: DelayCntEnable           20: FDivInstance/FDivCnt<6> 
  5: CntClk             13: FDiv<5>                  21: KeyIn 
  6: DelayCnt<0>        14: FDivInstance/FDivCnt<0>  22: N_PZ_459 
  7: DelayCnt<1>        15: FDivInstance/FDivCnt<1>  23: Reset 
  8: DelayCnt<2>        16: FDivInstance/FDivCnt<2> 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
AutomatState_FFd4 
                  XXXX.XXXXX..........X................... 10      
AutomatState_FFd2 
                  XXXX.XXXXX.............................. 9       
DelayCnt<4>       .....XXXX..XX........X.................. 7       
CntClk            .XXXX.................X................. 5       
FClk              .............XXXXXXX.................... 7       
DelayCntEnable    XXXX.......X..........X................. 6       
FDivInstance/FDivCnt<6> 
                  .............XXXXXX..................... 6       
FDivInstance/FDivCnt<5> 
                  .............XXXXX...................... 5       
FDivInstance/FDivCnt<4> 
                  .............XXXX....................... 4       
FDivInstance/FDivCnt<3> 
                  .............XXX........................ 3       
FDivInstance/FDivCnt<2> 
                  .............XX......................... 2       
DelayCntClear     XXXX......X...........X................. 6       
AutomatState_FFd1 
                  XXXX.XXXXX..........X................... 10      
AutomatState_FFd3 
                  XXXX.XXXXX..........X................... 10      
FDivInstance/FDivCnt<1> 
                  .............X.......................... 1       
FDivInstance/FDivCnt<0> 
                  ........................................ 0       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB2  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               21/19
Number of function block control terms used/remaining:        1/3
Number of PLA product terms used/remaining:                   25/31
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
MuxDisplInstance/Tetr<0>      4     FB2_1   2    GTS/I/O (b)               
Cnt100<0>                     2     FB2_2        (b)     (b)    +          
Cnt1<2>                       2     FB2_3   3    GTS/I/O (b)    +          
Cnt1<1>                       3     FB2_4   4    I/O     (b)    +          
Cnt1<3>                       3     FB2_5   5    GTS/I/O (b)    +          
Cnt100<2>                     2     FB2_6        (b)     (b)    +          
Cnt100<1>                     4     FB2_7        (b)     (b)    +          
Cnt100<3>                     3     FB2_8        (b)     (b)    +          
Cnt1000<0>                    2     FB2_9        (b)     (b)    +          
Cnt1000<2>                    2     FB2_10       (b)     (b)    +          
Cnt1000<3>                    3     FB2_11       (b)     (b)    +          
Cnt10<0>                      2     FB2_12  6    GTS/I/O (b)    +          
Cnt10<2>                      2     FB2_13  7    I/O     (b)    +          
Cnt10<1>                      4     FB2_14  9    I/O     (b)    +          
Cnt10<3>                      3     FB2_15  10   I/O     (b)    +          
Cnt1000<1>                    4     FB2_16       (b)     (b)    +          

Signals Used by Logic in Function Block
  1: Cnt1000<0>         8: Cnt100<3>         15: Cnt1<2> 
  2: Cnt1000<1>         9: Cnt10<0>          16: Cnt1<3> 
  3: Cnt1000<2>        10: Cnt10<1>          17: CntClk 
  4: Cnt1000<3>        11: Cnt10<2>          18: DSel0 
  5: Cnt100<0>         12: Cnt10<3>          19: DSel1 
  6: Cnt100<1>         13: Cnt1<0>           20: DSel2 
  7: Cnt100<2>         14: Cnt1<1>           21: DSel3 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
MuxDisplInstance/Tetr<0> 
                  X...X...X...X....XXXX................... 8       
Cnt100<0>         ........XXXXXXXXX....................... 9       
Cnt1<2>           ............XX..X....................... 3       
Cnt1<1>           ............XXXXX....................... 5       
Cnt1<3>           ............XXXXX....................... 5       
Cnt100<2>         ....XX..XXXXXXXXX....................... 11      
Cnt100<1>         ....XXXXXXXXXXXXX....................... 13      
Cnt100<3>         ....XXXXXXXXXXXXX....................... 13      
Cnt1000<0>        ....XXXXXXXXXXXXX....................... 13      
Cnt1000<2>        XX..XXXXXXXXXXXXX....................... 15      
Cnt1000<3>        XXXXXXXXXXXXXXXXX....................... 17      
Cnt10<0>          ............XXXXX....................... 5       
Cnt10<2>          ........XX..XXXXX....................... 7       
Cnt10<1>          ........XXXXXXXXX....................... 9       
Cnt10<3>          ........XXXXXXXXX....................... 9       
Cnt1000<1>        XXXXXXXXXXXXXXXXX....................... 17      
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB3  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               31/9
Number of function block control terms used/remaining:        2/2
Number of PLA product terms used/remaining:                   30/26
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
DelayCnt<2>                   3     FB3_1   136  I/O     (b)        +      
DelayCnt<1>                   3     FB3_2   135  I/O     (b)        +      
DelayCnt<0>                   3     FB3_3   134  I/O     (b)        +      
FDiv<5>                       2     FB3_4        (b)     (b)    +          
N_PZ_459                      1     FB3_5   133  I/O     (b)               
FDiv<4>                       2     FB3_6        (b)     (b)    +          
FDiv<3>                       2     FB3_7        (b)     (b)    +          
FDiv<2>                       2     FB3_8        (b)     (b)    +          
FDiv<1>                       2     FB3_9        (b)     (b)    +          
FDiv<0>                       1     FB3_10       (b)     (b)    +          
Cnt1<0>                       1     FB3_11       (b)     (b)               
MuxDisplInstance/Tetr<3>      4     FB3_12       (b)     (b)               
MuxDisplInstance/Tetr<2>      4     FB3_13       (b)     (b)               
MuxDisplInstance/SelCnt<1>    2     FB3_14  132  I/O     (b)               
MuxDisplInstance/Tetr<1>      4     FB3_15       (b)     (b)               
MuxDisplInstance/SelCnt<0>    1     FB3_16  131  I/O     (b)               

Signals Used by Logic in Function Block
  1: Cnt1000<1>        12: Cnt1<3>           22: FClk 
  2: Cnt1000<2>        13: CntClk            23: FDiv<0> 
  3: Cnt1000<3>        14: DSel0             24: FDiv<1> 
  4: Cnt100<1>         15: DSel1             25: FDiv<2> 
  5: Cnt100<2>         16: DSel2             26: FDiv<3> 
  6: Cnt100<3>         17: DSel3             27: FDiv<4> 
  7: Cnt10<1>          18: DelayCnt<0>       28: FDiv<5> 
  8: Cnt10<2>          19: DelayCnt<1>       29: MuxDisplInstance/SelCnt<0> 
  9: Cnt10<3>          20: DelayCntClear     30: N_PZ_459 
 10: Cnt1<1>           21: DelayCntEnable    31: Reset 
 11: Cnt1<2>          

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
DelayCnt<2>       .................XX.X......X.X.......... 5       
DelayCnt<1>       .................X..X......X.X.......... 4       
DelayCnt<0>       ....................X......X.X.......... 3       
FDiv<5>           .....................XXXXXX............. 6       
N_PZ_459          ...................X..........X......... 2       
FDiv<4>           .....................XXXXX.............. 5       
FDiv<3>           .....................XXXX............... 4       
FDiv<2>           .....................XXX................ 3       
FDiv<1>           .....................XX................. 2       
FDiv<0>           .....................X.................. 1       
Cnt1<0>           ............X........................... 1       
MuxDisplInstance/Tetr<3> 
                  ..X..X..X..X.XXXX....................... 8       
MuxDisplInstance/Tetr<2> 
                  .X..X..X..X..XXXX....................... 8       
MuxDisplInstance/SelCnt<1> 
                  ........................X...X........... 2       
MuxDisplInstance/Tetr<1> 
                  X..X..X..X...XXXX....................... 8       
MuxDisplInstance/SelCnt<0> 
                  ........................X............... 1       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB4  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               6/34
Number of function block control terms used/remaining:        2/2
Number of PLA product terms used/remaining:                   3/53
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB4_1   11   I/O           
(unused)                      0     FB4_2   12   I/O           
(unused)                      0     FB4_3   13   I/O           
(unused)                      0     FB4_4   14   I/O           
(unused)                      0     FB4_5   15   I/O           
(unused)                      0     FB4_6   16   I/O           
(unused)                      0     FB4_7        (b)           
(unused)                      0     FB4_8        (b)           
(unused)                      0     FB4_9        (b)           
(unused)                      0     FB4_10       (b)           
(unused)                      0     FB4_11       (b)           
(unused)                      0     FB4_12  17   I/O           
(unused)                      0     FB4_13       (b)           
(unused)                      0     FB4_14  18   I/O           
(unused)                      0     FB4_15       (b)           
DelayCnt<3>                   3     FB4_16       (b)     (b)    +   +      

Signals Used by Logic in Function Block
  1: DelayCnt<0>        3: DelayCnt<2>        5: FDiv<5> 
  2: DelayCnt<1>        4: DelayCntEnable     6: N_PZ_459 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
DelayCnt<3>       XXXXXX.................................. 6       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB5  ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB5_1        (b)           
(unused)                      0     FB5_2   33   I/O           
(unused)                      0     FB5_3        (b)           
(unused)                      0     FB5_4   32   GCK/I/O       
(unused)                      0     FB5_5   31   I/O           
(unused)                      0     FB5_6   30   GCK/I/O       
(unused)                      0     FB5_7        (b)           
(unused)                      0     FB5_8        (b)           
(unused)                      0     FB5_9        (b)           
(unused)                      0     FB5_10       (b)           
(unused)                      0     FB5_11       (b)           
(unused)                      0     FB5_12       (b)           
(unused)                      0     FB5_13       (b)           
(unused)                      0     FB5_14  28   I/O           
(unused)                      0     FB5_15       (b)           
(unused)                      0     FB5_16       (b)           
*********************************** FB6  ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB6_1   34   I/O           
(unused)                      0     FB6_2   35   CDR/I/O       
(unused)                      0     FB6_3        (b)           
(unused)                      0     FB6_4   38   GCK/I/O GCK   
(unused)                      0     FB6_5        (b)           
(unused)                      0     FB6_6        (b)           
(unused)                      0     FB6_7        (b)           
(unused)                      0     FB6_8        (b)           
(unused)                      0     FB6_9        (b)           
(unused)                      0     FB6_10       (b)           
(unused)                      0     FB6_11       (b)           
(unused)                      0     FB6_12  39   DGE/I/O       
(unused)                      0     FB6_13  40   I/O           
(unused)                      0     FB6_14  41   I/O           
(unused)                      0     FB6_15  42   I/O           
(unused)                      0     FB6_16  43   I/O           
*********************************** FB7  ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB7_1        (b)           
(unused)                      0     FB7_2        (b)           
(unused)                      0     FB7_3        (b)           
(unused)                      0     FB7_4        (b)           
(unused)                      0     FB7_5   26   I/O           
(unused)                      0     FB7_6   25   I/O           
(unused)                      0     FB7_7        (b)           
(unused)                      0     FB7_8        (b)           
(unused)                      0     FB7_9        (b)           
(unused)                      0     FB7_10       (b)           
(unused)                      0     FB7_11  24   I/O           
(unused)                      0     FB7_12  23   I/O           
(unused)                      0     FB7_13  22   I/O           
(unused)                      0     FB7_14  21   I/O           
(unused)                      0     FB7_15  20   I/O           
(unused)                      0     FB7_16  19   I/O           
*********************************** FB8  ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB8_1   44   I/O           
(unused)                      0     FB8_2   45   I/O           
(unused)                      0     FB8_3   46   I/O           
(unused)                      0     FB8_4        (b)           
(unused)                      0     FB8_5   48   I/O           
(unused)                      0     FB8_6   49   I/O           
(unused)                      0     FB8_7        (b)           
(unused)                      0     FB8_8        (b)           
(unused)                      0     FB8_9        (b)           
(unused)                      0     FB8_10       (b)           
(unused)                      0     FB8_11  50   I/O           
(unused)                      0     FB8_12  51   I/O           
(unused)                      0     FB8_13  52   I/O           
(unused)                      0     FB8_14       (b)           
(unused)                      0     FB8_15       (b)           
(unused)                      0     FB8_16       (b)           
*********************************** FB9  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB9_1   112  I/O           
(unused)                      0     FB9_2   113  I/O           
(unused)                      0     FB9_3        (b)           
(unused)                      0     FB9_4   114  I/O           
(unused)                      0     FB9_5        (b)           
(unused)                      0     FB9_6   115  I/O           
(unused)                      0     FB9_7        (b)           
(unused)                      0     FB9_8        (b)           
(unused)                      0     FB9_9        (b)           
(unused)                      0     FB9_10       (b)           
(unused)                      0     FB9_11       (b)           
(unused)                      0     FB9_12  116  I/O           
(unused)                      0     FB9_13  117  I/O           
(unused)                      0     FB9_14  118  I/O           
(unused)                      0     FB9_15  119  I/O           
(unused)                      0     FB9_16       (b)           
*********************************** FB10 ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB10_1  111  I/O           
(unused)                      0     FB10_2  110  I/O           
(unused)                      0     FB10_3  107  I/O           
(unused)                      0     FB10_4  106  I/O           
(unused)                      0     FB10_5  105  I/O           
(unused)                      0     FB10_6  104  I/O           
(unused)                      0     FB10_7       (b)           
(unused)                      0     FB10_8       (b)           
(unused)                      0     FB10_9       (b)           
(unused)                      0     FB10_10      (b)           
(unused)                      0     FB10_11      (b)           
(unused)                      0     FB10_12 103  I/O           
(unused)                      0     FB10_13      (b)           
(unused)                      0     FB10_14 102  I/O           
(unused)                      0     FB10_15      (b)           
(unused)                      0     FB10_16 101  I/O           
*********************************** FB11 ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               2/38
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   4/52
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB11_1       (b)           
(unused)                      0     FB11_2       (b)           
(unused)                      0     FB11_3       (b)           
(unused)                      0     FB11_4       (b)           
(unused)                      0     FB11_5  120  I/O           
(unused)                      0     FB11_6  121  I/O           
(unused)                      0     FB11_7       (b)           
(unused)                      0     FB11_8       (b)           
(unused)                      0     FB11_9       (b)           
(unused)                      0     FB11_10      (b)           
(unused)                      0     FB11_11 124  I/O           
(unused)                      0     FB11_12 125  I/O           
DSel0                         1     FB11_13 126  I/O     O                 
DSel1                         1     FB11_14 128  I/O     O                 
DSel2                         1     FB11_15 129  I/O     O                 
DSel3                         1     FB11_16 130  I/O     O                 

Signals Used by Logic in Function Block
  1: MuxDisplInstance/SelCnt<0>   2: MuxDisplInstance/SelCnt<1> 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
DSel0             XX...................................... 2       
DSel1             XX...................................... 2       
DSel2             XX...................................... 2       
DSel3             XX...................................... 2       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB12 ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB12_1       (b)           
(unused)                      0     FB12_2  100  I/O           
(unused)                      0     FB12_3       (b)           
(unused)                      0     FB12_4       (b)           
(unused)                      0     FB12_5       (b)           
(unused)                      0     FB12_6       (b)           
(unused)                      0     FB12_7       (b)           
(unused)                      0     FB12_8       (b)           
(unused)                      0     FB12_9       (b)           
(unused)                      0     FB12_10      (b)           
(unused)                      0     FB12_11 98   I/O           
(unused)                      0     FB12_12 97   I/O           
(unused)                      0     FB12_13 96   I/O           
(unused)                      0     FB12_14 95   I/O           
(unused)                      0     FB12_15 94   I/O     I     
(unused)                      0     FB12_16      (b)           
*********************************** FB13 ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB13_1  75   I/O           
(unused)                      0     FB13_2  76   I/O           
(unused)                      0     FB13_3  77   I/O           
(unused)                      0     FB13_4       (b)           
(unused)                      0     FB13_5  78   I/O           
(unused)                      0     FB13_6  79   I/O           
(unused)                      0     FB13_7       (b)           
(unused)                      0     FB13_8       (b)           
(unused)                      0     FB13_9       (b)           
(unused)                      0     FB13_10      (b)           
(unused)                      0     FB13_11      (b)           
(unused)                      0     FB13_12 80   I/O           
(unused)                      0     FB13_13 81   I/O           
(unused)                      0     FB13_14 82   I/O           
(unused)                      0     FB13_15      (b)           
(unused)                      0     FB13_16      (b)           
*********************************** FB14 ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               4/36
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   3/53
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB14_1  74   I/O           
(unused)                      0     FB14_2  71   I/O           
(unused)                      0     FB14_3  70   I/O           
(unused)                      0     FB14_4  69   I/O           
(unused)                      0     FB14_5       (b)           
(unused)                      0     FB14_6  68   I/O           
(unused)                      0     FB14_7       (b)           
(unused)                      0     FB14_8       (b)           
(unused)                      0     FB14_9       (b)           
(unused)                      0     FB14_10      (b)           
(unused)                      0     FB14_11      (b)           
(unused)                      0     FB14_12      (b)           
(unused)                      0     FB14_13 66   I/O           
(unused)                      0     FB14_14 64   I/O           
(unused)                      0     FB14_15      (b)           
Seg_G                         3     FB14_16 61   I/O     O                 

Signals Used by Logic in Function Block
  1: MuxDisplInstance/Tetr<0>   3: MuxDisplInstance/Tetr<2>   4: MuxDisplInstance/Tetr<3> 
  2: MuxDisplInstance/Tetr<1> 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
Seg_G             XXXX.................................... 4       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB15 ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB15_1       (b)           
(unused)                      0     FB15_2  83   I/O           
(unused)                      0     FB15_3       (b)           
(unused)                      0     FB15_4       (b)           
(unused)                      0     FB15_5       (b)           
(unused)                      0     FB15_6       (b)           
(unused)                      0     FB15_7       (b)           
(unused)                      0     FB15_8       (b)           
(unused)                      0     FB15_9       (b)           
(unused)                      0     FB15_10      (b)           
(unused)                      0     FB15_11 85   I/O           
(unused)                      0     FB15_12 86   I/O           
(unused)                      0     FB15_13 87   I/O           
(unused)                      0     FB15_14 88   I/O           
(unused)                      0     FB15_15 91   I/O           
(unused)                      0     FB15_16 92   I/O           
*********************************** FB16 ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               4/36
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   15/41
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB16_1       (b)           
(unused)                      0     FB16_2       (b)           
(unused)                      0     FB16_3       (b)           
(unused)                      0     FB16_4       (b)           
Seg_C                         3     FB16_5  60   I/O     O                 
Seg_K                         0     FB16_6  59   I/O     O                 
(unused)                      0     FB16_7       (b)           
(unused)                      0     FB16_8       (b)           
(unused)                      0     FB16_9       (b)           
(unused)                      0     FB16_10      (b)           
Seg_D                         4     FB16_11 58   I/O     O                 
Seg_E                         3     FB16_12 57   I/O     O                 
Seg_A                         3     FB16_13 56   I/O     O                 
(unused)                      0     FB16_14      (b)           
Seg_F                         3     FB16_15 54   I/O     O                 
Seg_B                         3     FB16_16 53   I/O     O                 

Signals Used by Logic in Function Block
  1: MuxDisplInstance/Tetr<0>   3: MuxDisplInstance/Tetr<2>   4: MuxDisplInstance/Tetr<3> 
  2: MuxDisplInstance/Tetr<1> 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
Seg_C             XXXX.................................... 4       
Seg_K             ........................................ 0       
Seg_D             XXXX.................................... 4       
Seg_E             XXXX.................................... 4       
Seg_A             XXXX.................................... 4       
Seg_F             XXXX.................................... 4       
Seg_B             XXXX.................................... 4       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********

FDCPE_AutomatState_FFd1: FDCPE port map (AutomatState_FFd1,AutomatState_FFd1_D,Clk,NOT Reset,'0','1');
AutomatState_FFd1_D <= ((AutomatState_FFd4 AND AutomatState_FFd2 AND 
	NOT AutomatState_FFd3)
	OR (NOT KeyIn AND AutomatState_FFd1 AND DelayCnt(0))
	OR (NOT KeyIn AND AutomatState_FFd1 AND DelayCnt(1))
	OR (NOT KeyIn AND AutomatState_FFd1 AND NOT DelayCnt(2))
	OR (NOT KeyIn AND AutomatState_FFd1 AND DelayCnt(3))
	OR (NOT KeyIn AND AutomatState_FFd1 AND DelayCnt(4)));

FDCPE_AutomatState_FFd2: FDCPE port map (AutomatState_FFd2,AutomatState_FFd2_D,Clk,NOT Reset,'0','1');
AutomatState_FFd2_D <= NOT (((AutomatState_FFd4 AND NOT AutomatState_FFd2 AND 
	NOT AutomatState_FFd1)
	OR (NOT AutomatState_FFd2 AND NOT AutomatState_FFd1 AND 
	NOT AutomatState_FFd3)
	OR (NOT AutomatState_FFd4 AND NOT AutomatState_FFd1 AND 
	NOT AutomatState_FFd3 AND DelayCnt(0) AND DelayCnt(1) AND NOT DelayCnt(2) AND 
	NOT DelayCnt(3) AND NOT DelayCnt(4))));

FTCPE_AutomatState_FFd3: FTCPE port map (AutomatState_FFd3,AutomatState_FFd3_T,Clk,NOT Reset,'0','1');
AutomatState_FFd3_T <= ((AutomatState_FFd4 AND NOT AutomatState_FFd2 AND 
	NOT AutomatState_FFd3)
	OR (KeyIn AND AutomatState_FFd1 AND NOT AutomatState_FFd3)
	OR (AutomatState_FFd4 AND KeyIn AND NOT AutomatState_FFd1 AND 
	AutomatState_FFd3)
	OR (AutomatState_FFd4 AND NOT KeyIn AND AutomatState_FFd2 AND 
	AutomatState_FFd3)
	OR (NOT KeyIn AND AutomatState_FFd2 AND AutomatState_FFd3 AND 
	NOT DelayCnt(0) AND NOT DelayCnt(1) AND DelayCnt(2) AND DelayCnt(3) AND 
	DelayCnt(4)));

FDCPE_AutomatState_FFd4: FDCPE port map (AutomatState_FFd4,AutomatState_FFd4_D,Clk,NOT Reset,'0','1');
AutomatState_FFd4_D <= (AutomatState_FFd4 AND NOT KeyIn AND NOT AutomatState_FFd2)
	XOR ((KeyIn AND AutomatState_FFd1)
	OR (AutomatState_FFd4 AND KeyIn AND NOT AutomatState_FFd2 AND 
	NOT AutomatState_FFd3)
	OR (NOT AutomatState_FFd4 AND KeyIn AND AutomatState_FFd2 AND 
	AutomatState_FFd3)
	OR (NOT AutomatState_FFd4 AND NOT KeyIn AND NOT AutomatState_FFd2 AND 
	NOT AutomatState_FFd3)
	OR (NOT AutomatState_FFd4 AND AutomatState_FFd1 AND 
	NOT DelayCnt(0) AND NOT DelayCnt(1) AND DelayCnt(2) AND NOT DelayCnt(3) AND 
	NOT DelayCnt(4))
	OR (AutomatState_FFd2 AND AutomatState_FFd1 AND 
	NOT DelayCnt(0) AND NOT DelayCnt(1) AND DelayCnt(2) AND NOT DelayCnt(3) AND 
	NOT DelayCnt(4))
	OR (NOT AutomatState_FFd4 AND AutomatState_FFd2 AND 
	AutomatState_FFd3 AND NOT DelayCnt(0) AND NOT DelayCnt(1) AND DelayCnt(2) AND 
	DelayCnt(3) AND DelayCnt(4))
	OR (AutomatState_FFd4 AND NOT KeyIn AND NOT AutomatState_FFd2 AND 
	AutomatState_FFd3 AND DelayCnt(0) AND DelayCnt(1) AND NOT DelayCnt(2) AND 
	NOT DelayCnt(3) AND NOT DelayCnt(4)));

FTCPE_Cnt10000: FTCPE port map (Cnt1000(0),Cnt1000_T(0),CntClk,NOT Reset,'0','1');
Cnt1000_T(0) <= (NOT Cnt100(1) AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND 
	NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND 
	Cnt10(3) AND NOT Cnt100(2) AND Cnt100(3));

FTCPE_Cnt10001: FTCPE port map (Cnt1000(1),Cnt1000_T(1),CntClk,NOT Reset,'0','1');
Cnt1000_T(1) <= ((NOT Cnt100(1) AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND 
	NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND 
	Cnt10(3) AND NOT Cnt100(2) AND Cnt100(3) AND Cnt1000(1) AND Cnt1000(0))
	OR (NOT Cnt100(1) AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND 
	NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND 
	Cnt10(3) AND NOT Cnt100(2) AND Cnt100(3) AND Cnt1000(0) AND Cnt1000(2))
	OR (NOT Cnt100(1) AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND 
	NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND 
	Cnt10(3) AND NOT Cnt100(2) AND Cnt100(3) AND Cnt1000(0) AND NOT Cnt1000(3)));

FTCPE_Cnt10002: FTCPE port map (Cnt1000(2),Cnt1000_T(2),CntClk,NOT Reset,'0','1');
Cnt1000_T(2) <= (NOT Cnt100(1) AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND 
	NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND 
	Cnt10(3) AND NOT Cnt100(2) AND Cnt100(3) AND Cnt1000(1) AND Cnt1000(0));

FTCPE_Cnt10003: FTCPE port map (Cnt1000(3),Cnt1000_T(3),CntClk,NOT Reset,'0','1');
Cnt1000_T(3) <= ((NOT Cnt100(1) AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND 
	NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND 
	Cnt10(3) AND NOT Cnt100(2) AND Cnt100(3) AND Cnt1000(1) AND Cnt1000(0) AND 
	Cnt1000(2))
	OR (NOT Cnt100(1) AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND 
	NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND 
	Cnt10(3) AND NOT Cnt100(2) AND Cnt100(3) AND NOT Cnt1000(1) AND Cnt1000(0) AND 
	NOT Cnt1000(2) AND Cnt1000(3)));

FTCPE_Cnt1000: FTCPE port map (Cnt100(0),Cnt100_T(0),CntClk,NOT Reset,'0','1');
Cnt100_T(0) <= (Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND 
	Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3));

FTCPE_Cnt1001: FTCPE port map (Cnt100(1),Cnt100_T(1),CntClk,NOT Reset,'0','1');
Cnt100_T(1) <= ((Cnt100(1) AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND 
	NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND 
	Cnt10(3))
	OR (Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND 
	NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3) AND 
	Cnt100(2))
	OR (Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND 
	NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3) AND 
	NOT Cnt100(3)));

FTCPE_Cnt1002: FTCPE port map (Cnt100(2),Cnt100_T(2),CntClk,NOT Reset,'0','1');
Cnt100_T(2) <= (Cnt100(1) AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND 
	NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND 
	Cnt10(3));

FTCPE_Cnt1003: FTCPE port map (Cnt100(3),Cnt100_T(3),CntClk,NOT Reset,'0','1');
Cnt100_T(3) <= ((Cnt100(1) AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND 
	NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND 
	Cnt10(3) AND Cnt100(2))
	OR (NOT Cnt100(1) AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND 
	NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND 
	Cnt10(3) AND NOT Cnt100(2) AND Cnt100(3)));

FTCPE_Cnt100: FTCPE port map (Cnt10(0),Cnt10_T(0),CntClk,NOT Reset,'0','1');
Cnt10_T(0) <= (Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3));

FTCPE_Cnt101: FTCPE port map (Cnt10(1),Cnt10_T(1),CntClk,NOT Reset,'0','1');
Cnt10_T(1) <= ((Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND 
	Cnt1(3) AND Cnt10(1))
	OR (Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND 
	Cnt1(3) AND Cnt10(2))
	OR (Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND 
	Cnt1(3) AND NOT Cnt10(3)));

FTCPE_Cnt102: FTCPE port map (Cnt10(2),Cnt10_T(2),CntClk,NOT Reset,'0','1');
Cnt10_T(2) <= (Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND 
	Cnt1(3) AND Cnt10(1));

FTCPE_Cnt103: FTCPE port map (Cnt10(3),Cnt10_T(3),CntClk,NOT Reset,'0','1');
Cnt10_T(3) <= ((Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND 
	Cnt1(3) AND Cnt10(1) AND Cnt10(2))
	OR (Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND 
	Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3)));

FTCPE_Cnt10: FTCPE port map (Cnt1(0),'0',CntClk,NOT Reset,'0','1');

FTCPE_Cnt11: FTCPE port map (Cnt1(1),Cnt1_T(1),CntClk,NOT Reset,'0','1');
Cnt1_T(1) <= NOT (((NOT Cnt1(0))
	OR (NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3))));

FTCPE_Cnt12: FTCPE port map (Cnt1(2),Cnt1_T(2),CntClk,NOT Reset,'0','1');
Cnt1_T(2) <= (Cnt1(0) AND Cnt1(1));

FTCPE_Cnt13: FTCPE port map (Cnt1(3),Cnt1_T(3),CntClk,NOT Reset,'0','1');
Cnt1_T(3) <= ((Cnt1(0) AND Cnt1(1) AND Cnt1(2))
	OR (Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3)));

FDCPE_CntClk: FDCPE port map (CntClk,CntClk_D,Clk,'0','0','1');
CntClk_D <= ((CntClk AND NOT Reset)
	OR (Reset AND AutomatState_FFd4 AND AutomatState_FFd2 AND 
	NOT AutomatState_FFd3)
	OR (Reset AND NOT AutomatState_FFd4 AND NOT AutomatState_FFd2 AND 
	AutomatState_FFd3));


DSel0 <= NOT ((NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1)));


DSel1 <= NOT ((MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1)));


DSel2 <= NOT ((NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1)));


DSel3 <= NOT ((MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1)));

FTCPE_DelayCnt0: FTCPE port map (DelayCnt(0),DelayCntEnable,FDiv(5),NOT N_PZ_459,'0','1');

FTCPE_DelayCnt1: FTCPE port map (DelayCnt(1),DelayCnt_T(1),FDiv(5),NOT N_PZ_459,'0','1');
DelayCnt_T(1) <= (DelayCnt(0) AND DelayCntEnable);

FTCPE_DelayCnt2: FTCPE port map (DelayCnt(2),DelayCnt_T(2),FDiv(5),NOT N_PZ_459,'0','1');
DelayCnt_T(2) <= (DelayCnt(0) AND DelayCntEnable AND DelayCnt(1));

FTCPE_DelayCnt3: FTCPE port map (DelayCnt(3),DelayCnt_T(3),FDiv(5),NOT N_PZ_459,'0','1');
DelayCnt_T(3) <= (DelayCnt(0) AND DelayCntEnable AND DelayCnt(1) AND 
	DelayCnt(2));

FTCPE_DelayCnt4: FTCPE port map (DelayCnt(4),DelayCnt_T(4),FDiv(5),NOT N_PZ_459,'0','1');
DelayCnt_T(4) <= (DelayCnt(0) AND DelayCntEnable AND DelayCnt(1) AND 
	DelayCnt(2) AND DelayCnt(3));

FDCPE_DelayCntClear: FDCPE port map (DelayCntClear,DelayCntClear_D,Clk,'0','0','1');
DelayCntClear_D <= NOT (((NOT Reset AND NOT DelayCntClear)
	OR (Reset AND AutomatState_FFd4 AND AutomatState_FFd2 AND 
	NOT AutomatState_FFd1)
	OR (Reset AND AutomatState_FFd4 AND NOT AutomatState_FFd1 AND 
	NOT AutomatState_FFd3)));

FDCPE_DelayCntEnable: FDCPE port map (DelayCntEnable,DelayCntEnable_D,Clk,'0','0','1');
DelayCntEnable_D <= NOT (((NOT Reset AND NOT DelayCntEnable)
	OR (Reset AND AutomatState_FFd4 AND AutomatState_FFd2 AND 
	NOT AutomatState_FFd1)
	OR (Reset AND NOT AutomatState_FFd2 AND NOT AutomatState_FFd1 AND 
	NOT AutomatState_FFd3)));

FTCPE_FClk: FTCPE port map (FClk,FClk_T,NOT Clk,NOT Reset,'0','1');
FClk_T <= (FDivInstance/FDivCnt(0) AND FDivInstance/FDivCnt(1) AND 
	FDivInstance/FDivCnt(2) AND FDivInstance/FDivCnt(3) AND FDivInstance/FDivCnt(4) AND 
	FDivInstance/FDivCnt(5) AND FDivInstance/FDivCnt(6));

FTCPE_FDiv0: FTCPE port map (FDiv(0),'0',FClk,NOT Reset,'0','1');

FTCPE_FDiv1: FTCPE port map (FDiv(1),FDiv(0),FClk,NOT Reset,'0','1');

FTCPE_FDiv2: FTCPE port map (FDiv(2),FDiv_T(2),FClk,NOT Reset,'0','1');
FDiv_T(2) <= (FDiv(0) AND FDiv(1));

FTCPE_FDiv3: FTCPE port map (FDiv(3),FDiv_T(3),FClk,NOT Reset,'0','1');
FDiv_T(3) <= (FDiv(2) AND FDiv(0) AND FDiv(1));

FTCPE_FDiv4: FTCPE port map (FDiv(4),FDiv_T(4),FClk,NOT Reset,'0','1');
FDiv_T(4) <= (FDiv(2) AND FDiv(0) AND FDiv(1) AND FDiv(3));

FTCPE_FDiv5: FTCPE port map (FDiv(5),FDiv_T(5),FClk,NOT Reset,'0','1');
FDiv_T(5) <= (FDiv(2) AND FDiv(0) AND FDiv(1) AND FDiv(3) AND 
	FDiv(4));

FTCPE_FDivInstance/FDivCnt0: FTCPE port map (FDivInstance/FDivCnt(0),'0',NOT Clk,NOT Reset,'0','1');

FTCPE_FDivInstance/FDivCnt1: FTCPE port map (FDivInstance/FDivCnt(1),FDivInstance/FDivCnt(0),NOT Clk,NOT Reset,'0','1');

FTCPE_FDivInstance/FDivCnt2: FTCPE port map (FDivInstance/FDivCnt(2),FDivInstance/FDivCnt_T(2),NOT Clk,NOT Reset,'0','1');
FDivInstance/FDivCnt_T(2) <= (FDivInstance/FDivCnt(0) AND FDivInstance/FDivCnt(1));

FTCPE_FDivInstance/FDivCnt3: FTCPE port map (FDivInstance/FDivCnt(3),FDivInstance/FDivCnt_T(3),NOT Clk,NOT Reset,'0','1');
FDivInstance/FDivCnt_T(3) <= (FDivInstance/FDivCnt(0) AND FDivInstance/FDivCnt(1) AND 
	FDivInstance/FDivCnt(2));

FTCPE_FDivInstance/FDivCnt4: FTCPE port map (FDivInstance/FDivCnt(4),FDivInstance/FDivCnt_T(4),NOT Clk,NOT Reset,'0','1');
FDivInstance/FDivCnt_T(4) <= (FDivInstance/FDivCnt(0) AND FDivInstance/FDivCnt(1) AND 
	FDivInstance/FDivCnt(2) AND FDivInstance/FDivCnt(3));

FTCPE_FDivInstance/FDivCnt5: FTCPE port map (FDivInstance/FDivCnt(5),FDivInstance/FDivCnt_T(5),NOT Clk,NOT Reset,'0','1');
FDivInstance/FDivCnt_T(5) <= (FDivInstance/FDivCnt(0) AND FDivInstance/FDivCnt(1) AND 
	FDivInstance/FDivCnt(2) AND FDivInstance/FDivCnt(3) AND FDivInstance/FDivCnt(4));

FTCPE_FDivInstance/FDivCnt6: FTCPE port map (FDivInstance/FDivCnt(6),FDivInstance/FDivCnt_T(6),NOT Clk,NOT Reset,'0','1');
FDivInstance/FDivCnt_T(6) <= (FDivInstance/FDivCnt(0) AND FDivInstance/FDivCnt(1) AND 
	FDivInstance/FDivCnt(2) AND FDivInstance/FDivCnt(3) AND FDivInstance/FDivCnt(4) AND 
	FDivInstance/FDivCnt(5));

FTCPE_MuxDisplInstance/SelCnt0: FTCPE port map (MuxDisplInstance/SelCnt(0),'0',FDiv(2),NOT Reset,'0','1');

FTCPE_MuxDisplInstance/SelCnt1: FTCPE port map (MuxDisplInstance/SelCnt(1),MuxDisplInstance/SelCnt(0),FDiv(2),NOT Reset,'0','1');


MuxDisplInstance/Tetr(0) <= ((Cnt100(0) AND NOT DSel2)
	OR (Cnt10(0) AND NOT DSel1)
	OR (Cnt1(0) AND NOT DSel0)
	OR (Cnt1000(0) AND NOT DSel3));


MuxDisplInstance/Tetr(1) <= ((Cnt100(1) AND NOT DSel2)
	OR (Cnt1(1) AND NOT DSel0)
	OR (Cnt10(1) AND NOT DSel1)
	OR (Cnt1000(1) AND NOT DSel3));


MuxDisplInstance/Tetr(2) <= ((Cnt1(2) AND NOT DSel0)
	OR (Cnt10(2) AND NOT DSel1)
	OR (Cnt100(2) AND NOT DSel2)
	OR (Cnt1000(2) AND NOT DSel3));


MuxDisplInstance/Tetr(3) <= ((Cnt1(3) AND NOT DSel0)
	OR (Cnt10(3) AND NOT DSel1)
	OR (Cnt100(3) AND NOT DSel2)
	OR (Cnt1000(3) AND NOT DSel3));


N_PZ_459 <= (Reset AND DelayCntClear);


Seg_A <= (NOT MuxDisplInstance/Tetr(1) AND 
	MuxDisplInstance/Tetr(0))
	XOR ((NOT MuxDisplInstance/Tetr(1) AND 
	NOT MuxDisplInstance/Tetr(3) AND MuxDisplInstance/Tetr(2))
	OR (MuxDisplInstance/Tetr(0) AND 
	MuxDisplInstance/Tetr(3) AND NOT MuxDisplInstance/Tetr(2)));


Seg_B <= (NOT MuxDisplInstance/Tetr(0) AND 
	MuxDisplInstance/Tetr(2))
	XOR ((MuxDisplInstance/Tetr(1) AND 
	MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(3))
	OR (NOT MuxDisplInstance/Tetr(1) AND 
	NOT MuxDisplInstance/Tetr(3) AND MuxDisplInstance/Tetr(2)));


Seg_C <= ((MuxDisplInstance/Tetr(1) AND 
	MuxDisplInstance/Tetr(3) AND MuxDisplInstance/Tetr(2))
	OR (NOT MuxDisplInstance/Tetr(0) AND 
	MuxDisplInstance/Tetr(3) AND MuxDisplInstance/Tetr(2))
	OR (MuxDisplInstance/Tetr(1) AND 
	NOT MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(3) AND 
	NOT MuxDisplInstance/Tetr(2)));


Seg_D <= ((MuxDisplInstance/Tetr(1) AND 
	MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(2))
	OR (MuxDisplInstance/Tetr(1) AND 
	NOT MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(3) AND 
	NOT MuxDisplInstance/Tetr(2))
	OR (NOT MuxDisplInstance/Tetr(1) AND 
	MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(3) AND 
	NOT MuxDisplInstance/Tetr(2))
	OR (NOT MuxDisplInstance/Tetr(1) AND 
	NOT MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(3) AND 
	MuxDisplInstance/Tetr(2)));


Seg_E <= ((MuxDisplInstance/Tetr(0) AND 
	NOT MuxDisplInstance/Tetr(3))
	OR (NOT MuxDisplInstance/Tetr(1) AND 
	MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(2))
	OR (NOT MuxDisplInstance/Tetr(1) AND 
	NOT MuxDisplInstance/Tetr(3) AND MuxDisplInstance/Tetr(2)));


Seg_F <= (MuxDisplInstance/Tetr(0) AND 
	NOT MuxDisplInstance/Tetr(3))
	XOR ((NOT MuxDisplInstance/Tetr(1) AND 
	MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(2))
	OR (MuxDisplInstance/Tetr(1) AND 
	NOT MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(3) AND 
	NOT MuxDisplInstance/Tetr(2)));


Seg_G <= ((NOT MuxDisplInstance/Tetr(1) AND 
	NOT MuxDisplInstance/Tetr(3) AND NOT MuxDisplInstance/Tetr(2))
	OR (MuxDisplInstance/Tetr(1) AND 
	MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(3) AND 
	MuxDisplInstance/Tetr(2))
	OR (NOT MuxDisplInstance/Tetr(1) AND 
	NOT MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(3) AND 
	MuxDisplInstance/Tetr(2)));


Seg_K <= NOT ('0');


Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE); 
 FDDCPE (Q,D,C,CLR,PRE,CE); 
 FTCPE (Q,D,C,CLR,PRE,CE); 
 FTDCPE (Q,D,C,CLR,PRE,CE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC2C256-6-TQ144


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 VCC                              73 VCCIO-1.8                     
  2 KPR                              74 KPR                           
  3 KPR                              75 KPR                           
  4 KPR                              76 KPR                           
  5 KPR                              77 KPR                           
  6 KPR                              78 KPR                           
  7 KPR                              79 KPR                           
  8 VCCAUX                           80 KPR                           
  9 KPR                              81 KPR                           
 10 KPR                              82 KPR                           
 11 KPR                              83 KPR                           
 12 KPR                              84 VCC                           
 13 KPR                              85 KPR                           
 14 KPR                              86 KPR                           
 15 KPR                              87 KPR                           
 16 KPR                              88 KPR                           
 17 KPR                              89 GND                           
 18 KPR                              90 GND                           
 19 KPR                              91 KPR                           
 20 KPR                              92 KPR                           
 21 KPR                              93 VCCIO-1.8                     
 22 KPR                              94 KeyIn                         
 23 KPR                              95 KPR                           
 24 KPR                              96 KPR                           
 25 KPR                              97 KPR                           
 26 KPR                              98 KPR                           
 27 VCCIO-1.8                        99 GND                           
 28 KPR                             100 KPR                           
 29 GND                             101 KPR                           
 30 KPR                             102 KPR                           
 31 KPR                             103 KPR                           
 32 KPR                             104 KPR                           
 33 KPR                             105 KPR                           
 34 KPR                             106 KPR                           
 35 KPR                             107 KPR                           
 36 GND                             108 GND                           
 37 VCC                             109 VCCIO-1.8                     
 38 Clk                             110 KPR                           
 39 KPR                             111 KPR                           
 40 KPR                             112 KPR                           
 41 KPR                             113 KPR                           
 42 KPR                             114 KPR                           
 43 KPR                             115 KPR                           
 44 KPR                             116 KPR                           
 45 KPR                             117 KPR                           
 46 KPR                             118 KPR                           
 47 GND                             119 KPR                           
 48 KPR                             120 KPR                           
 49 KPR                             121 KPR                           
 50 KPR                             122 TDO                           
 51 KPR                             123 GND                           
 52 KPR                             124 KPR                           
 53 Seg_B                           125 KPR                           
 54 Seg_F                           126 DSel0                         
 55 VCCIO-1.8                       127 VCCIO-1.8                     
 56 Seg_A                           128 DSel1                         
 57 Seg_E                           129 DSel2                         
 58 Seg_D                           130 DSel3                         
 59 Seg_K                           131 KPR                           
 60 Seg_C                           132 KPR                           
 61 Seg_G                           133 KPR                           
 62 GND                             134 KPR                           
 63 TDI                             135 KPR                           
 64 KPR                             136 KPR                           
 65 TMS                             137 KPR                           
 66 KPR                             138 KPR                           
 67 TCK                             139 KPR                           
 68 KPR                             140 KPR                           
 69 KPR                             141 VCCIO-1.8                     
 70 KPR                             142 KPR                           
 71 KPR                             143 Reset                         
 72 GND                             144 GND                           


Legend :  NC  = Not Connected, unbonded pin
        PGND  = Unused I/O configured as additional Ground pin
         KPR  = Unused I/O with weak keeper (leave unconnected)
         WPU  = Unused I/O with weak pull up (leave unconnected)
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
      VCCAUX  = Power supply for JTAG pins
   VCCIO-3.3  = I/O supply voltage for LVTTL, LVCMOS33, SSTL3_I
   VCCIO-2.5  = I/O supply voltage for LVCMOS25, SSTL2_I
   VCCIO-1.8  = I/O supply voltage for LVCMOS18
   VCCIO-1.5  = I/O supply voltage for LVCMOS15, HSTL_I
        VREF  = Reference voltage for indicated input standard
       *VREF  = Reference voltage pin selected by software
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc2c256-6-TQ144
Optimization Method                         : DENSITY
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Set Unused I/O Pin Termination              : KEEPER
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
Enable Input Registers                      : ON
Function Block Fan-in Limit                 : 38
Use DATA_GATE Attribute                     : ON
Set Tristate Outputs to Termination Mode    : KEEPER
Default Voltage Standard for All Outputs    : LVCMOS18
Input Limit                                 : 32
Pterm Limit                                 : 28