Equations

********** Mapped Logic **********
DSel0 <= NOT ((NOT SelCnt(0) AND NOT SelCnt(1)));
DSel1 <= NOT ((SelCnt(0) AND NOT SelCnt(1)));
DSel2 <= NOT ((NOT SelCnt(0) AND SelCnt(1)));
DSel3 <= NOT ((SelCnt(0) AND SelCnt(1)));
FTCPE_FDiv0: FTCPE port map (FDiv(0),'0',NOT Clk,NOT Reset,'0','1');
FTCPE_FDiv1: FTCPE port map (FDiv(1),FDiv(0),NOT Clk,NOT Reset,'0','1');
FTCPE_FDiv2: FTCPE port map (FDiv(2),FDiv_T(2),NOT Clk,NOT Reset,'0','1');
     FDiv_T(2) <= (FDiv(0) AND FDiv(1));
FTCPE_FDiv3: FTCPE port map (FDiv(3),FDiv_T(3),NOT Clk,NOT Reset,'0','1');
     FDiv_T(3) <= (FDiv(0) AND FDiv(1) AND FDiv(2));
FTCPE_FDiv4: FTCPE port map (FDiv(4),FDiv_T(4),NOT Clk,NOT Reset,'0','1');
     FDiv_T(4) <= (FDiv(0) AND FDiv(1) AND FDiv(2) AND FDiv(3));
Seg_A <= NOT ('0');
Seg_B <= NOT (((NOT DSel3)
      OR (KeyIn2 AND NOT DSel2)
      OR (KeyIn1 AND NOT DSel1)
      OR (KeyIn0 AND NOT DSel0)));
Seg_C <= NOT (((NOT DSel3)
      OR (KeyIn2 AND NOT DSel2)
      OR (KeyIn1 AND NOT DSel1)
      OR (KeyIn0 AND NOT DSel0)));
Seg_D <= ((NOT DSel3)
      OR (KeyIn2 AND NOT DSel2)
      OR (KeyIn1 AND NOT DSel1)
      OR (KeyIn0 AND NOT DSel0));
Seg_E <= '0';
Seg_F <= '0';
Seg_G <= NOT (((NOT DSel3)
      OR (KeyIn2 AND NOT DSel2)
      OR (KeyIn1 AND NOT DSel1)
      OR (KeyIn0 AND NOT DSel0)));
Seg_K <= NOT ('0');
FTCPE_SelCnt0: FTCPE port map (SelCnt(0),'0',FDiv(4),NOT Reset,'0','1');
FTCPE_SelCnt1: FTCPE port map (SelCnt(1),SelCnt(0),FDiv(4),NOT Reset,'0','1');
Register Legend:
      FDCPE (Q,D,C,CLR,PRE,CE);
      FDDCPE (Q,D,C,CLR,PRE,CE);
      FTCPE (Q,D,C,CLR,PRE,CE);
      FTDCPE (Q,D,C,CLR,PRE,CE);
      LDCP (Q,D,G,CLR,PRE);