Equations

********** Mapped Logic **********
FDCPE_Clr: FDCPE port map (Clr,Clr_D,NOT Clk,'0','0','1');
     Clr_D <= NOT (((NOT Reset AND NOT Clr)
      OR (Reset AND NOT MachineState_FFd1 AND MachineState_FFd3 AND
      NOT MachineState_FFd2)));
FTCPE_Cnt1000000: FTCPE port map (Cnt100000(0),Cnt100000_T(0),FInp,NOT N_PZ_797,'0','1');
     Cnt100000_T(0) <= (RunLed AND Cnt1000(3) AND Cnt1000(0) AND Cnt100(0) AND
      Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND
      NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(1) AND NOT Cnt100(2) AND
      Cnt100(3) AND NOT Cnt1000(1) AND NOT Cnt1000(2) AND Cnt10000(0) AND
      NOT Cnt10000(1) AND NOT Cnt10000(2) AND Cnt10000(3));
FTCPE_Cnt1000001: FTCPE port map (Cnt100000(1),Cnt100000_T(1),FInp,NOT N_PZ_797,'0','1');
     Cnt100000_T(1) <= ((RunLed AND Cnt1000(3) AND Cnt1000(0) AND Cnt100(0) AND
      Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND
      NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(1) AND NOT Cnt100(2) AND
      Cnt100(3) AND NOT Cnt1000(1) AND NOT Cnt1000(2) AND NOT Cnt100000(3) AND
      Cnt10000(0) AND Cnt100000(0) AND NOT Cnt10000(1) AND NOT Cnt10000(2) AND
      Cnt10000(3))
      OR (RunLed AND Cnt1000(3) AND Cnt1000(0) AND Cnt100(0) AND
      Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND
      NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(1) AND NOT Cnt100(2) AND
      Cnt100(3) AND NOT Cnt1000(1) AND NOT Cnt1000(2) AND Cnt10000(0) AND
      Cnt100000(0) AND NOT Cnt10000(1) AND NOT Cnt10000(2) AND Cnt10000(3) AND
      Cnt100000(1))
      OR (RunLed AND Cnt1000(3) AND Cnt1000(0) AND Cnt100(0) AND
      Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND
      NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(1) AND NOT Cnt100(2) AND
      Cnt100(3) AND NOT Cnt1000(1) AND NOT Cnt1000(2) AND Cnt10000(0) AND
      Cnt100000(0) AND NOT Cnt10000(1) AND NOT Cnt10000(2) AND Cnt10000(3) AND
      Cnt100000(2)));
FTCPE_Cnt1000002: FTCPE port map (Cnt100000(2),Cnt100000_T(2),FInp,NOT N_PZ_797,'0','1');
     Cnt100000_T(2) <= (RunLed AND Cnt1000(3) AND Cnt1000(0) AND Cnt100(0) AND
      Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND
      NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(1) AND NOT Cnt100(2) AND
      Cnt100(3) AND NOT Cnt1000(1) AND NOT Cnt1000(2) AND Cnt10000(0) AND
      Cnt100000(0) AND NOT Cnt10000(1) AND NOT Cnt10000(2) AND Cnt10000(3) AND
      Cnt100000(1));
FTCPE_Cnt1000003: FTCPE port map (Cnt100000(3),Cnt100000_T(3),FInp,NOT N_PZ_797,'0','1');
     Cnt100000_T(3) <= ((RunLed AND Cnt1000(3) AND Cnt1000(0) AND Cnt100(0) AND
      Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND
      NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(1) AND NOT Cnt100(2) AND
      Cnt100(3) AND NOT Cnt1000(1) AND NOT Cnt1000(2) AND Cnt10000(0) AND
      Cnt100000(0) AND NOT Cnt10000(1) AND NOT Cnt10000(2) AND Cnt10000(3) AND
      Cnt100000(1) AND Cnt100000(2))
      OR (RunLed AND Cnt1000(3) AND Cnt1000(0) AND Cnt100(0) AND
      Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND
      NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(1) AND NOT Cnt100(2) AND
      Cnt100(3) AND NOT Cnt1000(1) AND NOT Cnt1000(2) AND Cnt100000(3) AND
      Cnt10000(0) AND Cnt100000(0) AND NOT Cnt10000(1) AND NOT Cnt10000(2) AND
      Cnt10000(3) AND NOT Cnt100000(1) AND NOT Cnt100000(2)));
FTCPE_Cnt100000: FTCPE port map (Cnt10000(0),Cnt10000_T(0),FInp,NOT N_PZ_797,'0','1');
     Cnt10000_T(0) <= (RunLed AND Cnt1000(3) AND Cnt1000(0) AND Cnt100(0) AND
      Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND
      NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(1) AND NOT Cnt100(2) AND
      Cnt100(3) AND NOT Cnt1000(1) AND NOT Cnt1000(2));
FTCPE_Cnt100001: FTCPE port map (Cnt10000(1),Cnt10000_T(1),FInp,NOT N_PZ_797,'0','1');
     Cnt10000_T(1) <= ((RunLed AND Cnt1000(3) AND Cnt1000(0) AND Cnt100(0) AND
      Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND
      NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(1) AND NOT Cnt100(2) AND
      Cnt100(3) AND NOT Cnt1000(1) AND NOT Cnt1000(2) AND Cnt10000(0) AND
      Cnt10000(1))
      OR (RunLed AND Cnt1000(3) AND Cnt1000(0) AND Cnt100(0) AND
      Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND
      NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(1) AND NOT Cnt100(2) AND
      Cnt100(3) AND NOT Cnt1000(1) AND NOT Cnt1000(2) AND Cnt10000(0) AND
      Cnt10000(2))
      OR (RunLed AND Cnt1000(3) AND Cnt1000(0) AND Cnt100(0) AND
      Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND
      NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(1) AND NOT Cnt100(2) AND
      Cnt100(3) AND NOT Cnt1000(1) AND NOT Cnt1000(2) AND Cnt10000(0) AND
      NOT Cnt10000(3)));
FTCPE_Cnt100002: FTCPE port map (Cnt10000(2),Cnt10000_T(2),FInp,NOT N_PZ_797,'0','1');
     Cnt10000_T(2) <= (RunLed AND Cnt1000(3) AND Cnt1000(0) AND Cnt100(0) AND
      Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND
      NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(1) AND NOT Cnt100(2) AND
      Cnt100(3) AND NOT Cnt1000(1) AND NOT Cnt1000(2) AND Cnt10000(0) AND
      Cnt10000(1));
FTCPE_Cnt100003: FTCPE port map (Cnt10000(3),Cnt10000_T(3),FInp,NOT N_PZ_797,'0','1');
     Cnt10000_T(3) <= ((RunLed AND Cnt1000(3) AND Cnt1000(0) AND Cnt100(0) AND
      Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND
      NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(1) AND NOT Cnt100(2) AND
      Cnt100(3) AND NOT Cnt1000(1) AND NOT Cnt1000(2) AND Cnt10000(0) AND
      Cnt10000(1) AND Cnt10000(2))
      OR (RunLed AND Cnt1000(3) AND Cnt1000(0) AND Cnt100(0) AND
      Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND
      NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(1) AND NOT Cnt100(2) AND
      Cnt100(3) AND NOT Cnt1000(1) AND NOT Cnt1000(2) AND Cnt10000(0) AND
      NOT Cnt10000(1) AND NOT Cnt10000(2) AND Cnt10000(3)));
FTCPE_Cnt10000: FTCPE port map (Cnt1000(0),Cnt1000_T(0),FInp,NOT N_PZ_797,'0','1');
     Cnt1000_T(0) <= (RunLed AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND
      NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND
      Cnt10(3) AND NOT Cnt100(1) AND NOT Cnt100(2) AND Cnt100(3));
FTCPE_Cnt10001: FTCPE port map (Cnt1000(1),Cnt1000_T(1),FInp,NOT N_PZ_797,'0','1');
     Cnt1000_T(1) <= ((RunLed AND NOT Cnt1000(3) AND Cnt1000(0) AND Cnt100(0) AND
      Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND
      NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(1) AND NOT Cnt100(2) AND
      Cnt100(3))
      OR (RunLed AND Cnt1000(0) AND Cnt100(0) AND Cnt10(0) AND
      Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND
      NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(1) AND NOT Cnt100(2) AND Cnt100(3) AND
      Cnt1000(1))
      OR (RunLed AND Cnt1000(0) AND Cnt100(0) AND Cnt10(0) AND
      Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND
      NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(1) AND NOT Cnt100(2) AND Cnt100(3) AND
      Cnt1000(2)));
FTCPE_Cnt10002: FTCPE port map (Cnt1000(2),Cnt1000_T(2),FInp,NOT N_PZ_797,'0','1');
     Cnt1000_T(2) <= (RunLed AND Cnt1000(0) AND Cnt100(0) AND Cnt10(0) AND
      Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND
      NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(1) AND NOT Cnt100(2) AND Cnt100(3) AND
      Cnt1000(1));
FTCPE_Cnt10003: FTCPE port map (Cnt1000(3),Cnt1000_T(3),FInp,NOT N_PZ_797,'0','1');
     Cnt1000_T(3) <= ((RunLed AND Cnt1000(0) AND Cnt100(0) AND Cnt10(0) AND
      Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND
      NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(1) AND NOT Cnt100(2) AND Cnt100(3) AND
      Cnt1000(1) AND Cnt1000(2))
      OR (RunLed AND Cnt1000(3) AND Cnt1000(0) AND Cnt100(0) AND
      Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND
      NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(1) AND NOT Cnt100(2) AND
      Cnt100(3) AND NOT Cnt1000(1) AND NOT Cnt1000(2)));
FTCPE_Cnt1000: FTCPE port map (Cnt100(0),Cnt100_T(0),FInp,NOT N_PZ_797,'0','1');
     Cnt100_T(0) <= (RunLed AND Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND
      NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3));
FTCPE_Cnt1001: FTCPE port map (Cnt100(1),Cnt100_T(1),FInp,NOT N_PZ_797,'0','1');
     Cnt100_T(1) <= ((RunLed AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND
      NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND
      Cnt10(3) AND Cnt100(1))
      OR (RunLed AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND
      NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND
      Cnt10(3) AND Cnt100(2))
      OR (RunLed AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND
      NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND
      Cnt10(3) AND NOT Cnt100(3)));
FTCPE_Cnt1002: FTCPE port map (Cnt100(2),Cnt100_T(2),FInp,NOT N_PZ_797,'0','1');
     Cnt100_T(2) <= (RunLed AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND
      NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND
      Cnt10(3) AND Cnt100(1));
FTCPE_Cnt1003: FTCPE port map (Cnt100(3),Cnt100_T(3),FInp,NOT N_PZ_797,'0','1');
     Cnt100_T(3) <= ((RunLed AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND
      NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND
      Cnt10(3) AND Cnt100(1) AND Cnt100(2))
      OR (RunLed AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND
      NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND
      Cnt10(3) AND NOT Cnt100(1) AND NOT Cnt100(2) AND Cnt100(3)));
FTCPE_Cnt100: FTCPE port map (Cnt10(0),Cnt10_T(0),FInp,NOT N_PZ_797,'0','1');
     Cnt10_T(0) <= (RunLed AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3));
FTCPE_Cnt101: FTCPE port map (Cnt10(1),Cnt10_T(1),FInp,NOT N_PZ_797,'0','1');
     Cnt10_T(1) <= ((RunLed AND Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND
      NOT Cnt1(2) AND Cnt1(3) AND Cnt10(1))
      OR (RunLed AND Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND
      NOT Cnt1(2) AND Cnt1(3) AND Cnt10(2))
      OR (RunLed AND Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND
      NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(3)));
FTCPE_Cnt102: FTCPE port map (Cnt10(2),Cnt10_T(2),FInp,NOT N_PZ_797,'0','1');
     Cnt10_T(2) <= (RunLed AND Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND
      NOT Cnt1(2) AND Cnt1(3) AND Cnt10(1));
FTCPE_Cnt103: FTCPE port map (Cnt10(3),Cnt10_T(3),FInp,NOT N_PZ_797,'0','1');
     Cnt10_T(3) <= ((RunLed AND Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND
      NOT Cnt1(2) AND Cnt1(3) AND Cnt10(1) AND Cnt10(2))
      OR (RunLed AND Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND
      NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3)));
FTCPE_Cnt10: FTCPE port map (Cnt1(0),RunLed,FInp,NOT N_PZ_797,'0','1');
FTCPE_Cnt11: FTCPE port map (Cnt1(1),Cnt1_T(1),FInp,NOT N_PZ_797,'0','1');
     Cnt1_T(1) <= (RunLed AND Cnt1(0))
      XOR (RunLed AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3));
FTCPE_Cnt12: FTCPE port map (Cnt1(2),Cnt1_T(2),FInp,NOT N_PZ_797,'0','1');
     Cnt1_T(2) <= (RunLed AND Cnt1(0) AND Cnt1(1));
FTCPE_Cnt13: FTCPE port map (Cnt1(3),Cnt1_T(3),FInp,NOT N_PZ_797,'0','1');
     Cnt1_T(3) <= ((RunLed AND Cnt1(0) AND Cnt1(1) AND Cnt1(2))
      OR (RunLed AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3)));
DSel0 <= (NOT MuxDisplInstance/SelCnt(0) AND
      NOT MuxDisplInstance/SelCnt(1));
DSel1 <= (MuxDisplInstance/SelCnt(0) AND
      NOT MuxDisplInstance/SelCnt(1));
DSel2 <= (NOT MuxDisplInstance/SelCnt(0) AND
      MuxDisplInstance/SelCnt(1));
DSel3 <= (MuxDisplInstance/SelCnt(0) AND
      MuxDisplInstance/SelCnt(1));
FTCPE_F1HzCnt0: FTCPE port map (F1HzCnt(0),F1HzEnable,NOT Clk,'0',NOT N_PZ_797,'1');
FTCPE_F1HzCnt1: FTCPE port map (F1HzCnt(1),F1HzCnt_T(1),NOT Clk,'0',NOT N_PZ_797,'1');
     F1HzCnt_T(1) <= (F1HzEnable AND F1HzCnt(0));
FTCPE_F1HzCnt2: FTCPE port map (F1HzCnt(2),F1HzCnt_T(2),NOT Clk,'0',NOT N_PZ_797,'1');
     F1HzCnt_T(2) <= (F1HzEnable AND F1HzCnt(0) AND F1HzCnt(1));
FTCPE_F1HzCnt3: FTCPE port map (F1HzCnt(3),F1HzCnt_T(3),NOT Clk,'0',NOT N_PZ_797,'1');
     F1HzCnt_T(3) <= (F1HzEnable AND F1HzCnt(0) AND F1HzCnt(1) AND
      F1HzCnt(2));
FTCPE_F1HzCnt4: FTCPE port map (F1HzCnt(4),F1HzCnt_T(4),NOT Clk,'0',NOT N_PZ_797,'1');
     F1HzCnt_T(4) <= (F1HzEnable AND F1HzCnt(0) AND F1HzCnt(1) AND
      F1HzCnt(2) AND F1HzCnt(3));
FTCPE_F1HzCnt5: FTCPE port map (F1HzCnt(5),F1HzCnt_T(5),NOT Clk,'0',NOT N_PZ_797,'1');
     F1HzCnt_T(5) <= (F1HzEnable AND F1HzCnt(0) AND F1HzCnt(1) AND
      F1HzCnt(2) AND F1HzCnt(3) AND F1HzCnt(4));
FTCPE_F1HzCnt6: FTCPE port map (F1HzCnt(6),F1HzCnt_T(6),NOT Clk,'0',NOT N_PZ_797,'1');
     F1HzCnt_T(6) <= (F1HzEnable AND F1HzCnt(0) AND F1HzCnt(1) AND
      F1HzCnt(2) AND F1HzCnt(3) AND F1HzCnt(4) AND F1HzCnt(5));
FTCPE_F1HzCnt7: FTCPE port map (F1HzCnt(7),F1HzCnt_T(7),NOT Clk,'0',NOT N_PZ_797,'1');
     F1HzCnt_T(7) <= (F1HzEnable AND F1HzCnt(0) AND F1HzCnt(1) AND
      F1HzCnt(2) AND F1HzCnt(3) AND F1HzCnt(4) AND F1HzCnt(5) AND
      F1HzCnt(6));
FTCPE_F1HzCnt8: FTCPE port map (F1HzCnt(8),F1HzCnt_T(8),NOT Clk,'0',NOT N_PZ_797,'1');
     F1HzCnt_T(8) <= (F1HzEnable AND F1HzCnt(0) AND F1HzCnt(1) AND
      F1HzCnt(2) AND F1HzCnt(3) AND F1HzCnt(4) AND F1HzCnt(5) AND
      F1HzCnt(6) AND F1HzCnt(7));
FTCPE_F1HzCnt9: FTCPE port map (F1HzCnt(9),F1HzCnt_T(9),NOT Clk,'0',NOT N_PZ_797,'1');
     F1HzCnt_T(9) <= (F1HzEnable AND F1HzCnt(0) AND F1HzCnt(1) AND
      F1HzCnt(2) AND F1HzCnt(3) AND F1HzCnt(4) AND F1HzCnt(5) AND
      F1HzCnt(6) AND F1HzCnt(7) AND F1HzCnt(8));
FTCPE_F1HzCnt10: FTCPE port map (F1HzCnt(10),F1HzCnt_T(10),NOT Clk,'0',NOT N_PZ_797,'1');
     F1HzCnt_T(10) <= (F1HzEnable AND F1HzCnt(0) AND F1HzCnt(1) AND
      F1HzCnt(2) AND F1HzCnt(3) AND F1HzCnt(4) AND F1HzCnt(5) AND
      F1HzCnt(6) AND F1HzCnt(7) AND F1HzCnt(8) AND F1HzCnt(9));
FTCPE_F1HzCnt11: FTCPE port map (F1HzCnt(11),F1HzCnt_T(11),NOT Clk,'0',NOT N_PZ_797,'1');
     F1HzCnt_T(11) <= (F1HzEnable AND F1HzCnt(0) AND F1HzCnt(10) AND
      F1HzCnt(1) AND F1HzCnt(2) AND F1HzCnt(3) AND F1HzCnt(4) AND
      F1HzCnt(5) AND F1HzCnt(6) AND F1HzCnt(7) AND F1HzCnt(8) AND
      F1HzCnt(9));
FTCPE_F1HzCnt12: FTCPE port map (F1HzCnt(12),F1HzCnt_T(12),NOT Clk,'0',NOT N_PZ_797,'1');
     F1HzCnt_T(12) <= (F1HzEnable AND F1HzCnt(0) AND F1HzCnt(10) AND
      F1HzCnt(1) AND F1HzCnt(2) AND F1HzCnt(3) AND F1HzCnt(4) AND
      F1HzCnt(5) AND F1HzCnt(6) AND F1HzCnt(7) AND F1HzCnt(8) AND
      F1HzCnt(9) AND F1HzCnt(11));
FTCPE_F1HzCnt13: FTCPE port map (F1HzCnt(13),F1HzCnt_T(13),NOT Clk,'0',NOT N_PZ_797,'1');
     F1HzCnt_T(13) <= (F1HzEnable AND F1HzCnt(0) AND F1HzCnt(10) AND
      F1HzCnt(1) AND F1HzCnt(2) AND F1HzCnt(3) AND F1HzCnt(4) AND
      F1HzCnt(5) AND F1HzCnt(6) AND F1HzCnt(7) AND F1HzCnt(8) AND
      F1HzCnt(9) AND F1HzCnt(11) AND F1HzCnt(12));
FTCPE_F1HzCnt14: FTCPE port map (F1HzCnt(14),F1HzCnt_T(14),NOT Clk,'0',NOT N_PZ_797,'1');
     F1HzCnt_T(14) <= (F1HzEnable AND F1HzCnt(0) AND F1HzCnt(10) AND
      F1HzCnt(1) AND F1HzCnt(2) AND F1HzCnt(3) AND F1HzCnt(4) AND
      F1HzCnt(5) AND F1HzCnt(6) AND F1HzCnt(7) AND F1HzCnt(8) AND
      F1HzCnt(9) AND F1HzCnt(11) AND F1HzCnt(12) AND F1HzCnt(13));
FDCPE_F1HzEnable: FDCPE port map (F1HzEnable,F1HzEnable_D,NOT Clk,'0','0','1');
     F1HzEnable_D <= ((NOT Reset AND F1HzEnable)
      OR (Reset AND MachineState_FFd1 AND MachineState_FFd3)
      OR (Reset AND MachineState_FFd1 AND NOT MachineState_FFd2)
      OR (Reset AND MachineState_FFd3 AND NOT MachineState_FFd2));
FTCPE_FClk: FTCPE port map (FClk,FClk_T,NOT Clk,NOT Reset,'0','1');
     FClk_T <= (FDivInstance/FDivCnt(0) AND FDivInstance/FDivCnt(1));
FTCPE_FDiv0: FTCPE port map (FDiv(0),'0',FClk,NOT Reset,'0','1');
FTCPE_FDiv1: FTCPE port map (FDiv(1),FDiv(0),FClk,NOT Reset,'0','1');
FTCPE_FDiv2: FTCPE port map (FDiv(2),FDiv_T(2),FClk,NOT Reset,'0','1');
     FDiv_T(2) <= (FDiv(0) AND FDiv(1));
FTCPE_FDiv3: FTCPE port map (FDiv(3),FDiv_T(3),FClk,NOT Reset,'0','1');
     FDiv_T(3) <= (FDiv(0) AND FDiv(2) AND FDiv(1));
FTCPE_FDivInstance/FDivCnt0: FTCPE port map (FDivInstance/FDivCnt(0),'0',NOT Clk,NOT Reset,'0','1');
FTCPE_FDivInstance/FDivCnt1: FTCPE port map (FDivInstance/FDivCnt(1),FDivInstance/FDivCnt(0),NOT Clk,NOT Reset,'0','1');
FDCPE_GoKInstance/ShRegister0: FDCPE port map (GoKInstance/ShRegister(0),GoKey,FDiv(2),'0',NOT Reset,'1');
FDCPE_GoKInstance/ShRegister1: FDCPE port map (GoKInstance/ShRegister(1),GoKInstance/ShRegister(0),FDiv(2),'0',NOT Reset,'1');
FDCPE_GoKInstance/ShRegister2: FDCPE port map (GoKInstance/ShRegister(2),GoKInstance/ShRegister(1),FDiv(2),'0',NOT Reset,'1');
FDCPE_GoKInstance/ShRegister3: FDCPE port map (GoKInstance/ShRegister(3),GoKInstance/ShRegister(2),FDiv(2),'0',NOT Reset,'1');
LDCP_GoKeyStatus: LDCP port map (GoKeyStatus,NOT '0',,GoKeyStatus_CLR,'0');
     GoKeyStatus_G <= (NOT GoKInstance/ShRegister(0) AND
      NOT GoKInstance/ShRegister(1) AND NOT GoKInstance/ShRegister(2) AND
      NOT GoKInstance/ShRegister(3));
     GoKeyStatus_CLR <= (GoKInstance/ShRegister(0) AND
      GoKInstance/ShRegister(1) AND GoKInstance/ShRegister(2) AND
      GoKInstance/ShRegister(3));
FTCPE_HzRange: FTCPE port map (HzRange,HzRange_T,NOT Clk,'0',NOT Reset,'1');
     HzRange_T <= (NOT MachineState_FFd1 AND NOT MachineState_FFd3 AND
      MachineState_FFd2);
FTCPE_MachineState_FFd1: FTCPE port map (MachineState_FFd1,MachineState_FFd1_T,NOT Clk,NOT Reset,'0','1');
     MachineState_FFd1_T <= ((MachineState_FFd1 AND NOT MachineState_FFd3 AND
      MachineState_FFd2)
      OR (NOT MachineState_FFd1 AND MachineState_FFd3 AND
      NOT MachineState_FFd2));
FTCPE_MachineState_FFd2: FTCPE port map (MachineState_FFd2,MachineState_FFd2_T,NOT Clk,NOT Reset,'0','1');
     MachineState_FFd2_T <= ((MachineState_FFd1 AND MachineState_FFd3 AND NOT RunLed AND
      NOT MachineState_FFd2)
      OR (NOT MachineState_FFd1 AND MachineState_FFd3 AND
      MachineState_FFd2 AND NOT GoKeyStatus AND NOT RangeKeyStatus)
      OR (NOT MachineState_FFd1 AND NOT MachineState_FFd3 AND
      NOT MachineState_FFd2 AND NOT GoKeyStatus AND RangeKeyStatus));
FDCPE_MachineState_FFd3: FDCPE port map (MachineState_FFd3,MachineState_FFd3_D,NOT Clk,NOT Reset,'0','1');
     MachineState_FFd3_D <= NOT (((MachineState_FFd1 AND NOT RunLed AND NOT MachineState_FFd2)
      OR (NOT MachineState_FFd1 AND MachineState_FFd3 AND
      NOT MachineState_FFd2)
      OR (NOT MachineState_FFd1 AND NOT MachineState_FFd2 AND
      NOT GoKeyStatus)
      OR (NOT MachineState_FFd1 AND MachineState_FFd3 AND
      NOT GoKeyStatus AND NOT RangeKeyStatus)));
MuxDisplInstance/Blank <= ((MuxDisplInstance/SelCnt(0) AND
      MuxDisplInstance/SelCnt(1) AND HzRange AND NOT R1000(3) AND NOT R1000(2) AND NOT R1000(1) AND
      NOT R1000(0))
      OR (MuxDisplInstance/SelCnt(0) AND
      MuxDisplInstance/SelCnt(1) AND NOT HzRange AND NOT R100000(3) AND NOT R100000(2) AND NOT R100000(1) AND
      NOT R100000(0))
      OR (MuxDisplInstance/SelCnt(1) AND HzRange AND NOT R1000(3) AND
      NOT R100(3) AND NOT R1000(2) AND NOT R100(2) AND NOT R1000(1) AND NOT R100(1) AND
      NOT R1000(0) AND NOT R100(0))
      OR (MuxDisplInstance/SelCnt(1) AND NOT HzRange AND
      NOT R100000(3) AND NOT R10000(3) AND NOT R100000(2) AND NOT R10000(2) AND NOT R100000(1) AND
      NOT R10000(1) AND NOT R100000(0) AND NOT R10000(0))
      OR (MuxDisplInstance/SelCnt(0) AND HzRange AND NOT R1000(3) AND
      NOT R100(3) AND NOT R10(3) AND NOT R1000(2) AND NOT R100(2) AND NOT R10(2) AND
      NOT R1000(1) AND NOT R100(1) AND NOT R10(1) AND NOT R1000(0) AND NOT R100(0) AND NOT R10(0)));
FTCPE_MuxDisplInstance/SelCnt0: FTCPE port map (MuxDisplInstance/SelCnt(0),'0',FDiv(3),NOT Reset,'0','1');
FTCPE_MuxDisplInstance/SelCnt1: FTCPE port map (MuxDisplInstance/SelCnt(1),MuxDisplInstance/SelCnt(0),FDiv(3),NOT Reset,'0','1');
MuxDisplInstance/Tetr(0) <= ((MuxDisplInstance/SelCnt(0) AND
      MuxDisplInstance/SelCnt(1) AND HzRange AND NOT R1000(0))
      OR (MuxDisplInstance/SelCnt(0) AND
      MuxDisplInstance/SelCnt(1) AND NOT HzRange AND NOT R100000(0))
      OR (MuxDisplInstance/SelCnt(0) AND
      NOT MuxDisplInstance/SelCnt(1) AND HzRange AND NOT R10(0))
      OR (MuxDisplInstance/SelCnt(0) AND
      NOT MuxDisplInstance/SelCnt(1) AND NOT HzRange AND NOT R1000(0))
      OR (NOT MuxDisplInstance/SelCnt(0) AND
      MuxDisplInstance/SelCnt(1) AND HzRange AND NOT R100(0))
      OR (NOT MuxDisplInstance/SelCnt(0) AND
      MuxDisplInstance/SelCnt(1) AND NOT HzRange AND NOT R10000(0))
      OR (NOT MuxDisplInstance/SelCnt(0) AND
      NOT MuxDisplInstance/SelCnt(1) AND HzRange AND NOT R1(0))
      OR (NOT MuxDisplInstance/SelCnt(0) AND
      NOT MuxDisplInstance/SelCnt(1) AND NOT HzRange AND NOT R100(0)));
MuxDisplInstance/Tetr(1) <= ((MuxDisplInstance/SelCnt(0) AND
      MuxDisplInstance/SelCnt(1) AND HzRange AND NOT R1000(1))
      OR (MuxDisplInstance/SelCnt(0) AND
      MuxDisplInstance/SelCnt(1) AND NOT HzRange AND NOT R100000(1))
      OR (MuxDisplInstance/SelCnt(0) AND
      NOT MuxDisplInstance/SelCnt(1) AND HzRange AND NOT R10(1))
      OR (MuxDisplInstance/SelCnt(0) AND
      NOT MuxDisplInstance/SelCnt(1) AND NOT HzRange AND NOT R1000(1))
      OR (NOT MuxDisplInstance/SelCnt(0) AND
      MuxDisplInstance/SelCnt(1) AND HzRange AND NOT R100(1))
      OR (NOT MuxDisplInstance/SelCnt(0) AND
      MuxDisplInstance/SelCnt(1) AND NOT HzRange AND NOT R10000(1))
      OR (NOT MuxDisplInstance/SelCnt(0) AND
      NOT MuxDisplInstance/SelCnt(1) AND HzRange AND NOT R1(1))
      OR (NOT MuxDisplInstance/SelCnt(0) AND
      NOT MuxDisplInstance/SelCnt(1) AND NOT HzRange AND NOT R100(1)));
MuxDisplInstance/Tetr(2) <= ((MuxDisplInstance/SelCnt(0) AND
      MuxDisplInstance/SelCnt(1) AND HzRange AND NOT R1000(2))
      OR (MuxDisplInstance/SelCnt(0) AND
      MuxDisplInstance/SelCnt(1) AND NOT HzRange AND NOT R100000(2))
      OR (MuxDisplInstance/SelCnt(0) AND
      NOT MuxDisplInstance/SelCnt(1) AND HzRange AND NOT R10(2))
      OR (MuxDisplInstance/SelCnt(0) AND
      NOT MuxDisplInstance/SelCnt(1) AND NOT HzRange AND NOT R1000(2))
      OR (NOT MuxDisplInstance/SelCnt(0) AND
      MuxDisplInstance/SelCnt(1) AND HzRange AND NOT R100(2))
      OR (NOT MuxDisplInstance/SelCnt(0) AND
      MuxDisplInstance/SelCnt(1) AND NOT HzRange AND NOT R10000(2))
      OR (NOT MuxDisplInstance/SelCnt(0) AND
      NOT MuxDisplInstance/SelCnt(1) AND HzRange AND NOT R1(2))
      OR (NOT MuxDisplInstance/SelCnt(0) AND
      NOT MuxDisplInstance/SelCnt(1) AND NOT HzRange AND NOT R100(2)));
MuxDisplInstance/Tetr(3) <= ((MuxDisplInstance/SelCnt(0) AND
      MuxDisplInstance/SelCnt(1) AND HzRange AND NOT R1000(3))
      OR (MuxDisplInstance/SelCnt(0) AND
      MuxDisplInstance/SelCnt(1) AND NOT HzRange AND NOT R100000(3))
      OR (MuxDisplInstance/SelCnt(0) AND
      NOT MuxDisplInstance/SelCnt(1) AND HzRange AND NOT R10(3))
      OR (MuxDisplInstance/SelCnt(0) AND
      NOT MuxDisplInstance/SelCnt(1) AND NOT HzRange AND NOT R1000(3))
      OR (NOT MuxDisplInstance/SelCnt(0) AND
      MuxDisplInstance/SelCnt(1) AND HzRange AND NOT R100(3))
      OR (NOT MuxDisplInstance/SelCnt(0) AND
      MuxDisplInstance/SelCnt(1) AND NOT HzRange AND NOT R10000(3))
      OR (NOT MuxDisplInstance/SelCnt(0) AND
      NOT MuxDisplInstance/SelCnt(1) AND HzRange AND NOT R1(3))
      OR (NOT MuxDisplInstance/SelCnt(0) AND
      NOT MuxDisplInstance/SelCnt(1) AND NOT HzRange AND NOT R100(3)));
N_PZ_797 <= (Reset AND Clr);
FDCPE_R1000000: FDCPE port map (R100000(0),Cnt100000(0),NOT Clk,NOT Reset,'0',R100000_CE(0));
     R100000_CE(0) <= (MachineState_FFd1 AND MachineState_FFd2);
FDCPE_R1000001: FDCPE port map (R100000(1),Cnt100000(1),NOT Clk,NOT Reset,'0',R100000_CE(1));
     R100000_CE(1) <= (MachineState_FFd1 AND MachineState_FFd2);
FDCPE_R1000002: FDCPE port map (R100000(2),Cnt100000(2),NOT Clk,NOT Reset,'0',R100000_CE(2));
     R100000_CE(2) <= (MachineState_FFd1 AND MachineState_FFd2);
FDCPE_R1000003: FDCPE port map (R100000(3),Cnt100000(3),NOT Clk,NOT Reset,'0',R100000_CE(3));
     R100000_CE(3) <= (MachineState_FFd1 AND MachineState_FFd2);
FDCPE_R100000: FDCPE port map (R10000(0),Cnt10000(0),NOT Clk,NOT Reset,'0',R10000_CE(0));
     R10000_CE(0) <= (MachineState_FFd1 AND MachineState_FFd2);
FDCPE_R100001: FDCPE port map (R10000(1),Cnt10000(1),NOT Clk,NOT Reset,'0',R10000_CE(1));
     R10000_CE(1) <= (MachineState_FFd1 AND MachineState_FFd2);
FDCPE_R100002: FDCPE port map (R10000(2),Cnt10000(2),NOT Clk,NOT Reset,'0',R10000_CE(2));
     R10000_CE(2) <= (MachineState_FFd1 AND MachineState_FFd2);
FDCPE_R100003: FDCPE port map (R10000(3),Cnt10000(3),NOT Clk,NOT Reset,'0',R10000_CE(3));
     R10000_CE(3) <= (MachineState_FFd1 AND MachineState_FFd2);
FDCPE_R10000: FDCPE port map (R1000(0),Cnt1000(0),NOT Clk,NOT Reset,'0',R1000_CE(0));
     R1000_CE(0) <= (MachineState_FFd1 AND MachineState_FFd2);
FDCPE_R10001: FDCPE port map (R1000(1),Cnt1000(1),NOT Clk,NOT Reset,'0',R1000_CE(1));
     R1000_CE(1) <= (MachineState_FFd1 AND MachineState_FFd2);
FDCPE_R10002: FDCPE port map (R1000(2),Cnt1000(2),NOT Clk,NOT Reset,'0',R1000_CE(2));
     R1000_CE(2) <= (MachineState_FFd1 AND MachineState_FFd2);
FDCPE_R10003: FDCPE port map (R1000(3),Cnt1000(3),NOT Clk,NOT Reset,'0',R1000_CE(3));
     R1000_CE(3) <= (MachineState_FFd1 AND MachineState_FFd2);
FDCPE_R1000: FDCPE port map (R100(0),Cnt100(0),NOT Clk,NOT Reset,'0',R100_CE(0));
     R100_CE(0) <= (MachineState_FFd1 AND MachineState_FFd2);
FDCPE_R1001: FDCPE port map (R100(1),Cnt100(1),NOT Clk,NOT Reset,'0',R100_CE(1));
     R100_CE(1) <= (MachineState_FFd1 AND MachineState_FFd2);
FDCPE_R1002: FDCPE port map (R100(2),Cnt100(2),NOT Clk,NOT Reset,'0',R100_CE(2));
     R100_CE(2) <= (MachineState_FFd1 AND MachineState_FFd2);
FDCPE_R1003: FDCPE port map (R100(3),Cnt100(3),NOT Clk,NOT Reset,'0',R100_CE(3));
     R100_CE(3) <= (MachineState_FFd1 AND MachineState_FFd2);
FDCPE_R100: FDCPE port map (R10(0),Cnt10(0),NOT Clk,NOT Reset,'0',R10_CE(0));
     R10_CE(0) <= (MachineState_FFd1 AND MachineState_FFd2);
FDCPE_R101: FDCPE port map (R10(1),Cnt10(1),NOT Clk,NOT Reset,'0',R10_CE(1));
     R10_CE(1) <= (MachineState_FFd1 AND MachineState_FFd2);
FDCPE_R102: FDCPE port map (R10(2),Cnt10(2),NOT Clk,NOT Reset,'0',R10_CE(2));
     R10_CE(2) <= (MachineState_FFd1 AND MachineState_FFd2);
FDCPE_R103: FDCPE port map (R10(3),Cnt10(3),NOT Clk,NOT Reset,'0',R10_CE(3));
     R10_CE(3) <= (MachineState_FFd1 AND MachineState_FFd2);
FDCPE_R10: FDCPE port map (R1(0),Cnt1(0),NOT Clk,NOT Reset,'0',R1_CE(0));
     R1_CE(0) <= (MachineState_FFd1 AND MachineState_FFd2);
FDCPE_R11: FDCPE port map (R1(1),Cnt1(1),NOT Clk,NOT Reset,'0',R1_CE(1));
     R1_CE(1) <= (MachineState_FFd1 AND MachineState_FFd2);
FDCPE_R12: FDCPE port map (R1(2),Cnt1(2),NOT Clk,NOT Reset,'0',R1_CE(2));
     R1_CE(2) <= (MachineState_FFd1 AND MachineState_FFd2);
FDCPE_R13: FDCPE port map (R1(3),Cnt1(3),NOT Clk,NOT Reset,'0',R1_CE(3));
     R1_CE(3) <= (MachineState_FFd1 AND MachineState_FFd2);
FDCPE_RangeKInstance/ShRegister0: FDCPE port map (RangeKInstance/ShRegister(0),RangeKey,FDiv(2),'0',NOT Reset,'1');
FDCPE_RangeKInstance/ShRegister1: FDCPE port map (RangeKInstance/ShRegister(1),RangeKInstance/ShRegister(0),FDiv(2),'0',NOT Reset,'1');
FDCPE_RangeKInstance/ShRegister2: FDCPE port map (RangeKInstance/ShRegister(2),RangeKInstance/ShRegister(1),FDiv(2),'0',NOT Reset,'1');
FDCPE_RangeKInstance/ShRegister3: FDCPE port map (RangeKInstance/ShRegister(3),RangeKInstance/ShRegister(2),FDiv(2),'0',NOT Reset,'1');
LDCP_RangeKeyStatus: LDCP port map (RangeKeyStatus,NOT '0',,RangeKeyStatus_CLR,'0');
     RangeKeyStatus_G <= (NOT RangeKInstance/ShRegister(0) AND
      NOT RangeKInstance/ShRegister(1) AND NOT RangeKInstance/ShRegister(2) AND
      NOT RangeKInstance/ShRegister(3));
     RangeKeyStatus_CLR <= (RangeKInstance/ShRegister(0) AND
      RangeKInstance/ShRegister(1) AND RangeKInstance/ShRegister(2) AND
      RangeKInstance/ShRegister(3));
FTCPE_RunLed: FTCPE port map (RunLed,F1HzEnable,F1HzCnt(14),NOT N_PZ_797,'0','1');
Seg_A <= NOT (((MuxDisplInstance/Blank)
      OR (MuxDisplInstance/Tetr(3) AND
      MuxDisplInstance/Tetr(2) AND MuxDisplInstance/Tetr(1) AND
      NOT MuxDisplInstance/Tetr(0))
      OR (MuxDisplInstance/Tetr(3) AND
      NOT MuxDisplInstance/Tetr(2) AND MuxDisplInstance/Tetr(1) AND
      MuxDisplInstance/Tetr(0))
      OR (NOT MuxDisplInstance/Tetr(3) AND
      MuxDisplInstance/Tetr(2) AND NOT MuxDisplInstance/Tetr(1) AND
      NOT MuxDisplInstance/Tetr(0))
      OR (NOT MuxDisplInstance/Tetr(3) AND
      NOT MuxDisplInstance/Tetr(2) AND MuxDisplInstance/Tetr(1) AND
      NOT MuxDisplInstance/Tetr(0))));
Seg_B <= (NOT MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Blank)
      XOR ((MuxDisplInstance/Tetr(2) AND
      MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Blank)
      OR (MuxDisplInstance/Tetr(3) AND
      NOT MuxDisplInstance/Tetr(2) AND MuxDisplInstance/Tetr(1) AND NOT MuxDisplInstance/Blank)
      OR (NOT MuxDisplInstance/Tetr(3) AND
      NOT MuxDisplInstance/Tetr(1) AND NOT MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Blank));
Seg_C <= NOT (((MuxDisplInstance/Blank)
      OR (NOT MuxDisplInstance/Tetr(3) AND
      NOT MuxDisplInstance/Tetr(2) AND NOT MuxDisplInstance/Tetr(1))
      OR (NOT MuxDisplInstance/Tetr(3) AND
      NOT MuxDisplInstance/Tetr(2) AND MuxDisplInstance/Tetr(0))
      OR (MuxDisplInstance/Tetr(3) AND
      MuxDisplInstance/Tetr(2) AND NOT MuxDisplInstance/Tetr(1) AND
      MuxDisplInstance/Tetr(0))));
Seg_D <= NOT (((MuxDisplInstance/Blank)
      OR (NOT MuxDisplInstance/Tetr(2) AND
      NOT MuxDisplInstance/Tetr(1) AND NOT MuxDisplInstance/Tetr(0))
      OR (MuxDisplInstance/Tetr(3) AND
      MuxDisplInstance/Tetr(2) AND MuxDisplInstance/Tetr(1) AND
      NOT MuxDisplInstance/Tetr(0))
      OR (MuxDisplInstance/Tetr(3) AND
      NOT MuxDisplInstance/Tetr(2) AND MuxDisplInstance/Tetr(1) AND
      MuxDisplInstance/Tetr(0))
      OR (NOT MuxDisplInstance/Tetr(3) AND
      MuxDisplInstance/Tetr(2) AND NOT MuxDisplInstance/Tetr(1) AND
      MuxDisplInstance/Tetr(0))));
Seg_E <= ((NOT MuxDisplInstance/Tetr(3) AND
      NOT MuxDisplInstance/Tetr(2) AND NOT MuxDisplInstance/Blank)
      OR (NOT MuxDisplInstance/Tetr(3) AND
      NOT MuxDisplInstance/Tetr(1) AND NOT MuxDisplInstance/Blank)
      OR (MuxDisplInstance/Tetr(2) AND
      MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Blank)
      OR (NOT MuxDisplInstance/Tetr(1) AND
      MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Blank));
Seg_F <= (NOT MuxDisplInstance/Tetr(3) AND NOT MuxDisplInstance/Blank)
      XOR ((MuxDisplInstance/Tetr(3) AND
      NOT MuxDisplInstance/Tetr(2) AND MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Blank)
      OR (MuxDisplInstance/Tetr(3) AND
      MuxDisplInstance/Tetr(1) AND MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Blank)
      OR (NOT MuxDisplInstance/Tetr(2) AND
      MuxDisplInstance/Tetr(1) AND NOT MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Blank));
Seg_G <= NOT (((MuxDisplInstance/Blank)
      OR (MuxDisplInstance/Tetr(3) AND
      MuxDisplInstance/Tetr(2) AND MuxDisplInstance/Tetr(1))
      OR (MuxDisplInstance/Tetr(3) AND
      NOT MuxDisplInstance/Tetr(2) AND NOT MuxDisplInstance/Tetr(1) AND
      NOT MuxDisplInstance/Tetr(0))
      OR (NOT MuxDisplInstance/Tetr(3) AND
      NOT MuxDisplInstance/Tetr(2) AND MuxDisplInstance/Tetr(1) AND
      MuxDisplInstance/Tetr(0))));
Seg_K <= ((MuxDisplInstance/SelCnt(0) AND
      NOT MuxDisplInstance/SelCnt(1) AND NOT HzRange)
      OR (NOT MuxDisplInstance/SelCnt(0) AND
      NOT MuxDisplInstance/SelCnt(1) AND HzRange));
Register Legend:
      FDCPE (Q,D,C,CLR,PRE,CE);
      FDDCPE (Q,D,C,CLR,PRE,CE);
      FTCPE (Q,D,C,CLR,PRE,CE);
      FTDCPE (Q,D,C,CLR,PRE,CE);
      LDCP (Q,D,G,CLR,PRE);