cpldfit:  version J.36                              Xilinx Inc.
                                  Fitter Report
Design Name: Freq                                Date:  8-14-2009, 10:39PM
Device Used: XC2C256-6-VQ100
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
107/256 ( 42%) 225 /896  ( 25%) 159 /640  ( 25%) 89 /256 ( 35%) 18 /80  ( 22%)

** Function Block Resources **

Function Mcells   FB Inps  Pterms   IO       CTC      CTR      CTS      CTE     
Block    Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot
FB1      16/16*    26/40    22/56     0/ 5    0/1      1/1*     0/1      0/1
FB2      16/16*    36/40    56/56*    6/ 6*   1/1*     1/1*     0/1      0/1
FB3      16/16*    17/40    18/56     0/ 4    0/1      1/1*     1/1*     0/1
FB4      16/16*    18/40    40/56     2/ 6    0/1      1/1*     0/1      0/1
FB5      16/16*    19/40    37/56     0/ 2    0/1      1/1*     1/1*     0/1
FB6      16/16*    26/40    35/56     2/ 5    1/1*     1/1*     1/1*     0/1
FB7       9/16     15/40    15/56     3/ 6    1/1*     1/1*     1/1*     0/1
FB8       0/16      0/40     0/56     0/ 6    0/1      0/1      0/1      0/1
FB9       0/16      0/40     0/56     0/ 5    0/1      0/1      0/1      0/1
FB10      0/16      0/40     0/56     0/ 7    0/1      0/1      0/1      0/1
FB11      0/16      0/40     0/56     0/ 4    0/1      0/1      0/1      0/1
FB12      0/16      0/40     0/56     0/ 4    0/1      0/1      0/1      0/1
FB13      2/16      2/40     2/56     0/ 4    1/1*     0/1      1/1*     0/1
FB14      0/16      0/40     0/56     0/ 5    0/1      0/1      0/1      0/1
FB15      0/16      0/40     0/56     0/ 6    0/1      0/1      0/1      0/1
FB16      0/16      0/40     0/56     0/ 5    0/1      0/1      0/1      0/1
         -----    -------  -------   -----    ---      ---      ---      ---
Total   107/256   159/640  225/896   13/80    4/16     7/16     5/16     0/16

CTC - Control Term Clock
CTR - Control Term Reset
CTS - Control Term Set
CTE - Control Term Output Enable

* - Resource is exhausted

** Global Control Resources **

GCK         GSR         GTS         
Used/Tot    Used/Tot    Used/Tot    
2/3         0/1         0/4

Signal 'Clk' mapped onto global clock net GCK0.
Signal 'FInp' mapped onto global clock net GCK1.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :    3           3    |  I/O              :    10     70
Output        :   13          13    |  GCK/IO           :     3      3
Bidirectional :    0           0    |  GTS/IO           :     4      4
GCK           :    2           2    |  GSR/IO           :     0      1
GTS           :    0           0    |  CDR/IO           :     1      1
GSR           :    0           0    |  DGE/IO           :     0      1
                 ----        ----
        Total     18          18

End of Mapped Resource Summary
*************************  Summary of Mapped Logic  ************************

** 13 Outputs **

Signal                        Total Total Loc     Pin   Pin       Pin     I/O      I/O       Slew Reg     Reg Init
Name                          Pts   Inps          No.   Type      Use     STD      Style     Rate Use     State
Seg_K                         2     3     FB2_1   1     GTS/I/O   O       LVCMOS18           FAST         
Seg_G                         4     5     FB2_3   2     GTS/I/O   O       LVCMOS18           FAST         
Seg_F                         4     5     FB2_5   3     GTS/I/O   O       LVCMOS18           FAST         
Seg_E                         4     5     FB2_12  4     GTS/I/O   O       LVCMOS18           FAST         
Seg_D                         5     5     FB2_14  6     I/O       O       LVCMOS18           FAST         
Seg_C                         4     5     FB2_15  7     I/O       O       LVCMOS18           FAST         
Seg_A                         5     5     FB4_1   8     I/O       O       LVCMOS18           FAST         
Seg_B                         4     5     FB4_2   9     I/O       O       LVCMOS18           FAST         
DSel2                         1     2     FB6_2   24    CDR/I/O   O       LVCMOS18           FAST         
DSel3                         1     2     FB6_4   27    GCK/I/O   O       LVCMOS18           FAST         
DSel1                         1     2     FB7_5   19    I/O       O       LVCMOS18           FAST         
DSel0                         1     2     FB7_6   18    I/O       O       LVCMOS18           FAST         
RunLed                        3     3     FB7_11  17    I/O       O       LVCMOS18           FAST TFF/S   SET

** 94 Buried Nodes **

Signal                        Total Total Loc     Reg     Reg Init
Name                          Pts   Inps          Use     State
Cnt1000<2>                    2     16    FB1_1   TFF     RESET
Cnt1000<1>                    4     18    FB1_2   TFF     RESET
Cnt100<0>                     2     10    FB1_3   TFF     RESET
Cnt1000<3>                    3     18    FB1_4   TFF     RESET
Cnt10000<0>                   2     18    FB1_5   TFF     RESET
Cnt100<2>                     2     12    FB1_6   TFF     RESET
Cnt10000<2>                   2     20    FB1_7   TFF     RESET
Cnt10000<1>                   4     22    FB1_8   TFF     RESET
Cnt10000<3>                   3     22    FB1_9   TFF     RESET
Cnt100000<0>                  2     22    FB1_10  TFF     RESET
Cnt100000<2>                  2     24    FB1_11  TFF     RESET
Cnt100<1>                     4     14    FB1_12  TFF     RESET
Cnt100<3>                     3     14    FB1_13  TFF     RESET
Cnt1000<0>                    2     14    FB1_14  TFF     RESET
Cnt100000<3>                  3     26    FB1_15  TFF     RESET
Cnt100000<1>                  4     26    FB1_16  TFF     RESET
FDiv<0>                       2     2     FB2_2   TFF     RESET
MuxDisplInstance/SelCnt<0>    2     2     FB2_4   TFF     RESET
MuxDisplInstance/SelCnt<1>    3     3     FB2_6   TFF     RESET
FClk                          2     3     FB2_7   TFF     RESET
FDivInstance/FDivCnt<1>       2     2     FB2_8   TFF     RESET
FDivInstance/FDivCnt<0>       1     1     FB2_9   TFF     RESET
MuxDisplInstance/Tetr<2>      8     9     FB2_10          
MuxDisplInstance/Tetr<1>      8     9     FB2_11          
MuxDisplInstance/Blank        5     23    FB2_13          
MuxDisplInstance/Tetr<0>      8     9     FB2_16          
F1HzCnt<3>                    2     5     FB3_1   TFF     RESET
F1HzCnt<4>                    2     6     FB3_2   TFF     RESET
F1HzCnt<5>                    2     7     FB3_3   TFF     RESET
F1HzCnt<6>                    2     8     FB3_4   TFF     RESET
Cnt1<0>                       2     2     FB3_5   TFF     RESET
F1HzCnt<7>                    2     9     FB3_6   TFF     RESET
F1HzCnt<8>                    2     10    FB3_7   TFF     RESET
F1HzCnt<9>                    2     11    FB3_8   TFF     RESET
F1HzCnt<10>                   2     12    FB3_9   TFF     RESET
F1HzCnt<11>                   2     13    FB3_10  TFF     RESET
F1HzCnt<12>                   2     14    FB3_11  TFF     RESET
F1HzCnt<0>                    2     2     FB3_12  TFF     RESET
F1HzCnt<13>                   2     15    FB3_13  TFF     RESET
F1HzCnt<1>                    2     3     FB3_14  TFF     RESET

Signal                        Total Total Loc     Reg     Reg Init
Name                          Pts   Inps          Use     State
F1HzCnt<14>                   2     16    FB3_15  TFF     RESET
F1HzCnt<2>                    2     4     FB3_16  TFF     RESET
R1<2>                         3     4     FB4_3   DEFF    RESET
R10<2>                        3     4     FB4_4   DEFF    RESET
R1<1>                         3     4     FB4_5   DEFF    RESET
R1<0>                         3     4     FB4_6   DEFF    RESET
R10<1>                        3     4     FB4_7   DEFF    RESET
R10<0>                        3     4     FB4_8   DEFF    RESET
Cnt10<3>                      3     10    FB4_9   TFF     RESET
Cnt10<1>                      4     10    FB4_10  TFF     RESET
Cnt10<2>                      2     8     FB4_11  TFF     RESET
Cnt1<3>                       3     6     FB4_12  TFF     RESET
R10<3>                        3     4     FB4_13  DEFF    RESET
Cnt10<0>                      2     6     FB4_14  TFF     RESET
Cnt1<1>                       3     6     FB4_15  TFF     RESET
Cnt1<2>                       2     4     FB4_16  TFF     RESET
R10000<3>                     3     4     FB5_1   DEFF    RESET
R10000<2>                     3     4     FB5_2   DEFF    RESET
R10000<1>                     3     4     FB5_3   DEFF    RESET
R1000<1>                      3     4     FB5_4   DEFF    RESET
R10000<0>                     3     4     FB5_5   DEFF    RESET
R1000<0>                      3     4     FB5_6   DEFF    RESET
R100000<3>                    3     4     FB5_7   DEFF    RESET
R100000<2>                    3     4     FB5_8   DEFF    RESET
R100000<1>                    3     4     FB5_9   DEFF    RESET
R100000<0>                    3     4     FB5_10  DEFF    RESET
MachineState_FFd2             4     7     FB5_11  TFF     RESET
MachineState_FFd3             5     7     FB5_12  DFF     RESET
F1HzEnable                    4     5     FB5_13  DFF     RESET
Clr                           2     5     FB5_14  DFF     RESET
MachineState_FFd1             3     4     FB5_15  TFF     RESET
HzRange                       2     4     FB5_16  TFF     RESET
FDiv<2>                       3     4     FB6_1   TFF     RESET
FDiv<1>                       3     3     FB6_3   TFF     RESET
N_PZ_797                      1     2     FB6_5           
R1<3>                         3     4     FB6_6   DEFF    RESET
R100<3>                       3     4     FB6_7   DEFF    RESET
R100<2>                       3     4     FB6_8   DEFF    RESET
R100<1>                       3     4     FB6_9   DEFF    RESET
R100<0>                       3     4     FB6_10  DEFF    RESET

Signal                        Total Total Loc     Reg     Reg Init
Name                          Pts   Inps          Use     State
R1000<3>                      3     4     FB6_11  DEFF    RESET
GoKInstance/ShRegister<2>     3     3     FB6_12  DFF     RESET
R1000<2>                      3     4     FB6_13  DEFF    RESET
GoKInstance/ShRegister<1>     3     3     FB6_14  DFF     RESET
MuxDisplInstance/Tetr<3>      8     9     FB6_15          
FDiv<3>                       3     5     FB6_16  TFF     RESET
GoKeyStatus                   2     4     FB7_7   LATCH   RESET
RangeKeyStatus                2     4     FB7_8   LATCH   RESET
RangeKInstance/ShRegister<3>  3     3     FB7_9   DFF     RESET
RangeKInstance/ShRegister<2>  3     3     FB7_10  DFF     RESET
RangeKInstance/ShRegister<1>  3     3     FB7_15  DFF     RESET
GoKInstance/ShRegister<3>     3     3     FB7_16  DFF     RESET
GoKInstance/ShRegister<0>     2     2     FB13_6  DFF     RESET
RangeKInstance/ShRegister<0>  2     2     FB13_13 DFF     RESET

** 5 Inputs **

Signal                        Loc     Pin   Pin       Pin     I/O      I/O
Name                                  No.   Type      Use     STD      Style
FInp                          FB5_4   23    GCK/I/O   GCK     LVCMOS18 PU
Clk                           FB5_6   22    GCK/I/O   GCK     LVCMOS18 PU
Reset                         FB12_15 65    I/O       I       LVCMOS18 PU
GoKey                         FB13_6  55    I/O       I       LVCMOS18 PU
RangeKey                      FB13_13 56    I/O       I       LVCMOS18 PU

Legend:
Pin No.   - ~     - User Assigned
I/O Style - OD    - OpenDrain
          - PU    - Pullup
          - KPR   - Keeper
          - S     - SchmittTrigger
          - DG    - DataGate
Reg Use   - LATCH - Transparent latch
          - DFF   - D-flip-flop
          - DEFF  - D-flip-flop with clock enable
          - TFF   - T-flip-flop
          - TDFF  - Dual-edge-triggered T-flip-flop
          - DDFF  - Dual-edge-triggered flip-flop
          - DDEFF - Dual-edge-triggered flip-flop with clock enable
          /S (after any above flop/latch type) indicates initial state is Set
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
              VRF - Vref
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               26/14
Number of function block control terms used/remaining:        1/3
Number of PLA product terms used/remaining:                   22/34
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
Cnt1000<2>                    2     FB1_1        (b)     (b)        +      
Cnt1000<1>                    4     FB1_2        (b)     (b)        +      
Cnt100<0>                     2     FB1_3   99   GSR/I/O (b)        +      
Cnt1000<3>                    3     FB1_4        (b)     (b)        +      
Cnt10000<0>                   2     FB1_5        (b)     (b)        +      
Cnt100<2>                     2     FB1_6   97   I/O     (b)        +      
Cnt10000<2>                   2     FB1_7        (b)     (b)        +      
Cnt10000<1>                   4     FB1_8        (b)     (b)        +      
Cnt10000<3>                   3     FB1_9        (b)     (b)        +      
Cnt100000<0>                  2     FB1_10       (b)     (b)        +      
Cnt100000<2>                  2     FB1_11       (b)     (b)        +      
Cnt100<1>                     4     FB1_12  96   I/O     (b)        +      
Cnt100<3>                     3     FB1_13  95   I/O     (b)        +      
Cnt1000<0>                    2     FB1_14  94   I/O     (b)        +      
Cnt100000<3>                  3     FB1_15       (b)     (b)        +      
Cnt100000<1>                  4     FB1_16       (b)     (b)        +      

Signals Used by Logic in Function Block
  1: Cnt100000<0>      10: Cnt1000<1>        19: Cnt10<2> 
  2: Cnt100000<1>      11: Cnt1000<2>        20: Cnt10<3> 
  3: Cnt100000<2>      12: Cnt1000<3>        21: Cnt1<0> 
  4: Cnt100000<3>      13: Cnt100<0>         22: Cnt1<1> 
  5: Cnt10000<0>       14: Cnt100<1>         23: Cnt1<2> 
  6: Cnt10000<1>       15: Cnt100<2>         24: Cnt1<3> 
  7: Cnt10000<2>       16: Cnt100<3>         25: N_PZ_797 
  8: Cnt10000<3>       17: Cnt10<0>          26: RunLed 
  9: Cnt1000<0>        18: Cnt10<1>         

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
Cnt1000<2>        ........XX..XXXXXXXXXXXXXX.............. 16      
Cnt1000<1>        ........XXXXXXXXXXXXXXXXXX.............. 18      
Cnt100<0>         ................XXXXXXXXXX.............. 10      
Cnt1000<3>        ........XXXXXXXXXXXXXXXXXX.............. 18      
Cnt10000<0>       ........XXXXXXXXXXXXXXXXXX.............. 18      
Cnt100<2>         ............XX..XXXXXXXXXX.............. 12      
Cnt10000<2>       ....XX..XXXXXXXXXXXXXXXXXX.............. 20      
Cnt10000<1>       ....XXXXXXXXXXXXXXXXXXXXXX.............. 22      
Cnt10000<3>       ....XXXXXXXXXXXXXXXXXXXXXX.............. 22      
Cnt100000<0>      ....XXXXXXXXXXXXXXXXXXXXXX.............. 22      
Cnt100000<2>      XX..XXXXXXXXXXXXXXXXXXXXXX.............. 24      
Cnt100<1>         ............XXXXXXXXXXXXXX.............. 14      
Cnt100<3>         ............XXXXXXXXXXXXXX.............. 14      
Cnt1000<0>        ............XXXXXXXXXXXXXX.............. 14      
Cnt100000<3>      XXXXXXXXXXXXXXXXXXXXXXXXXX.............. 26      
Cnt100000<1>      XXXXXXXXXXXXXXXXXXXXXXXXXX.............. 26      
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB2  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               36/4
Number of function block control terms used/remaining:        2/2
Number of PLA product terms used/remaining:                   56/0
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
Seg_K                         2     FB2_1   1    GTS/I/O O                 
FDiv<0>                       2     FB2_2        (b)     (b)        +      
Seg_G                         4     FB2_3   2    GTS/I/O O                 
MuxDisplInstance/SelCnt<0>    2     FB2_4        (b)     (b)    +   +      
Seg_F                         4     FB2_5   3    GTS/I/O O                 
MuxDisplInstance/SelCnt<1>    3     FB2_6        (b)     (b)    +   +      
FClk                          2     FB2_7        (b)     (b)        +      
FDivInstance/FDivCnt<1>       2     FB2_8        (b)     (b)        +      
FDivInstance/FDivCnt<0>       1     FB2_9        (b)     (b)        +      
MuxDisplInstance/Tetr<2>      8     FB2_10       (b)     (b)               
MuxDisplInstance/Tetr<1>      8     FB2_11       (b)     (b)               
Seg_E                         4     FB2_12  4    GTS/I/O O                 
MuxDisplInstance/Blank        5     FB2_13       (b)     (b)               
Seg_D                         5     FB2_14  6    I/O     O                 
Seg_C                         4     FB2_15  7    I/O     O                 
MuxDisplInstance/Tetr<0>      8     FB2_16       (b)     (b)               

Signals Used by Logic in Function Block
  1: FClk                        13: R100000<0>        25: R100<0> 
  2: FDiv<3>                     14: R100000<1>        26: R100<1> 
  3: FDivInstance/FDivCnt<0>     15: R100000<2>        27: R100<2> 
  4: FDivInstance/FDivCnt<1>     16: R100000<3>        28: R100<3> 
  5: HzRange                     17: R10000<0>         29: R10<0> 
  6: MuxDisplInstance/Blank      18: R10000<1>         30: R10<1> 
  7: MuxDisplInstance/SelCnt<0>  19: R10000<2>         31: R10<2> 
  8: MuxDisplInstance/SelCnt<1>  20: R10000<3>         32: R10<3> 
  9: MuxDisplInstance/Tetr<0>    21: R1000<0>          33: R1<0> 
 10: MuxDisplInstance/Tetr<1>    22: R1000<1>          34: R1<1> 
 11: MuxDisplInstance/Tetr<2>    23: R1000<2>          35: R1<2> 
 12: MuxDisplInstance/Tetr<3>    24: R1000<3>          36: Reset 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
Seg_K             ....X.XX................................ 3       
FDiv<0>           X..................................X.... 2       
Seg_G             .....X..XXXX............................ 5       
MuxDisplInstance/SelCnt<0> 
                  .X.................................X.... 2       
Seg_F             .....X..XXXX............................ 5       
MuxDisplInstance/SelCnt<1> 
                  .X....X............................X.... 3       
FClk              ..XX...............................X.... 3       
FDivInstance/FDivCnt<1> 
                  ..X................................X.... 2       
FDivInstance/FDivCnt<0> 
                  ...................................X.... 1       
MuxDisplInstance/Tetr<2> 
                  ....X.XX......X...X...X...X...X...X..... 9       
MuxDisplInstance/Tetr<1> 
                  ....X.XX.....X...X...X...X...X...X...... 9       
Seg_E             .....X..XXXX............................ 5       
MuxDisplInstance/Blank 
                  ....X.XX....XXXXXXXXXXXXXXXXXXXX........ 23      
Seg_D             .....X..XXXX............................ 5       
Seg_C             .....X..XXXX............................ 5       
MuxDisplInstance/Tetr<0> 
                  ....X.XX....X...X...X...X...X...X....... 9       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB3  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               17/23
Number of function block control terms used/remaining:        2/2
Number of PLA product terms used/remaining:                   18/38
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
F1HzCnt<3>                    2     FB3_1        (b)     (b)            +  
F1HzCnt<4>                    2     FB3_2        (b)     (b)            +  
F1HzCnt<5>                    2     FB3_3        (b)     (b)            +  
F1HzCnt<6>                    2     FB3_4        (b)     (b)            +  
Cnt1<0>                       2     FB3_5   93   I/O     (b)        +      
F1HzCnt<7>                    2     FB3_6        (b)     (b)            +  
F1HzCnt<8>                    2     FB3_7        (b)     (b)            +  
F1HzCnt<9>                    2     FB3_8        (b)     (b)            +  
F1HzCnt<10>                   2     FB3_9        (b)     (b)            +  
F1HzCnt<11>                   2     FB3_10       (b)     (b)            +  
F1HzCnt<12>                   2     FB3_11       (b)     (b)            +  
F1HzCnt<0>                    2     FB3_12  92   I/O     (b)            +  
F1HzCnt<13>                   2     FB3_13       (b)     (b)            +  
F1HzCnt<1>                    2     FB3_14  91   I/O     (b)            +  
F1HzCnt<14>                   2     FB3_15       (b)     (b)            +  
F1HzCnt<2>                    2     FB3_16  90   I/O     (b)            +  

Signals Used by Logic in Function Block
  1: F1HzCnt<0>         7: F1HzCnt<2>        13: F1HzCnt<8> 
  2: F1HzCnt<10>        8: F1HzCnt<3>        14: F1HzCnt<9> 
  3: F1HzCnt<11>        9: F1HzCnt<4>        15: F1HzEnable 
  4: F1HzCnt<12>       10: F1HzCnt<5>        16: N_PZ_797 
  5: F1HzCnt<13>       11: F1HzCnt<6>        17: RunLed 
  6: F1HzCnt<1>        12: F1HzCnt<7>       

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
F1HzCnt<3>        X....XX.......XX........................ 5       
F1HzCnt<4>        X....XXX......XX........................ 6       
F1HzCnt<5>        X....XXXX.....XX........................ 7       
F1HzCnt<6>        X....XXXXX....XX........................ 8       
Cnt1<0>           ...............XX....................... 2       
F1HzCnt<7>        X....XXXXXX...XX........................ 9       
F1HzCnt<8>        X....XXXXXXX..XX........................ 10      
F1HzCnt<9>        X....XXXXXXXX.XX........................ 11      
F1HzCnt<10>       X....XXXXXXXXXXX........................ 12      
F1HzCnt<11>       XX...XXXXXXXXXXX........................ 13      
F1HzCnt<12>       XXX..XXXXXXXXXXX........................ 14      
F1HzCnt<0>        ..............XX........................ 2       
F1HzCnt<13>       XXXX.XXXXXXXXXXX........................ 15      
F1HzCnt<1>        X.............XX........................ 3       
F1HzCnt<14>       XXXXXXXXXXXXXXXX........................ 16      
F1HzCnt<2>        X....X........XX........................ 4       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB4  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               18/22
Number of function block control terms used/remaining:        1/3
Number of PLA product terms used/remaining:                   40/16
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
Seg_A                         5     FB4_1   8    I/O     O                 
Seg_B                         4     FB4_2   9    I/O     O                 
R1<2>                         3     FB4_3   10   I/O     (b)        +      
R10<2>                        3     FB4_4        (b)     (b)        +      
R1<1>                         3     FB4_5   11   I/O     (b)        +      
R1<0>                         3     FB4_6   12   I/O     (b)        +      
R10<1>                        3     FB4_7        (b)     (b)        +      
R10<0>                        3     FB4_8        (b)     (b)        +      
Cnt10<3>                      3     FB4_9        (b)     (b)               
Cnt10<1>                      4     FB4_10       (b)     (b)               
Cnt10<2>                      2     FB4_11       (b)     (b)               
Cnt1<3>                       3     FB4_12       (b)     (b)               
R10<3>                        3     FB4_13  13   I/O     (b)        +      
Cnt10<0>                      2     FB4_14       (b)     (b)               
Cnt1<1>                       3     FB4_15       (b)     (b)               
Cnt1<2>                       2     FB4_16       (b)     (b)               

Signals Used by Logic in Function Block
  1: Cnt10<0>           7: Cnt1<2>                   13: MuxDisplInstance/Tetr<1> 
  2: Cnt10<1>           8: Cnt1<3>                   14: MuxDisplInstance/Tetr<2> 
  3: Cnt10<2>           9: MachineState_FFd1         15: MuxDisplInstance/Tetr<3> 
  4: Cnt10<3>          10: MachineState_FFd2         16: N_PZ_797 
  5: Cnt1<0>           11: MuxDisplInstance/Blank    17: Reset 
  6: Cnt1<1>           12: MuxDisplInstance/Tetr<0>  18: RunLed 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
Seg_A             ..........XXXXX......................... 5       
Seg_B             ..........XXXXX......................... 5       
R1<2>             ......X.XX......X....................... 4       
R10<2>            ..X.....XX......X....................... 4       
R1<1>             .....X..XX......X....................... 4       
R1<0>             ....X...XX......X....................... 4       
R10<1>            .X......XX......X....................... 4       
R10<0>            X.......XX......X....................... 4       
Cnt10<3>          XXXXXXXX.......X.X...................... 10      
Cnt10<1>          XXXXXXXX.......X.X...................... 10      
Cnt10<2>          XX..XXXX.......X.X...................... 8       
Cnt1<3>           ....XXXX.......X.X...................... 6       
R10<3>            ...X....XX......X....................... 4       
Cnt10<0>          ....XXXX.......X.X...................... 6       
Cnt1<1>           ....XXXX.......X.X...................... 6       
Cnt1<2>           ....XX.........X.X...................... 4       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB5  ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               19/21
Number of function block control terms used/remaining:        2/2
Number of PLA product terms used/remaining:                   37/19
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
R10000<3>                     3     FB5_1        (b)     (b)        +      
R10000<2>                     3     FB5_2        (b)     (b)        +      
R10000<1>                     3     FB5_3        (b)     (b)        +      
R1000<1>                      3     FB5_4   23   GCK/I/O GCK        +      
R10000<0>                     3     FB5_5        (b)     (b)        +      
R1000<0>                      3     FB5_6   22   GCK/I/O GCK        +      
R100000<3>                    3     FB5_7        (b)     (b)        +      
R100000<2>                    3     FB5_8        (b)     (b)        +      
R100000<1>                    3     FB5_9        (b)     (b)        +      
R100000<0>                    3     FB5_10       (b)     (b)        +      
MachineState_FFd2             4     FB5_11       (b)     (b)        +      
MachineState_FFd3             5     FB5_12       (b)     (b)        +      
F1HzEnable                    4     FB5_13       (b)     (b)               
Clr                           2     FB5_14       (b)     (b)               
MachineState_FFd1             3     FB5_15       (b)     (b)        +      
HzRange                       2     FB5_16       (b)     (b)            +  

Signals Used by Logic in Function Block
  1: Clr                8: Cnt10000<2>       14: MachineState_FFd1 
  2: Cnt100000<0>       9: Cnt10000<3>       15: MachineState_FFd2 
  3: Cnt100000<1>      10: Cnt1000<0>        16: MachineState_FFd3 
  4: Cnt100000<2>      11: Cnt1000<1>        17: RangeKeyStatus 
  5: Cnt100000<3>      12: F1HzEnable        18: Reset 
  6: Cnt10000<0>       13: GoKeyStatus       19: RunLed 
  7: Cnt10000<1>      

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
R10000<3>         ........X....XX..X...................... 4       
R10000<2>         .......X.....XX..X...................... 4       
R10000<1>         ......X......XX..X...................... 4       
R1000<1>          ..........X..XX..X...................... 4       
R10000<0>         .....X.......XX..X...................... 4       
R1000<0>          .........X...XX..X...................... 4       
R100000<3>        ....X........XX..X...................... 4       
R100000<2>        ...X.........XX..X...................... 4       
R100000<1>        ..X..........XX..X...................... 4       
R100000<0>        .X...........XX..X...................... 4       
MachineState_FFd2 
                  ............XXXXXXX..................... 7       
MachineState_FFd3 
                  ............XXXXXXX..................... 7       
F1HzEnable        ...........X.XXX.X...................... 5       
Clr               X............XXX.X...................... 5       
MachineState_FFd1 
                  .............XXX.X...................... 4       
HzRange           .............XXX.X...................... 4       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB6  ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               26/14
Number of function block control terms used/remaining:        3/1
Number of PLA product terms used/remaining:                   35/21
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
FDiv<2>                       3     FB6_1        (b)     (b)    +   +      
DSel2                         1     FB6_2   24   CDR/I/O O                 
FDiv<1>                       3     FB6_3        (b)     (b)    +   +      
DSel3                         1     FB6_4   27   GCK/I/O O                 
N_PZ_797                      1     FB6_5        (b)     (b)               
R1<3>                         3     FB6_6        (b)     (b)        +      
R100<3>                       3     FB6_7        (b)     (b)        +      
R100<2>                       3     FB6_8        (b)     (b)        +      
R100<1>                       3     FB6_9        (b)     (b)        +      
R100<0>                       3     FB6_10       (b)     (b)        +      
R1000<3>                      3     FB6_11       (b)     (b)        +      
GoKInstance/ShRegister<2>     3     FB6_12  28   DGE/I/O (b)            +  
R1000<2>                      3     FB6_13       (b)     (b)        +      
GoKInstance/ShRegister<1>     3     FB6_14  29   I/O     (b)            +  
MuxDisplInstance/Tetr<3>      8     FB6_15       (b)     (b)               
FDiv<3>                       3     FB6_16  30   I/O     (b)    +   +      

Signals Used by Logic in Function Block
  1: Clr               10: FDiv<0>                     19: MuxDisplInstance/SelCnt<1> 
  2: Cnt1000<2>        11: FDiv<1>                     20: R100000<3> 
  3: Cnt1000<3>        12: FDiv<2>                     21: R10000<3> 
  4: Cnt100<0>         13: GoKInstance/ShRegister<0>   22: R1000<3> 
  5: Cnt100<1>         14: GoKInstance/ShRegister<1>   23: R100<3> 
  6: Cnt100<2>         15: HzRange                     24: R10<3> 
  7: Cnt100<3>         16: MachineState_FFd1           25: R1<3> 
  8: Cnt1<3>           17: MachineState_FFd2           26: Reset 
  9: FClk              18: MuxDisplInstance/SelCnt<0> 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
FDiv<2>           ........XXX..............X.............. 4       
DSel2             .................XX..................... 2       
FDiv<1>           ........XX...............X.............. 3       
DSel3             .................XX..................... 2       
N_PZ_797          X........................X.............. 2       
R1<3>             .......X.......XX........X.............. 4       
R100<3>           ......X........XX........X.............. 4       
R100<2>           .....X.........XX........X.............. 4       
R100<1>           ....X..........XX........X.............. 4       
R100<0>           ...X...........XX........X.............. 4       
R1000<3>          ..X............XX........X.............. 4       
GoKInstance/ShRegister<2> 
                  ...........X.X...........X.............. 3       
R1000<2>          .X.............XX........X.............. 4       
GoKInstance/ShRegister<1> 
                  ...........XX............X.............. 3       
MuxDisplInstance/Tetr<3> 
                  ..............X..XXXXXXXX............... 9       
FDiv<3>           ........XXXX.............X.............. 5       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB7  ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               15/25
Number of function block control terms used/remaining:        3/1
Number of PLA product terms used/remaining:                   15/41
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB7_1        (b)           
(unused)                      0     FB7_2        (b)           
(unused)                      0     FB7_3        (b)           
(unused)                      0     FB7_4        (b)           
DSel1                         1     FB7_5   19   I/O     O                 
DSel0                         1     FB7_6   18   I/O     O                 
GoKeyStatus                   2     FB7_7        (b)     (b)        +      
RangeKeyStatus                2     FB7_8        (b)     (b)               
RangeKInstance/ShRegister<3>  3     FB7_9        (b)     (b)    +       +  
RangeKInstance/ShRegister<2>  3     FB7_10       (b)     (b)    +       +  
RunLed                        3     FB7_11  17   I/O     O                 
(unused)                      0     FB7_12  16   I/O           
(unused)                      0     FB7_13  15   I/O           
(unused)                      0     FB7_14  14   I/O           
RangeKInstance/ShRegister<1>  3     FB7_15       (b)     (b)    +       +  
GoKInstance/ShRegister<3>     3     FB7_16       (b)     (b)    +       +  

Signals Used by Logic in Function Block
  1: F1HzCnt<14>                 6: GoKInstance/ShRegister<2>   11: RangeKInstance/ShRegister<0> 
  2: F1HzEnable                  7: GoKInstance/ShRegister<3>   12: RangeKInstance/ShRegister<1> 
  3: FDiv<2>                     8: MuxDisplInstance/SelCnt<0>  13: RangeKInstance/ShRegister<2> 
  4: GoKInstance/ShRegister<0>   9: MuxDisplInstance/SelCnt<1>  14: RangeKInstance/ShRegister<3> 
  5: GoKInstance/ShRegister<1>  10: N_PZ_797                    15: Reset 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
DSel1             .......XX............................... 2       
DSel0             .......XX............................... 2       
GoKeyStatus       ...XXXX................................. 4       
RangeKeyStatus    ..........XXXX.......................... 4       
RangeKInstance/ShRegister<3> 
                  ..X.........X.X......................... 3       
RangeKInstance/ShRegister<2> 
                  ..X........X..X......................... 3       
RunLed            XX.......X.............................. 3       
RangeKInstance/ShRegister<1> 
                  ..X.......X...X......................... 3       
GoKInstance/ShRegister<3> 
                  ..X..X........X......................... 3       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB8  ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB8_1        (b)           
(unused)                      0     FB8_2        (b)           
(unused)                      0     FB8_3        (b)           
(unused)                      0     FB8_4        (b)           
(unused)                      0     FB8_5        (b)           
(unused)                      0     FB8_6   32   I/O           
(unused)                      0     FB8_7        (b)           
(unused)                      0     FB8_8        (b)           
(unused)                      0     FB8_9        (b)           
(unused)                      0     FB8_10       (b)           
(unused)                      0     FB8_11  33   I/O           
(unused)                      0     FB8_12  34   I/O           
(unused)                      0     FB8_13  35   I/O           
(unused)                      0     FB8_14  36   I/O           
(unused)                      0     FB8_15  37   I/O           
(unused)                      0     FB8_16       (b)           
*********************************** FB9  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB9_1   78   I/O           
(unused)                      0     FB9_2   79   I/O           
(unused)                      0     FB9_3        (b)           
(unused)                      0     FB9_4   80   I/O           
(unused)                      0     FB9_5        (b)           
(unused)                      0     FB9_6   81   I/O           
(unused)                      0     FB9_7        (b)           
(unused)                      0     FB9_8        (b)           
(unused)                      0     FB9_9        (b)           
(unused)                      0     FB9_10       (b)           
(unused)                      0     FB9_11       (b)           
(unused)                      0     FB9_12  82   I/O           
(unused)                      0     FB9_13       (b)           
(unused)                      0     FB9_14       (b)           
(unused)                      0     FB9_15       (b)           
(unused)                      0     FB9_16       (b)           
*********************************** FB10 ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB10_1  77   I/O           
(unused)                      0     FB10_2  76   I/O           
(unused)                      0     FB10_3  74   I/O           
(unused)                      0     FB10_4  73   I/O           
(unused)                      0     FB10_5  72   I/O           
(unused)                      0     FB10_6  71   I/O           
(unused)                      0     FB10_7       (b)           
(unused)                      0     FB10_8       (b)           
(unused)                      0     FB10_9       (b)           
(unused)                      0     FB10_10      (b)           
(unused)                      0     FB10_11      (b)           
(unused)                      0     FB10_12 70   I/O           
(unused)                      0     FB10_13      (b)           
(unused)                      0     FB10_14      (b)           
(unused)                      0     FB10_15      (b)           
(unused)                      0     FB10_16      (b)           
*********************************** FB11 ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB11_1       (b)           
(unused)                      0     FB11_2       (b)           
(unused)                      0     FB11_3       (b)           
(unused)                      0     FB11_4       (b)           
(unused)                      0     FB11_5       (b)           
(unused)                      0     FB11_6       (b)           
(unused)                      0     FB11_7       (b)           
(unused)                      0     FB11_8       (b)           
(unused)                      0     FB11_9       (b)           
(unused)                      0     FB11_10      (b)           
(unused)                      0     FB11_11 85   I/O           
(unused)                      0     FB11_12 86   I/O           
(unused)                      0     FB11_13 87   I/O           
(unused)                      0     FB11_14 89   I/O           
(unused)                      0     FB11_15      (b)           
(unused)                      0     FB11_16      (b)           
*********************************** FB12 ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB12_1       (b)           
(unused)                      0     FB12_2       (b)           
(unused)                      0     FB12_3       (b)           
(unused)                      0     FB12_4       (b)           
(unused)                      0     FB12_5       (b)           
(unused)                      0     FB12_6       (b)           
(unused)                      0     FB12_7       (b)           
(unused)                      0     FB12_8       (b)           
(unused)                      0     FB12_9       (b)           
(unused)                      0     FB12_10      (b)           
(unused)                      0     FB12_11 68   I/O           
(unused)                      0     FB12_12      (b)           
(unused)                      0     FB12_13 67   I/O           
(unused)                      0     FB12_14 66   I/O           
(unused)                      0     FB12_15 65   I/O     I     
(unused)                      0     FB12_16      (b)           
*********************************** FB13 ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               2/38
Number of function block control terms used/remaining:        2/2
Number of PLA product terms used/remaining:                   2/54
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB13_1       (b)           
(unused)                      0     FB13_2  53   I/O           
(unused)                      0     FB13_3       (b)           
(unused)                      0     FB13_4  54   I/O           
(unused)                      0     FB13_5       (b)           
GoKInstance/ShRegister<0>     2     FB13_6  55   I/O     I      +       +  
(unused)                      0     FB13_7       (b)           
(unused)                      0     FB13_8       (b)           
(unused)                      0     FB13_9       (b)           
(unused)                      0     FB13_10      (b)           
(unused)                      0     FB13_11      (b)           
(unused)                      0     FB13_12      (b)           
RangeKInstance/ShRegister<0>  2     FB13_13 56   I/O     I      +       +  
(unused)                      0     FB13_14      (b)           
(unused)                      0     FB13_15      (b)           
(unused)                      0     FB13_16      (b)           

Signals Used by Logic in Function Block
  1: FDiv<2>            2: Reset            

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB14 ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB14_1  52   I/O           
(unused)                      0     FB14_2       (b)           
(unused)                      0     FB14_3  50   I/O           
(unused)                      0     FB14_4       (b)           
(unused)                      0     FB14_5  49   I/O           
(unused)                      0     FB14_6       (b)           
(unused)                      0     FB14_7       (b)           
(unused)                      0     FB14_8       (b)           
(unused)                      0     FB14_9       (b)           
(unused)                      0     FB14_10      (b)           
(unused)                      0     FB14_11      (b)           
(unused)                      0     FB14_12      (b)           
(unused)                      0     FB14_13      (b)           
(unused)                      0     FB14_14 46   I/O           
(unused)                      0     FB14_15 44   I/O           
(unused)                      0     FB14_16      (b)           
*********************************** FB15 ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB15_1       (b)           
(unused)                      0     FB15_2       (b)           
(unused)                      0     FB15_3       (b)           
(unused)                      0     FB15_4       (b)           
(unused)                      0     FB15_5       (b)           
(unused)                      0     FB15_6       (b)           
(unused)                      0     FB15_7       (b)           
(unused)                      0     FB15_8       (b)           
(unused)                      0     FB15_9       (b)           
(unused)                      0     FB15_10      (b)           
(unused)                      0     FB15_11 58   I/O           
(unused)                      0     FB15_12 59   I/O           
(unused)                      0     FB15_13 60   I/O           
(unused)                      0     FB15_14 61   I/O           
(unused)                      0     FB15_15 63   I/O           
(unused)                      0     FB15_16 64   I/O           
*********************************** FB16 ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB16_1       (b)           
(unused)                      0     FB16_2       (b)           
(unused)                      0     FB16_3       (b)           
(unused)                      0     FB16_4       (b)           
(unused)                      0     FB16_5  43   I/O           
(unused)                      0     FB16_6  42   I/O           
(unused)                      0     FB16_7       (b)           
(unused)                      0     FB16_8       (b)           
(unused)                      0     FB16_9       (b)           
(unused)                      0     FB16_10      (b)           
(unused)                      0     FB16_11 41   I/O           
(unused)                      0     FB16_12 40   I/O           
(unused)                      0     FB16_13 39   I/O           
(unused)                      0     FB16_14      (b)           
(unused)                      0     FB16_15      (b)           
(unused)                      0     FB16_16      (b)           
*******************************  Equations  ********************************

********** Mapped Logic **********

FDCPE_Clr: FDCPE port map (Clr,Clr_D,NOT Clk,'0','0','1');
Clr_D <= NOT (((NOT Reset AND NOT Clr)
	OR (Reset AND NOT MachineState_FFd1 AND MachineState_FFd3 AND 
	NOT MachineState_FFd2)));

FTCPE_Cnt1000000: FTCPE port map (Cnt100000(0),Cnt100000_T(0),FInp,NOT N_PZ_797,'0','1');
Cnt100000_T(0) <= (RunLed AND Cnt1000(3) AND Cnt1000(0) AND Cnt100(0) AND 
	Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND 
	NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(1) AND NOT Cnt100(2) AND 
	Cnt100(3) AND NOT Cnt1000(1) AND NOT Cnt1000(2) AND Cnt10000(0) AND 
	NOT Cnt10000(1) AND NOT Cnt10000(2) AND Cnt10000(3));

FTCPE_Cnt1000001: FTCPE port map (Cnt100000(1),Cnt100000_T(1),FInp,NOT N_PZ_797,'0','1');
Cnt100000_T(1) <= ((RunLed AND Cnt1000(3) AND Cnt1000(0) AND Cnt100(0) AND 
	Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND 
	NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(1) AND NOT Cnt100(2) AND 
	Cnt100(3) AND NOT Cnt1000(1) AND NOT Cnt1000(2) AND NOT Cnt100000(3) AND 
	Cnt10000(0) AND Cnt100000(0) AND NOT Cnt10000(1) AND NOT Cnt10000(2) AND 
	Cnt10000(3))
	OR (RunLed AND Cnt1000(3) AND Cnt1000(0) AND Cnt100(0) AND 
	Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND 
	NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(1) AND NOT Cnt100(2) AND 
	Cnt100(3) AND NOT Cnt1000(1) AND NOT Cnt1000(2) AND Cnt10000(0) AND 
	Cnt100000(0) AND NOT Cnt10000(1) AND NOT Cnt10000(2) AND Cnt10000(3) AND 
	Cnt100000(1))
	OR (RunLed AND Cnt1000(3) AND Cnt1000(0) AND Cnt100(0) AND 
	Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND 
	NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(1) AND NOT Cnt100(2) AND 
	Cnt100(3) AND NOT Cnt1000(1) AND NOT Cnt1000(2) AND Cnt10000(0) AND 
	Cnt100000(0) AND NOT Cnt10000(1) AND NOT Cnt10000(2) AND Cnt10000(3) AND 
	Cnt100000(2)));

FTCPE_Cnt1000002: FTCPE port map (Cnt100000(2),Cnt100000_T(2),FInp,NOT N_PZ_797,'0','1');
Cnt100000_T(2) <= (RunLed AND Cnt1000(3) AND Cnt1000(0) AND Cnt100(0) AND 
	Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND 
	NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(1) AND NOT Cnt100(2) AND 
	Cnt100(3) AND NOT Cnt1000(1) AND NOT Cnt1000(2) AND Cnt10000(0) AND 
	Cnt100000(0) AND NOT Cnt10000(1) AND NOT Cnt10000(2) AND Cnt10000(3) AND 
	Cnt100000(1));

FTCPE_Cnt1000003: FTCPE port map (Cnt100000(3),Cnt100000_T(3),FInp,NOT N_PZ_797,'0','1');
Cnt100000_T(3) <= ((RunLed AND Cnt1000(3) AND Cnt1000(0) AND Cnt100(0) AND 
	Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND 
	NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(1) AND NOT Cnt100(2) AND 
	Cnt100(3) AND NOT Cnt1000(1) AND NOT Cnt1000(2) AND Cnt10000(0) AND 
	Cnt100000(0) AND NOT Cnt10000(1) AND NOT Cnt10000(2) AND Cnt10000(3) AND 
	Cnt100000(1) AND Cnt100000(2))
	OR (RunLed AND Cnt1000(3) AND Cnt1000(0) AND Cnt100(0) AND 
	Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND 
	NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(1) AND NOT Cnt100(2) AND 
	Cnt100(3) AND NOT Cnt1000(1) AND NOT Cnt1000(2) AND Cnt100000(3) AND 
	Cnt10000(0) AND Cnt100000(0) AND NOT Cnt10000(1) AND NOT Cnt10000(2) AND 
	Cnt10000(3) AND NOT Cnt100000(1) AND NOT Cnt100000(2)));

FTCPE_Cnt100000: FTCPE port map (Cnt10000(0),Cnt10000_T(0),FInp,NOT N_PZ_797,'0','1');
Cnt10000_T(0) <= (RunLed AND Cnt1000(3) AND Cnt1000(0) AND Cnt100(0) AND 
	Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND 
	NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(1) AND NOT Cnt100(2) AND 
	Cnt100(3) AND NOT Cnt1000(1) AND NOT Cnt1000(2));

FTCPE_Cnt100001: FTCPE port map (Cnt10000(1),Cnt10000_T(1),FInp,NOT N_PZ_797,'0','1');
Cnt10000_T(1) <= ((RunLed AND Cnt1000(3) AND Cnt1000(0) AND Cnt100(0) AND 
	Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND 
	NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(1) AND NOT Cnt100(2) AND 
	Cnt100(3) AND NOT Cnt1000(1) AND NOT Cnt1000(2) AND Cnt10000(0) AND 
	Cnt10000(1))
	OR (RunLed AND Cnt1000(3) AND Cnt1000(0) AND Cnt100(0) AND 
	Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND 
	NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(1) AND NOT Cnt100(2) AND 
	Cnt100(3) AND NOT Cnt1000(1) AND NOT Cnt1000(2) AND Cnt10000(0) AND 
	Cnt10000(2))
	OR (RunLed AND Cnt1000(3) AND Cnt1000(0) AND Cnt100(0) AND 
	Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND 
	NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(1) AND NOT Cnt100(2) AND 
	Cnt100(3) AND NOT Cnt1000(1) AND NOT Cnt1000(2) AND Cnt10000(0) AND 
	NOT Cnt10000(3)));

FTCPE_Cnt100002: FTCPE port map (Cnt10000(2),Cnt10000_T(2),FInp,NOT N_PZ_797,'0','1');
Cnt10000_T(2) <= (RunLed AND Cnt1000(3) AND Cnt1000(0) AND Cnt100(0) AND 
	Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND 
	NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(1) AND NOT Cnt100(2) AND 
	Cnt100(3) AND NOT Cnt1000(1) AND NOT Cnt1000(2) AND Cnt10000(0) AND 
	Cnt10000(1));

FTCPE_Cnt100003: FTCPE port map (Cnt10000(3),Cnt10000_T(3),FInp,NOT N_PZ_797,'0','1');
Cnt10000_T(3) <= ((RunLed AND Cnt1000(3) AND Cnt1000(0) AND Cnt100(0) AND 
	Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND 
	NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(1) AND NOT Cnt100(2) AND 
	Cnt100(3) AND NOT Cnt1000(1) AND NOT Cnt1000(2) AND Cnt10000(0) AND 
	Cnt10000(1) AND Cnt10000(2))
	OR (RunLed AND Cnt1000(3) AND Cnt1000(0) AND Cnt100(0) AND 
	Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND 
	NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(1) AND NOT Cnt100(2) AND 
	Cnt100(3) AND NOT Cnt1000(1) AND NOT Cnt1000(2) AND Cnt10000(0) AND 
	NOT Cnt10000(1) AND NOT Cnt10000(2) AND Cnt10000(3)));

FTCPE_Cnt10000: FTCPE port map (Cnt1000(0),Cnt1000_T(0),FInp,NOT N_PZ_797,'0','1');
Cnt1000_T(0) <= (RunLed AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND 
	NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND 
	Cnt10(3) AND NOT Cnt100(1) AND NOT Cnt100(2) AND Cnt100(3));

FTCPE_Cnt10001: FTCPE port map (Cnt1000(1),Cnt1000_T(1),FInp,NOT N_PZ_797,'0','1');
Cnt1000_T(1) <= ((RunLed AND NOT Cnt1000(3) AND Cnt1000(0) AND Cnt100(0) AND 
	Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND 
	NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(1) AND NOT Cnt100(2) AND 
	Cnt100(3))
	OR (RunLed AND Cnt1000(0) AND Cnt100(0) AND Cnt10(0) AND 
	Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND 
	NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(1) AND NOT Cnt100(2) AND Cnt100(3) AND 
	Cnt1000(1))
	OR (RunLed AND Cnt1000(0) AND Cnt100(0) AND Cnt10(0) AND 
	Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND 
	NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(1) AND NOT Cnt100(2) AND Cnt100(3) AND 
	Cnt1000(2)));

FTCPE_Cnt10002: FTCPE port map (Cnt1000(2),Cnt1000_T(2),FInp,NOT N_PZ_797,'0','1');
Cnt1000_T(2) <= (RunLed AND Cnt1000(0) AND Cnt100(0) AND Cnt10(0) AND 
	Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND 
	NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(1) AND NOT Cnt100(2) AND Cnt100(3) AND 
	Cnt1000(1));

FTCPE_Cnt10003: FTCPE port map (Cnt1000(3),Cnt1000_T(3),FInp,NOT N_PZ_797,'0','1');
Cnt1000_T(3) <= ((RunLed AND Cnt1000(0) AND Cnt100(0) AND Cnt10(0) AND 
	Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND 
	NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(1) AND NOT Cnt100(2) AND Cnt100(3) AND 
	Cnt1000(1) AND Cnt1000(2))
	OR (RunLed AND Cnt1000(3) AND Cnt1000(0) AND Cnt100(0) AND 
	Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND 
	NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(1) AND NOT Cnt100(2) AND 
	Cnt100(3) AND NOT Cnt1000(1) AND NOT Cnt1000(2)));

FTCPE_Cnt1000: FTCPE port map (Cnt100(0),Cnt100_T(0),FInp,NOT N_PZ_797,'0','1');
Cnt100_T(0) <= (RunLed AND Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND 
	NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3));

FTCPE_Cnt1001: FTCPE port map (Cnt100(1),Cnt100_T(1),FInp,NOT N_PZ_797,'0','1');
Cnt100_T(1) <= ((RunLed AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND 
	NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND 
	Cnt10(3) AND Cnt100(1))
	OR (RunLed AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND 
	NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND 
	Cnt10(3) AND Cnt100(2))
	OR (RunLed AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND 
	NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND 
	Cnt10(3) AND NOT Cnt100(3)));

FTCPE_Cnt1002: FTCPE port map (Cnt100(2),Cnt100_T(2),FInp,NOT N_PZ_797,'0','1');
Cnt100_T(2) <= (RunLed AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND 
	NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND 
	Cnt10(3) AND Cnt100(1));

FTCPE_Cnt1003: FTCPE port map (Cnt100(3),Cnt100_T(3),FInp,NOT N_PZ_797,'0','1');
Cnt100_T(3) <= ((RunLed AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND 
	NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND 
	Cnt10(3) AND Cnt100(1) AND Cnt100(2))
	OR (RunLed AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND 
	NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND 
	Cnt10(3) AND NOT Cnt100(1) AND NOT Cnt100(2) AND Cnt100(3)));

FTCPE_Cnt100: FTCPE port map (Cnt10(0),Cnt10_T(0),FInp,NOT N_PZ_797,'0','1');
Cnt10_T(0) <= (RunLed AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3));

FTCPE_Cnt101: FTCPE port map (Cnt10(1),Cnt10_T(1),FInp,NOT N_PZ_797,'0','1');
Cnt10_T(1) <= ((RunLed AND Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND 
	NOT Cnt1(2) AND Cnt1(3) AND Cnt10(1))
	OR (RunLed AND Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND 
	NOT Cnt1(2) AND Cnt1(3) AND Cnt10(2))
	OR (RunLed AND Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND 
	NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(3)));

FTCPE_Cnt102: FTCPE port map (Cnt10(2),Cnt10_T(2),FInp,NOT N_PZ_797,'0','1');
Cnt10_T(2) <= (RunLed AND Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND 
	NOT Cnt1(2) AND Cnt1(3) AND Cnt10(1));

FTCPE_Cnt103: FTCPE port map (Cnt10(3),Cnt10_T(3),FInp,NOT N_PZ_797,'0','1');
Cnt10_T(3) <= ((RunLed AND Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND 
	NOT Cnt1(2) AND Cnt1(3) AND Cnt10(1) AND Cnt10(2))
	OR (RunLed AND Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND 
	NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3)));

FTCPE_Cnt10: FTCPE port map (Cnt1(0),RunLed,FInp,NOT N_PZ_797,'0','1');

FTCPE_Cnt11: FTCPE port map (Cnt1(1),Cnt1_T(1),FInp,NOT N_PZ_797,'0','1');
Cnt1_T(1) <= (RunLed AND Cnt1(0))
	XOR (RunLed AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3));

FTCPE_Cnt12: FTCPE port map (Cnt1(2),Cnt1_T(2),FInp,NOT N_PZ_797,'0','1');
Cnt1_T(2) <= (RunLed AND Cnt1(0) AND Cnt1(1));

FTCPE_Cnt13: FTCPE port map (Cnt1(3),Cnt1_T(3),FInp,NOT N_PZ_797,'0','1');
Cnt1_T(3) <= ((RunLed AND Cnt1(0) AND Cnt1(1) AND Cnt1(2))
	OR (RunLed AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3)));


DSel0 <= (NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1));


DSel1 <= (MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1));


DSel2 <= (NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1));


DSel3 <= (MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1));

FTCPE_F1HzCnt0: FTCPE port map (F1HzCnt(0),F1HzEnable,NOT Clk,'0',NOT N_PZ_797,'1');

FTCPE_F1HzCnt1: FTCPE port map (F1HzCnt(1),F1HzCnt_T(1),NOT Clk,'0',NOT N_PZ_797,'1');
F1HzCnt_T(1) <= (F1HzEnable AND F1HzCnt(0));

FTCPE_F1HzCnt2: FTCPE port map (F1HzCnt(2),F1HzCnt_T(2),NOT Clk,'0',NOT N_PZ_797,'1');
F1HzCnt_T(2) <= (F1HzEnable AND F1HzCnt(0) AND F1HzCnt(1));

FTCPE_F1HzCnt3: FTCPE port map (F1HzCnt(3),F1HzCnt_T(3),NOT Clk,'0',NOT N_PZ_797,'1');
F1HzCnt_T(3) <= (F1HzEnable AND F1HzCnt(0) AND F1HzCnt(1) AND 
	F1HzCnt(2));

FTCPE_F1HzCnt4: FTCPE port map (F1HzCnt(4),F1HzCnt_T(4),NOT Clk,'0',NOT N_PZ_797,'1');
F1HzCnt_T(4) <= (F1HzEnable AND F1HzCnt(0) AND F1HzCnt(1) AND 
	F1HzCnt(2) AND F1HzCnt(3));

FTCPE_F1HzCnt5: FTCPE port map (F1HzCnt(5),F1HzCnt_T(5),NOT Clk,'0',NOT N_PZ_797,'1');
F1HzCnt_T(5) <= (F1HzEnable AND F1HzCnt(0) AND F1HzCnt(1) AND 
	F1HzCnt(2) AND F1HzCnt(3) AND F1HzCnt(4));

FTCPE_F1HzCnt6: FTCPE port map (F1HzCnt(6),F1HzCnt_T(6),NOT Clk,'0',NOT N_PZ_797,'1');
F1HzCnt_T(6) <= (F1HzEnable AND F1HzCnt(0) AND F1HzCnt(1) AND 
	F1HzCnt(2) AND F1HzCnt(3) AND F1HzCnt(4) AND F1HzCnt(5));

FTCPE_F1HzCnt7: FTCPE port map (F1HzCnt(7),F1HzCnt_T(7),NOT Clk,'0',NOT N_PZ_797,'1');
F1HzCnt_T(7) <= (F1HzEnable AND F1HzCnt(0) AND F1HzCnt(1) AND 
	F1HzCnt(2) AND F1HzCnt(3) AND F1HzCnt(4) AND F1HzCnt(5) AND 
	F1HzCnt(6));

FTCPE_F1HzCnt8: FTCPE port map (F1HzCnt(8),F1HzCnt_T(8),NOT Clk,'0',NOT N_PZ_797,'1');
F1HzCnt_T(8) <= (F1HzEnable AND F1HzCnt(0) AND F1HzCnt(1) AND 
	F1HzCnt(2) AND F1HzCnt(3) AND F1HzCnt(4) AND F1HzCnt(5) AND 
	F1HzCnt(6) AND F1HzCnt(7));

FTCPE_F1HzCnt9: FTCPE port map (F1HzCnt(9),F1HzCnt_T(9),NOT Clk,'0',NOT N_PZ_797,'1');
F1HzCnt_T(9) <= (F1HzEnable AND F1HzCnt(0) AND F1HzCnt(1) AND 
	F1HzCnt(2) AND F1HzCnt(3) AND F1HzCnt(4) AND F1HzCnt(5) AND 
	F1HzCnt(6) AND F1HzCnt(7) AND F1HzCnt(8));

FTCPE_F1HzCnt10: FTCPE port map (F1HzCnt(10),F1HzCnt_T(10),NOT Clk,'0',NOT N_PZ_797,'1');
F1HzCnt_T(10) <= (F1HzEnable AND F1HzCnt(0) AND F1HzCnt(1) AND 
	F1HzCnt(2) AND F1HzCnt(3) AND F1HzCnt(4) AND F1HzCnt(5) AND 
	F1HzCnt(6) AND F1HzCnt(7) AND F1HzCnt(8) AND F1HzCnt(9));

FTCPE_F1HzCnt11: FTCPE port map (F1HzCnt(11),F1HzCnt_T(11),NOT Clk,'0',NOT N_PZ_797,'1');
F1HzCnt_T(11) <= (F1HzEnable AND F1HzCnt(0) AND F1HzCnt(10) AND 
	F1HzCnt(1) AND F1HzCnt(2) AND F1HzCnt(3) AND F1HzCnt(4) AND 
	F1HzCnt(5) AND F1HzCnt(6) AND F1HzCnt(7) AND F1HzCnt(8) AND 
	F1HzCnt(9));

FTCPE_F1HzCnt12: FTCPE port map (F1HzCnt(12),F1HzCnt_T(12),NOT Clk,'0',NOT N_PZ_797,'1');
F1HzCnt_T(12) <= (F1HzEnable AND F1HzCnt(0) AND F1HzCnt(10) AND 
	F1HzCnt(1) AND F1HzCnt(2) AND F1HzCnt(3) AND F1HzCnt(4) AND 
	F1HzCnt(5) AND F1HzCnt(6) AND F1HzCnt(7) AND F1HzCnt(8) AND 
	F1HzCnt(9) AND F1HzCnt(11));

FTCPE_F1HzCnt13: FTCPE port map (F1HzCnt(13),F1HzCnt_T(13),NOT Clk,'0',NOT N_PZ_797,'1');
F1HzCnt_T(13) <= (F1HzEnable AND F1HzCnt(0) AND F1HzCnt(10) AND 
	F1HzCnt(1) AND F1HzCnt(2) AND F1HzCnt(3) AND F1HzCnt(4) AND 
	F1HzCnt(5) AND F1HzCnt(6) AND F1HzCnt(7) AND F1HzCnt(8) AND 
	F1HzCnt(9) AND F1HzCnt(11) AND F1HzCnt(12));

FTCPE_F1HzCnt14: FTCPE port map (F1HzCnt(14),F1HzCnt_T(14),NOT Clk,'0',NOT N_PZ_797,'1');
F1HzCnt_T(14) <= (F1HzEnable AND F1HzCnt(0) AND F1HzCnt(10) AND 
	F1HzCnt(1) AND F1HzCnt(2) AND F1HzCnt(3) AND F1HzCnt(4) AND 
	F1HzCnt(5) AND F1HzCnt(6) AND F1HzCnt(7) AND F1HzCnt(8) AND 
	F1HzCnt(9) AND F1HzCnt(11) AND F1HzCnt(12) AND F1HzCnt(13));

FDCPE_F1HzEnable: FDCPE port map (F1HzEnable,F1HzEnable_D,NOT Clk,'0','0','1');
F1HzEnable_D <= ((NOT Reset AND F1HzEnable)
	OR (Reset AND MachineState_FFd1 AND MachineState_FFd3)
	OR (Reset AND MachineState_FFd1 AND NOT MachineState_FFd2)
	OR (Reset AND MachineState_FFd3 AND NOT MachineState_FFd2));

FTCPE_FClk: FTCPE port map (FClk,FClk_T,NOT Clk,NOT Reset,'0','1');
FClk_T <= (FDivInstance/FDivCnt(0) AND FDivInstance/FDivCnt(1));

FTCPE_FDiv0: FTCPE port map (FDiv(0),'0',FClk,NOT Reset,'0','1');

FTCPE_FDiv1: FTCPE port map (FDiv(1),FDiv(0),FClk,NOT Reset,'0','1');

FTCPE_FDiv2: FTCPE port map (FDiv(2),FDiv_T(2),FClk,NOT Reset,'0','1');
FDiv_T(2) <= (FDiv(0) AND FDiv(1));

FTCPE_FDiv3: FTCPE port map (FDiv(3),FDiv_T(3),FClk,NOT Reset,'0','1');
FDiv_T(3) <= (FDiv(0) AND FDiv(2) AND FDiv(1));

FTCPE_FDivInstance/FDivCnt0: FTCPE port map (FDivInstance/FDivCnt(0),'0',NOT Clk,NOT Reset,'0','1');

FTCPE_FDivInstance/FDivCnt1: FTCPE port map (FDivInstance/FDivCnt(1),FDivInstance/FDivCnt(0),NOT Clk,NOT Reset,'0','1');

FDCPE_GoKInstance/ShRegister0: FDCPE port map (GoKInstance/ShRegister(0),GoKey,FDiv(2),'0',NOT Reset,'1');

FDCPE_GoKInstance/ShRegister1: FDCPE port map (GoKInstance/ShRegister(1),GoKInstance/ShRegister(0),FDiv(2),'0',NOT Reset,'1');

FDCPE_GoKInstance/ShRegister2: FDCPE port map (GoKInstance/ShRegister(2),GoKInstance/ShRegister(1),FDiv(2),'0',NOT Reset,'1');

FDCPE_GoKInstance/ShRegister3: FDCPE port map (GoKInstance/ShRegister(3),GoKInstance/ShRegister(2),FDiv(2),'0',NOT Reset,'1');

LDCP_GoKeyStatus: LDCP port map (GoKeyStatus,NOT '0',,GoKeyStatus_CLR,'0');
GoKeyStatus_G <= (NOT GoKInstance/ShRegister(0) AND 
	NOT GoKInstance/ShRegister(1) AND NOT GoKInstance/ShRegister(2) AND 
	NOT GoKInstance/ShRegister(3));
GoKeyStatus_CLR <= (GoKInstance/ShRegister(0) AND 
	GoKInstance/ShRegister(1) AND GoKInstance/ShRegister(2) AND 
	GoKInstance/ShRegister(3));

FTCPE_HzRange: FTCPE port map (HzRange,HzRange_T,NOT Clk,'0',NOT Reset,'1');
HzRange_T <= (NOT MachineState_FFd1 AND NOT MachineState_FFd3 AND 
	MachineState_FFd2);

FTCPE_MachineState_FFd1: FTCPE port map (MachineState_FFd1,MachineState_FFd1_T,NOT Clk,NOT Reset,'0','1');
MachineState_FFd1_T <= ((MachineState_FFd1 AND NOT MachineState_FFd3 AND 
	MachineState_FFd2)
	OR (NOT MachineState_FFd1 AND MachineState_FFd3 AND 
	NOT MachineState_FFd2));

FTCPE_MachineState_FFd2: FTCPE port map (MachineState_FFd2,MachineState_FFd2_T,NOT Clk,NOT Reset,'0','1');
MachineState_FFd2_T <= ((MachineState_FFd1 AND MachineState_FFd3 AND NOT RunLed AND 
	NOT MachineState_FFd2)
	OR (NOT MachineState_FFd1 AND MachineState_FFd3 AND 
	MachineState_FFd2 AND NOT GoKeyStatus AND NOT RangeKeyStatus)
	OR (NOT MachineState_FFd1 AND NOT MachineState_FFd3 AND 
	NOT MachineState_FFd2 AND NOT GoKeyStatus AND RangeKeyStatus));

FDCPE_MachineState_FFd3: FDCPE port map (MachineState_FFd3,MachineState_FFd3_D,NOT Clk,NOT Reset,'0','1');
MachineState_FFd3_D <= NOT (((MachineState_FFd1 AND NOT RunLed AND NOT MachineState_FFd2)
	OR (NOT MachineState_FFd1 AND MachineState_FFd3 AND 
	NOT MachineState_FFd2)
	OR (NOT MachineState_FFd1 AND NOT MachineState_FFd2 AND 
	NOT GoKeyStatus)
	OR (NOT MachineState_FFd1 AND MachineState_FFd3 AND 
	NOT GoKeyStatus AND NOT RangeKeyStatus)));


MuxDisplInstance/Blank <= ((MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND HzRange AND NOT R1000(3) AND NOT R1000(2) AND NOT R1000(1) AND 
	NOT R1000(0))
	OR (MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND NOT HzRange AND NOT R100000(3) AND NOT R100000(2) AND NOT R100000(1) AND 
	NOT R100000(0))
	OR (MuxDisplInstance/SelCnt(1) AND HzRange AND NOT R1000(3) AND 
	NOT R100(3) AND NOT R1000(2) AND NOT R100(2) AND NOT R1000(1) AND NOT R100(1) AND 
	NOT R1000(0) AND NOT R100(0))
	OR (MuxDisplInstance/SelCnt(1) AND NOT HzRange AND 
	NOT R100000(3) AND NOT R10000(3) AND NOT R100000(2) AND NOT R10000(2) AND NOT R100000(1) AND 
	NOT R10000(1) AND NOT R100000(0) AND NOT R10000(0))
	OR (MuxDisplInstance/SelCnt(0) AND HzRange AND NOT R1000(3) AND 
	NOT R100(3) AND NOT R10(3) AND NOT R1000(2) AND NOT R100(2) AND NOT R10(2) AND 
	NOT R1000(1) AND NOT R100(1) AND NOT R10(1) AND NOT R1000(0) AND NOT R100(0) AND NOT R10(0)));

FTCPE_MuxDisplInstance/SelCnt0: FTCPE port map (MuxDisplInstance/SelCnt(0),'0',FDiv(3),NOT Reset,'0','1');

FTCPE_MuxDisplInstance/SelCnt1: FTCPE port map (MuxDisplInstance/SelCnt(1),MuxDisplInstance/SelCnt(0),FDiv(3),NOT Reset,'0','1');


MuxDisplInstance/Tetr(0) <= ((MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND HzRange AND NOT R1000(0))
	OR (MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND NOT HzRange AND NOT R100000(0))
	OR (MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND HzRange AND NOT R10(0))
	OR (MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND NOT HzRange AND NOT R1000(0))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND HzRange AND NOT R100(0))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND NOT HzRange AND NOT R10000(0))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND HzRange AND NOT R1(0))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND NOT HzRange AND NOT R100(0)));


MuxDisplInstance/Tetr(1) <= ((MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND HzRange AND NOT R1000(1))
	OR (MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND NOT HzRange AND NOT R100000(1))
	OR (MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND HzRange AND NOT R10(1))
	OR (MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND NOT HzRange AND NOT R1000(1))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND HzRange AND NOT R100(1))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND NOT HzRange AND NOT R10000(1))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND HzRange AND NOT R1(1))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND NOT HzRange AND NOT R100(1)));


MuxDisplInstance/Tetr(2) <= ((MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND HzRange AND NOT R1000(2))
	OR (MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND NOT HzRange AND NOT R100000(2))
	OR (MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND HzRange AND NOT R10(2))
	OR (MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND NOT HzRange AND NOT R1000(2))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND HzRange AND NOT R100(2))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND NOT HzRange AND NOT R10000(2))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND HzRange AND NOT R1(2))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND NOT HzRange AND NOT R100(2)));


MuxDisplInstance/Tetr(3) <= ((MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND HzRange AND NOT R1000(3))
	OR (MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND NOT HzRange AND NOT R100000(3))
	OR (MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND HzRange AND NOT R10(3))
	OR (MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND NOT HzRange AND NOT R1000(3))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND HzRange AND NOT R100(3))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND NOT HzRange AND NOT R10000(3))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND HzRange AND NOT R1(3))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND NOT HzRange AND NOT R100(3)));


N_PZ_797 <= (Reset AND Clr);

FDCPE_R1000000: FDCPE port map (R100000(0),Cnt100000(0),NOT Clk,NOT Reset,'0',R100000_CE(0));
R100000_CE(0) <= (MachineState_FFd1 AND MachineState_FFd2);

FDCPE_R1000001: FDCPE port map (R100000(1),Cnt100000(1),NOT Clk,NOT Reset,'0',R100000_CE(1));
R100000_CE(1) <= (MachineState_FFd1 AND MachineState_FFd2);

FDCPE_R1000002: FDCPE port map (R100000(2),Cnt100000(2),NOT Clk,NOT Reset,'0',R100000_CE(2));
R100000_CE(2) <= (MachineState_FFd1 AND MachineState_FFd2);

FDCPE_R1000003: FDCPE port map (R100000(3),Cnt100000(3),NOT Clk,NOT Reset,'0',R100000_CE(3));
R100000_CE(3) <= (MachineState_FFd1 AND MachineState_FFd2);

FDCPE_R100000: FDCPE port map (R10000(0),Cnt10000(0),NOT Clk,NOT Reset,'0',R10000_CE(0));
R10000_CE(0) <= (MachineState_FFd1 AND MachineState_FFd2);

FDCPE_R100001: FDCPE port map (R10000(1),Cnt10000(1),NOT Clk,NOT Reset,'0',R10000_CE(1));
R10000_CE(1) <= (MachineState_FFd1 AND MachineState_FFd2);

FDCPE_R100002: FDCPE port map (R10000(2),Cnt10000(2),NOT Clk,NOT Reset,'0',R10000_CE(2));
R10000_CE(2) <= (MachineState_FFd1 AND MachineState_FFd2);

FDCPE_R100003: FDCPE port map (R10000(3),Cnt10000(3),NOT Clk,NOT Reset,'0',R10000_CE(3));
R10000_CE(3) <= (MachineState_FFd1 AND MachineState_FFd2);

FDCPE_R10000: FDCPE port map (R1000(0),Cnt1000(0),NOT Clk,NOT Reset,'0',R1000_CE(0));
R1000_CE(0) <= (MachineState_FFd1 AND MachineState_FFd2);

FDCPE_R10001: FDCPE port map (R1000(1),Cnt1000(1),NOT Clk,NOT Reset,'0',R1000_CE(1));
R1000_CE(1) <= (MachineState_FFd1 AND MachineState_FFd2);

FDCPE_R10002: FDCPE port map (R1000(2),Cnt1000(2),NOT Clk,NOT Reset,'0',R1000_CE(2));
R1000_CE(2) <= (MachineState_FFd1 AND MachineState_FFd2);

FDCPE_R10003: FDCPE port map (R1000(3),Cnt1000(3),NOT Clk,NOT Reset,'0',R1000_CE(3));
R1000_CE(3) <= (MachineState_FFd1 AND MachineState_FFd2);

FDCPE_R1000: FDCPE port map (R100(0),Cnt100(0),NOT Clk,NOT Reset,'0',R100_CE(0));
R100_CE(0) <= (MachineState_FFd1 AND MachineState_FFd2);

FDCPE_R1001: FDCPE port map (R100(1),Cnt100(1),NOT Clk,NOT Reset,'0',R100_CE(1));
R100_CE(1) <= (MachineState_FFd1 AND MachineState_FFd2);

FDCPE_R1002: FDCPE port map (R100(2),Cnt100(2),NOT Clk,NOT Reset,'0',R100_CE(2));
R100_CE(2) <= (MachineState_FFd1 AND MachineState_FFd2);

FDCPE_R1003: FDCPE port map (R100(3),Cnt100(3),NOT Clk,NOT Reset,'0',R100_CE(3));
R100_CE(3) <= (MachineState_FFd1 AND MachineState_FFd2);

FDCPE_R100: FDCPE port map (R10(0),Cnt10(0),NOT Clk,NOT Reset,'0',R10_CE(0));
R10_CE(0) <= (MachineState_FFd1 AND MachineState_FFd2);

FDCPE_R101: FDCPE port map (R10(1),Cnt10(1),NOT Clk,NOT Reset,'0',R10_CE(1));
R10_CE(1) <= (MachineState_FFd1 AND MachineState_FFd2);

FDCPE_R102: FDCPE port map (R10(2),Cnt10(2),NOT Clk,NOT Reset,'0',R10_CE(2));
R10_CE(2) <= (MachineState_FFd1 AND MachineState_FFd2);

FDCPE_R103: FDCPE port map (R10(3),Cnt10(3),NOT Clk,NOT Reset,'0',R10_CE(3));
R10_CE(3) <= (MachineState_FFd1 AND MachineState_FFd2);

FDCPE_R10: FDCPE port map (R1(0),Cnt1(0),NOT Clk,NOT Reset,'0',R1_CE(0));
R1_CE(0) <= (MachineState_FFd1 AND MachineState_FFd2);

FDCPE_R11: FDCPE port map (R1(1),Cnt1(1),NOT Clk,NOT Reset,'0',R1_CE(1));
R1_CE(1) <= (MachineState_FFd1 AND MachineState_FFd2);

FDCPE_R12: FDCPE port map (R1(2),Cnt1(2),NOT Clk,NOT Reset,'0',R1_CE(2));
R1_CE(2) <= (MachineState_FFd1 AND MachineState_FFd2);

FDCPE_R13: FDCPE port map (R1(3),Cnt1(3),NOT Clk,NOT Reset,'0',R1_CE(3));
R1_CE(3) <= (MachineState_FFd1 AND MachineState_FFd2);

FDCPE_RangeKInstance/ShRegister0: FDCPE port map (RangeKInstance/ShRegister(0),RangeKey,FDiv(2),'0',NOT Reset,'1');

FDCPE_RangeKInstance/ShRegister1: FDCPE port map (RangeKInstance/ShRegister(1),RangeKInstance/ShRegister(0),FDiv(2),'0',NOT Reset,'1');

FDCPE_RangeKInstance/ShRegister2: FDCPE port map (RangeKInstance/ShRegister(2),RangeKInstance/ShRegister(1),FDiv(2),'0',NOT Reset,'1');

FDCPE_RangeKInstance/ShRegister3: FDCPE port map (RangeKInstance/ShRegister(3),RangeKInstance/ShRegister(2),FDiv(2),'0',NOT Reset,'1');

LDCP_RangeKeyStatus: LDCP port map (RangeKeyStatus,NOT '0',,RangeKeyStatus_CLR,'0');
RangeKeyStatus_G <= (NOT RangeKInstance/ShRegister(0) AND 
	NOT RangeKInstance/ShRegister(1) AND NOT RangeKInstance/ShRegister(2) AND 
	NOT RangeKInstance/ShRegister(3));
RangeKeyStatus_CLR <= (RangeKInstance/ShRegister(0) AND 
	RangeKInstance/ShRegister(1) AND RangeKInstance/ShRegister(2) AND 
	RangeKInstance/ShRegister(3));

FTCPE_RunLed: FTCPE port map (RunLed,F1HzEnable,F1HzCnt(14),NOT N_PZ_797,'0','1');


Seg_A <= NOT (((MuxDisplInstance/Blank)
	OR (MuxDisplInstance/Tetr(3) AND 
	MuxDisplInstance/Tetr(2) AND MuxDisplInstance/Tetr(1) AND 
	NOT MuxDisplInstance/Tetr(0))
	OR (MuxDisplInstance/Tetr(3) AND 
	NOT MuxDisplInstance/Tetr(2) AND MuxDisplInstance/Tetr(1) AND 
	MuxDisplInstance/Tetr(0))
	OR (NOT MuxDisplInstance/Tetr(3) AND 
	MuxDisplInstance/Tetr(2) AND NOT MuxDisplInstance/Tetr(1) AND 
	NOT MuxDisplInstance/Tetr(0))
	OR (NOT MuxDisplInstance/Tetr(3) AND 
	NOT MuxDisplInstance/Tetr(2) AND MuxDisplInstance/Tetr(1) AND 
	NOT MuxDisplInstance/Tetr(0))));


Seg_B <= (NOT MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Blank)
	XOR ((MuxDisplInstance/Tetr(2) AND 
	MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Blank)
	OR (MuxDisplInstance/Tetr(3) AND 
	NOT MuxDisplInstance/Tetr(2) AND MuxDisplInstance/Tetr(1) AND NOT MuxDisplInstance/Blank)
	OR (NOT MuxDisplInstance/Tetr(3) AND 
	NOT MuxDisplInstance/Tetr(1) AND NOT MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Blank));


Seg_C <= NOT (((MuxDisplInstance/Blank)
	OR (NOT MuxDisplInstance/Tetr(3) AND 
	NOT MuxDisplInstance/Tetr(2) AND NOT MuxDisplInstance/Tetr(1))
	OR (NOT MuxDisplInstance/Tetr(3) AND 
	NOT MuxDisplInstance/Tetr(2) AND MuxDisplInstance/Tetr(0))
	OR (MuxDisplInstance/Tetr(3) AND 
	MuxDisplInstance/Tetr(2) AND NOT MuxDisplInstance/Tetr(1) AND 
	MuxDisplInstance/Tetr(0))));


Seg_D <= NOT (((MuxDisplInstance/Blank)
	OR (NOT MuxDisplInstance/Tetr(2) AND 
	NOT MuxDisplInstance/Tetr(1) AND NOT MuxDisplInstance/Tetr(0))
	OR (MuxDisplInstance/Tetr(3) AND 
	MuxDisplInstance/Tetr(2) AND MuxDisplInstance/Tetr(1) AND 
	NOT MuxDisplInstance/Tetr(0))
	OR (MuxDisplInstance/Tetr(3) AND 
	NOT MuxDisplInstance/Tetr(2) AND MuxDisplInstance/Tetr(1) AND 
	MuxDisplInstance/Tetr(0))
	OR (NOT MuxDisplInstance/Tetr(3) AND 
	MuxDisplInstance/Tetr(2) AND NOT MuxDisplInstance/Tetr(1) AND 
	MuxDisplInstance/Tetr(0))));


Seg_E <= ((NOT MuxDisplInstance/Tetr(3) AND 
	NOT MuxDisplInstance/Tetr(2) AND NOT MuxDisplInstance/Blank)
	OR (NOT MuxDisplInstance/Tetr(3) AND 
	NOT MuxDisplInstance/Tetr(1) AND NOT MuxDisplInstance/Blank)
	OR (MuxDisplInstance/Tetr(2) AND 
	MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Blank)
	OR (NOT MuxDisplInstance/Tetr(1) AND 
	MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Blank));


Seg_F <= (NOT MuxDisplInstance/Tetr(3) AND NOT MuxDisplInstance/Blank)
	XOR ((MuxDisplInstance/Tetr(3) AND 
	NOT MuxDisplInstance/Tetr(2) AND MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Blank)
	OR (MuxDisplInstance/Tetr(3) AND 
	MuxDisplInstance/Tetr(1) AND MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Blank)
	OR (NOT MuxDisplInstance/Tetr(2) AND 
	MuxDisplInstance/Tetr(1) AND NOT MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Blank));


Seg_G <= NOT (((MuxDisplInstance/Blank)
	OR (MuxDisplInstance/Tetr(3) AND 
	MuxDisplInstance/Tetr(2) AND MuxDisplInstance/Tetr(1))
	OR (MuxDisplInstance/Tetr(3) AND 
	NOT MuxDisplInstance/Tetr(2) AND NOT MuxDisplInstance/Tetr(1) AND 
	NOT MuxDisplInstance/Tetr(0))
	OR (NOT MuxDisplInstance/Tetr(3) AND 
	NOT MuxDisplInstance/Tetr(2) AND MuxDisplInstance/Tetr(1) AND 
	MuxDisplInstance/Tetr(0))));


Seg_K <= ((MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND NOT HzRange)
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND HzRange));


Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE); 
 FDDCPE (Q,D,C,CLR,PRE,CE); 
 FTCPE (Q,D,C,CLR,PRE,CE); 
 FTDCPE (Q,D,C,CLR,PRE,CE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC2C256-6-VQ100


   --------------------------------------------------  
  /100 98  96  94  92  90  88  86  84  82  80  78  76  \
 |   99  97  95  93  91  89  87  85  83  81  79  77    |
 | 1                                               75  | 
 | 2                                               74  | 
 | 3                                               73  | 
 | 4                                               72  | 
 | 5                                               71  | 
 | 6                                               70  | 
 | 7                                               69  | 
 | 8                                               68  | 
 | 9                                               67  | 
 | 10                                              66  | 
 | 11                                              65  | 
 | 12                                              64  | 
 | 13                XC2C256-6-VQ100               63  | 
 | 14                                              62  | 
 | 15                                              61  | 
 | 16                                              60  | 
 | 17                                              59  | 
 | 18                                              58  | 
 | 19                                              57  | 
 | 20                                              56  | 
 | 21                                              55  | 
 | 22                                              54  | 
 | 23                                              53  | 
 | 24                                              52  | 
 | 25                                              51  | 
 |   27  29  31  33  35  37  39  41  43  45  47  49    |
  \26  28  30  32  34  36  38  40  42  44  46  48  50  /
   --------------------------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 Seg_K                            51 VCCIO-1.8                     
  2 Seg_G                            52 PGND                          
  3 Seg_F                            53 PGND                          
  4 Seg_E                            54 PGND                          
  5 VCCAUX                           55 GoKey                         
  6 Seg_D                            56 RangeKey                      
  7 Seg_C                            57 VCC                           
  8 Seg_A                            58 PGND                          
  9 Seg_B                            59 PGND                          
 10 PGND                             60 PGND                          
 11 PGND                             61 PGND                          
 12 PGND                             62 GND                           
 13 PGND                             63 PGND                          
 14 PGND                             64 PGND                          
 15 PGND                             65 Reset                         
 16 PGND                             66 PGND                          
 17 RunLed                           67 PGND                          
 18 DSel0                            68 PGND                          
 19 DSel1                            69 GND                           
 20 VCCIO-1.8                        70 PGND                          
 21 GND                              71 PGND                          
 22 Clk                              72 PGND                          
 23 FInp                             73 PGND                          
 24 DSel2                            74 PGND                          
 25 GND                              75 GND                           
 26 VCC                              76 PGND                          
 27 DSel3                            77 PGND                          
 28 PGND                             78 PGND                          
 29 PGND                             79 PGND                          
 30 PGND                             80 PGND                          
 31 GND                              81 PGND                          
 32 PGND                             82 PGND                          
 33 PGND                             83 TDO                           
 34 PGND                             84 GND                           
 35 PGND                             85 PGND                          
 36 PGND                             86 PGND                          
 37 PGND                             87 PGND                          
 38 VCCIO-1.8                        88 VCCIO-1.8                     
 39 PGND                             89 PGND                          
 40 PGND                             90 PGND                          
 41 PGND                             91 PGND                          
 42 PGND                             92 PGND                          
 43 PGND                             93 PGND                          
 44 PGND                             94 PGND                          
 45 TDI                              95 PGND                          
 46 PGND                             96 PGND                          
 47 TMS                              97 PGND                          
 48 TCK                              98 VCCIO-1.8                     
 49 PGND                             99 PGND                          
 50 PGND                            100 GND                           


Legend :  NC  = Not Connected, unbonded pin
        PGND  = Unused I/O configured as additional Ground pin
         KPR  = Unused I/O with weak keeper (leave unconnected)
         WPU  = Unused I/O with weak pull up (leave unconnected)
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
      VCCAUX  = Power supply for JTAG pins
   VCCIO-3.3  = I/O supply voltage for LVTTL, LVCMOS33, SSTL3_I
   VCCIO-2.5  = I/O supply voltage for LVCMOS25, SSTL2_I
   VCCIO-1.8  = I/O supply voltage for LVCMOS18
   VCCIO-1.5  = I/O supply voltage for LVCMOS15, HSTL_I
        VREF  = Reference voltage for indicated input standard
       *VREF  = Reference voltage pin selected by software
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc2c256-6-VQ100
Optimization Method                         : DENSITY
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Set Unused I/O Pin Termination              : GROUND
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
Enable Input Registers                      : ON
Function Block Fan-in Limit                 : 38
Use DATA_GATE Attribute                     : ON
Set Tristate Outputs to Termination Mode    : PULLUP
Default Voltage Standard for All Outputs    : LVCMOS18
Input Limit                                 : 32
Pterm Limit                                 : 28