Timing Report

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Design Name DispLCD
Device, Speed (SpeedFile Version) XC2C256, -6 (14.0 Advance Product Specification)
Date Created Sun May 24 23:25:22 2009
Created By Timing Report Generator: version J.36
Copyright Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.

Performance Summary
Min. Clock Period 12.000 ns.
Max. Clock Frequency (fSYSTEM) 83.333 MHz.
Limited by Clock Pulse Width for FDiv<11>_MC.Q
Clock to Setup (tCYC) 5.000 ns.
Clock Pad to Output Pad Delay (tCO) 16.700 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS1000 0.0 0.0 0 0
TS1001 0.0 0.0 0 0
TS1002 0.0 0.0 0 0
AUTO_TS_F2F 0.0 5.0 113 113
AUTO_TS_P2P 0.0 16.7 17 17
AUTO_TS_P2F 0.0 1.8 1 1
AUTO_TS_F2P 0.0 11.4 75 75


Constraint: TS1000

Description: PERIOD:PERIOD_FDiv<11>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1001

Description: PERIOD:PERIOD_Clk:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1002

Description: PERIOD:PERIOD_FClk_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
Cnt10<0>.Q to Cnt10<1>.D 0.000 5.000 -5.000
Cnt10<0>.Q to Cnt10<2>.D 0.000 5.000 -5.000
Cnt10<0>.Q to Cnt10<3>.D 0.000 5.000 -5.000


Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
Clk to LCD10_A 0.000 16.700 -16.700
Clk to LCD10_B 0.000 16.700 -16.700
Clk to LCD10_C 0.000 16.700 -16.700


Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
Clk to Clk.GCK 0.000 1.800 -1.800


Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
LCDMuxInstance/RegLCD10<1>.Q to LCD10_A 0.000 11.400 -11.400
LCDMuxInstance/RegLCD10<1>.Q to LCD10_B 0.000 11.400 -11.400
LCDMuxInstance/RegLCD10<1>.Q to LCD10_C 0.000 11.400 -11.400



Number of constraints not met: 4

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
FDiv<11>_MC.Q 83.333 Limited by Clock Pulse Width for FDiv<11>_MC.Q
Clk 256.410 Limited by Cycle Time for Clk
FClk_MC.Q 212.766 Limited by Cycle Time for FClk_MC.Q

Setup/Hold Times for Clocks


Clock to Pad Timing

Clock Clk to Pad
Destination Pad Clock (edge) to Pad
LCD10_A 16.700
LCD10_B 16.700
LCD10_C 16.700
LCD10_D 16.700
LCD10_E 16.700
LCD10_F 16.700
LCD10_G 16.700
LCD1_A 14.000
LCD1_B 14.000
LCD1_C 14.000
LCD1_D 14.000
LCD1_E 14.000
LCD1_F 14.000
LCD1_G 14.000
LCD10_DP 11.000
LCD1_DP 11.000
LCD_BP 8.000


Clock to Setup Times for Clocks

Clock to Setup for clock FDiv<11>.Q
Source Destination Delay
Cnt10<0>.Q Cnt10<1>.D 5.000
Cnt10<0>.Q Cnt10<2>.D 5.000
Cnt10<0>.Q Cnt10<3>.D 5.000
Cnt10<1>.Q Cnt10<1>.D 5.000
Cnt10<1>.Q Cnt10<2>.D 5.000
Cnt10<1>.Q Cnt10<3>.D 5.000
Cnt10<2>.Q Cnt10<1>.D 5.000
Cnt10<2>.Q Cnt10<3>.D 5.000
Cnt10<3>.Q Cnt10<1>.D 5.000
Cnt10<3>.Q Cnt10<3>.D 5.000
Cnt1<0>.Q Cnt10<0>.D 5.000
Cnt1<0>.Q Cnt10<1>.D 5.000
Cnt1<0>.Q Cnt10<2>.D 5.000
Cnt1<0>.Q Cnt10<3>.D 5.000
Cnt1<0>.Q Cnt1<1>.D 5.000
Cnt1<0>.Q Cnt1<3>.D 5.000
Cnt1<1>.Q Cnt10<0>.D 5.000
Cnt1<1>.Q Cnt10<1>.D 5.000
Cnt1<1>.Q Cnt10<2>.D 5.000
Cnt1<1>.Q Cnt10<3>.D 5.000
Cnt1<1>.Q Cnt1<1>.D 5.000
Cnt1<1>.Q Cnt1<3>.D 5.000
Cnt1<2>.Q Cnt10<0>.D 5.000
Cnt1<2>.Q Cnt10<1>.D 5.000
Cnt1<2>.Q Cnt10<2>.D 5.000
Cnt1<2>.Q Cnt10<3>.D 5.000
Cnt1<2>.Q Cnt1<1>.D 5.000
Cnt1<2>.Q Cnt1<3>.D 5.000
Cnt1<3>.Q Cnt10<0>.D 5.000
Cnt1<3>.Q Cnt10<1>.D 5.000
Cnt1<3>.Q Cnt10<2>.D 5.000
Cnt1<3>.Q Cnt10<3>.D 5.000
Cnt1<3>.Q Cnt1<1>.D 5.000
Cnt1<3>.Q Cnt1<3>.D 5.000
Cnt1<0>.Q Cnt1<2>.D 4.700
Cnt1<1>.Q Cnt1<2>.D 4.700

Clock to Setup for clock Clk
Source Destination Delay
FDivInstance/FDivCnt<0>.Q FClk.D 3.900
FDivInstance/FDivCnt<0>.Q FDivInstance/FDivCnt<1>.D 3.900
FDivInstance/FDivCnt<1>.Q FClk.D 3.900

Clock to Setup for clock FClk.Q
Source Destination Delay
FDiv<0>.Q FDiv<10>.D 4.700
FDiv<0>.Q FDiv<11>.D 4.700
FDiv<0>.Q FDiv<1>.D 4.700
FDiv<0>.Q FDiv<2>.D 4.700
FDiv<0>.Q FDiv<3>.D 4.700
FDiv<0>.Q FDiv<4>.D 4.700
FDiv<0>.Q FDiv<5>.D 4.700
FDiv<0>.Q FDiv<7>.D 4.700
FDiv<0>.Q FDiv<8>.D 4.700
FDiv<0>.Q FDiv<9>.D 4.700
FDiv<0>.Q LCD_BP.D 4.700
FDiv<10>.Q FDiv<11>.D 4.700
FDiv<1>.Q FDiv<10>.D 4.700
FDiv<1>.Q FDiv<11>.D 4.700
FDiv<1>.Q FDiv<2>.D 4.700
FDiv<1>.Q FDiv<3>.D 4.700
FDiv<1>.Q FDiv<4>.D 4.700
FDiv<1>.Q FDiv<5>.D 4.700
FDiv<1>.Q FDiv<7>.D 4.700
FDiv<1>.Q FDiv<8>.D 4.700
FDiv<1>.Q FDiv<9>.D 4.700
FDiv<1>.Q LCD_BP.D 4.700
FDiv<2>.Q FDiv<10>.D 4.700
FDiv<2>.Q FDiv<11>.D 4.700
FDiv<2>.Q FDiv<3>.D 4.700
FDiv<2>.Q FDiv<4>.D 4.700
FDiv<2>.Q FDiv<5>.D 4.700
FDiv<2>.Q FDiv<7>.D 4.700
FDiv<2>.Q FDiv<8>.D 4.700
FDiv<2>.Q FDiv<9>.D 4.700
FDiv<2>.Q LCD_BP.D 4.700
FDiv<3>.Q FDiv<10>.D 4.700
FDiv<3>.Q FDiv<11>.D 4.700
FDiv<3>.Q FDiv<4>.D 4.700
FDiv<3>.Q FDiv<5>.D 4.700
FDiv<3>.Q FDiv<7>.D 4.700
FDiv<3>.Q FDiv<8>.D 4.700
FDiv<3>.Q FDiv<9>.D 4.700
FDiv<3>.Q LCD_BP.D 4.700
FDiv<4>.Q FDiv<10>.D 4.700
FDiv<4>.Q FDiv<11>.D 4.700
FDiv<4>.Q FDiv<5>.D 4.700
FDiv<4>.Q FDiv<7>.D 4.700
FDiv<4>.Q FDiv<8>.D 4.700
FDiv<4>.Q FDiv<9>.D 4.700
FDiv<4>.Q LCD_BP.D 4.700
FDiv<5>.Q FDiv<10>.D 4.700
FDiv<5>.Q FDiv<11>.D 4.700
FDiv<5>.Q FDiv<7>.D 4.700
FDiv<5>.Q FDiv<8>.D 4.700
FDiv<5>.Q FDiv<9>.D 4.700
FDiv<5>.Q LCD_BP.D 4.700
FDiv<7>.Q FDiv<10>.D 4.700
FDiv<7>.Q FDiv<11>.D 4.700
FDiv<7>.Q FDiv<8>.D 4.700
FDiv<7>.Q FDiv<9>.D 4.700
FDiv<8>.Q FDiv<10>.D 4.700
FDiv<8>.Q FDiv<11>.D 4.700
FDiv<8>.Q FDiv<9>.D 4.700
FDiv<9>.Q FDiv<10>.D 4.700
FDiv<9>.Q FDiv<11>.D 4.700
LCD_BP.Q FDiv<10>.D 4.700
LCD_BP.Q FDiv<11>.D 4.700
LCD_BP.Q FDiv<7>.D 4.700
LCD_BP.Q FDiv<8>.D 4.700
LCD_BP.Q FDiv<9>.D 4.700


Pad to Pad List

Source Pad Destination Pad Delay



Number of paths analyzed: 206
Number of Timing errors: 206
Analysis Completed: Sun May 24 23:25:22 2009