Timing Report

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Design Name Pierwszy
Device, Speed (SpeedFile Version) XC2C256, -6 (14.0 Advance Product Specification)
Date Created Sun Apr 12 23:38:07 2009
Created By Timing Report Generator: version J.36
Copyright Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.

Performance Summary
Min. Clock Period 4.700 ns.
Max. Clock Frequency (fSYSTEM) 212.766 MHz.
Limited by Cycle Time for FDiv<6>_MC.Q
Clock to Setup (tCYC) 4.700 ns.
Pad to Pad Delay (tPD) 6.000 ns.
Clock Pad to Output Pad Delay (tCO) 13.700 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS1000 0.0 0.0 0 0
TS1001 0.0 0.0 0 0
AUTO_TS_F2F 0.0 4.7 22 22
AUTO_TS_P2P 0.0 13.7 24 24
AUTO_TS_P2F 0.0 1.8 1 1
AUTO_TS_F2P 0.0 8.4 16 16


Constraint: TS1000

Description: PERIOD:PERIOD_Clk:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1001

Description: PERIOD:PERIOD_FDiv<6>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
SelCnt<0>.Q to SelCnt<1>.D 0.000 4.700 -4.700
FDiv<0>.Q to FDiv<1>.D 0.000 3.900 -3.900
FDiv<0>.Q to FDiv<2>.D 0.000 3.900 -3.900


Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
Clk to Seg_B 0.000 13.700 -13.700
Clk to Seg_C 0.000 13.700 -13.700
Clk to Seg_D 0.000 13.700 -13.700


Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
Clk to Clk.GCK 0.000 1.800 -1.800


Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
SelCnt<0>.Q to Seg_B 0.000 8.400 -8.400
SelCnt<0>.Q to Seg_C 0.000 8.400 -8.400
SelCnt<0>.Q to Seg_D 0.000 8.400 -8.400



Number of constraints not met: 4

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
Clk 256.410 Limited by Cycle Time for Clk
FDiv<6>_MC.Q 212.766 Limited by Cycle Time for FDiv<6>_MC.Q

Setup/Hold Times for Clocks


Clock to Pad Timing

Clock Clk to Pad
Destination Pad Clock (edge) to Pad
Seg_B 13.700
Seg_C 13.700
Seg_D 13.700
Seg_G 13.700
DSel0 10.700
DSel1 10.700
DSel2 10.700
DSel3 10.700


Clock to Setup Times for Clocks

Clock to Setup for clock Clk
Source Destination Delay
FDiv<0>.Q FDiv<1>.D 3.900
FDiv<0>.Q FDiv<2>.D 3.900
FDiv<0>.Q FDiv<3>.D 3.900
FDiv<0>.Q FDiv<4>.D 3.900
FDiv<0>.Q FDiv<5>.D 3.900
FDiv<0>.Q FDiv<6>.D 3.900
FDiv<1>.Q FDiv<2>.D 3.900
FDiv<1>.Q FDiv<3>.D 3.900
FDiv<1>.Q FDiv<4>.D 3.900
FDiv<1>.Q FDiv<5>.D 3.900
FDiv<1>.Q FDiv<6>.D 3.900
FDiv<2>.Q FDiv<3>.D 3.900
FDiv<2>.Q FDiv<4>.D 3.900
FDiv<2>.Q FDiv<5>.D 3.900
FDiv<2>.Q FDiv<6>.D 3.900
FDiv<3>.Q FDiv<4>.D 3.900
FDiv<3>.Q FDiv<5>.D 3.900
FDiv<3>.Q FDiv<6>.D 3.900
FDiv<4>.Q FDiv<5>.D 3.900
FDiv<4>.Q FDiv<6>.D 3.900
FDiv<5>.Q FDiv<6>.D 3.900

Clock to Setup for clock FDiv<6>.Q
Source Destination Delay
SelCnt<0>.Q SelCnt<1>.D 4.700


Pad to Pad List

Source Pad Destination Pad Delay
KeyIn0 Seg_B 6.000
KeyIn0 Seg_C 6.000
KeyIn0 Seg_D 6.000
KeyIn0 Seg_G 6.000
KeyIn1 Seg_B 6.000
KeyIn1 Seg_C 6.000
KeyIn1 Seg_D 6.000
KeyIn1 Seg_G 6.000
KeyIn2 Seg_B 6.000
KeyIn2 Seg_C 6.000
KeyIn2 Seg_D 6.000
KeyIn2 Seg_G 6.000
KeyIn3 Seg_B 6.000
KeyIn3 Seg_C 6.000
KeyIn3 Seg_D 6.000
KeyIn3 Seg_G 6.000



Number of paths analyzed: 63
Number of Timing errors: 63
Analysis Completed: Sun Apr 12 23:38:07 2009