Timing Report

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Design Name Generator
Device, Speed (SpeedFile Version) XC2C256, -6 (14.0 Advance Product Specification)
Date Created Tue Mar 30 23:18:42 2010
Created By Timing Report Generator: version J.36
Copyright Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.
Possible asynchronous logic: Clock pin 'OutSig.CLKF' has multiple original clock nets 'SpeedKeyInp' 'Clk' 'FDiv<3>_MC.Q'.
Possible asynchronous logic: Clock pin 'FB3__ctinst/4' has multiple original clock nets 'SpeedKeyInp' 'Clk' 'FDiv<3>_MC.Q'.
Possible asynchronous logic: Clock pin 'BinCnt<7>.CLKF' has multiple original clock nets 'SpeedKeyInp' 'Clk' 'FDiv<3>_MC.Q'.
Possible asynchronous logic: Clock pin 'DirKeyStatus.CLKF' has multiple original clock nets 'DirKeyInstance/ShRegister<3>_MC.Q' 'DirKeyInstance/ShRegister<2>_MC.Q' 'DirKeyInstance/ShRegister<1>_MC.Q' 'DirKeyInstance/ShRegister<0>_MC.Q'.
Possible asynchronous logic: Clock pin 'ModeKeyStatus.CLKF' has multiple original clock nets 'ModeKeyInstance/ShRegister<3>_MC.Q' 'ModeKeyInstance/ShRegister<2>_MC.Q' 'ModeKeyInstance/ShRegister<1>_MC.Q' 'ModeKeyInstance/ShRegister<0>_MC.Q'.

Performance Summary
Min. Clock Period 12.000 ns.
Max. Clock Frequency (fSYSTEM) 83.333 MHz.
Limited by Clock Pulse Width for SetKeyStatus_MC.Q
Clock to Setup (tCYC) 11.000 ns.
Pad to Pad Delay (tPD) 5.700 ns.
Setup to Clock at the Pad (tSU) 2.700 ns.
Clock Pad to Output Pad Delay (tCO) 17.500 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS1000 0.0 0.0 0 0
TS1001 0.0 0.0 0 0
TS1002 0.0 0.0 0 0
TS1003 0.0 0.0 0 0
TS1004 0.0 0.0 0 0
TS1005 0.0 0.0 0 0
TS1006 0.0 0.0 0 0
TS1007 0.0 0.0 0 0
TS1008 0.0 0.0 0 0
TS1009 0.0 0.0 0 0
TS1010 0.0 0.0 0 0
TS1011 0.0 0.0 0 0
TS1012 0.0 0.0 0 0
TS1013 0.0 0.0 0 0
TS1014 0.0 0.0 0 0
AUTO_TS_F2F 0.0 11.0 442 442
AUTO_TS_P2P 0.0 17.5 16 16
AUTO_TS_P2F 0.0 6.8 15 15
AUTO_TS_F2P 0.0 8.7 139 139


Constraint: TS1000

Description: PERIOD:PERIOD_FDiv<6>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1001

Description: PERIOD:PERIOD_SetKeyStatus_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1002

Description: PERIOD:PERIOD_SpeedKeyInp:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1003

Description: PERIOD:PERIOD_DirKeyInstance/ShRegister<3>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1004

Description: PERIOD:PERIOD_DirKeyInstance/ShRegister<2>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1005

Description: PERIOD:PERIOD_DirKeyInstance/ShRegister<1>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1006

Description: PERIOD:PERIOD_DirKeyInstance/ShRegister<0>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1007

Description: PERIOD:PERIOD_FDiv<4>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1008

Description: PERIOD:PERIOD_ModeKeyInstance/ShRegister<3>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1009

Description: PERIOD:PERIOD_ModeKeyInstance/ShRegister<2>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1010

Description: PERIOD:PERIOD_ModeKeyInstance/ShRegister<1>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1011

Description: PERIOD:PERIOD_ModeKeyInstance/ShRegister<0>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1012

Description: PERIOD:PERIOD_Clk:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1013

Description: PERIOD:PERIOD_FClk_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1014

Description: PERIOD:PERIOD_FDiv<3>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
BinCnt<0>.Q to BinCnt<0>.D 0.000 11.000 -11.000
BinCnt<0>.Q to BinCnt<1>.D 0.000 11.000 -11.000
BinCnt<0>.Q to BinCnt<2>.D 0.000 11.000 -11.000


Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
Clk to Seg_A 0.000 17.500 -17.500
Clk to Seg_B 0.000 17.500 -17.500
Clk to Seg_C 0.000 17.500 -17.500


Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
Clk to BinCnt<7>.CLKF 0.000 6.800 -6.800
Clk to FB3__ctinst/4 0.000 6.800 -6.800
Clk to OutSig.CLKF 0.000 6.800 -6.800


Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
LCmpReg<0>.Q to Seg_A 0.000 8.700 -8.700
LCmpReg<0>.Q to Seg_D 0.000 8.700 -8.700
LCmpReg<0>.Q to Seg_F 0.000 8.700 -8.700



Number of constraints not met: 4

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
FDiv<6>_MC.Q 212.766 Limited by Cycle Time for FDiv<6>_MC.Q
SetKeyStatus_MC.Q 83.333 Limited by Clock Pulse Width for SetKeyStatus_MC.Q
SpeedKeyInp 83.333 Limited by Clock Pulse Width for SpeedKeyInp
DirKeyInstance/ShRegister<3>_MC.Q 83.333 Limited by Clock Pulse Width for DirKeyInstance/ShRegister<3>_MC.Q
DirKeyInstance/ShRegister<2>_MC.Q 83.333 Limited by Clock Pulse Width for DirKeyInstance/ShRegister<2>_MC.Q
DirKeyInstance/ShRegister<1>_MC.Q 83.333 Limited by Clock Pulse Width for DirKeyInstance/ShRegister<1>_MC.Q
DirKeyInstance/ShRegister<0>_MC.Q 83.333 Limited by Clock Pulse Width for DirKeyInstance/ShRegister<0>_MC.Q
FDiv<4>_MC.Q 200.000 Limited by Cycle Time for FDiv<4>_MC.Q
ModeKeyInstance/ShRegister<3>_MC.Q 83.333 Limited by Clock Pulse Width for ModeKeyInstance/ShRegister<3>_MC.Q
ModeKeyInstance/ShRegister<2>_MC.Q 83.333 Limited by Clock Pulse Width for ModeKeyInstance/ShRegister<2>_MC.Q
ModeKeyInstance/ShRegister<1>_MC.Q 83.333 Limited by Clock Pulse Width for ModeKeyInstance/ShRegister<1>_MC.Q
ModeKeyInstance/ShRegister<0>_MC.Q 83.333 Limited by Clock Pulse Width for ModeKeyInstance/ShRegister<0>_MC.Q
Clk 90.909 Limited by Cycle Time for Clk
FClk_MC.Q 83.333 Limited by Clock Pulse Width for FClk_MC.Q
FDiv<3>_MC.Q 90.909 Limited by Cycle Time for FDiv<3>_MC.Q

Setup/Hold Times for Clocks

Setup/Hold Times for Clock FDiv<4>.Q
Source Pad Setup to clk (edge) Hold to clk (edge)
DirKeyInp 1.600 0.000
ModeKeyInp 1.600 0.000

Setup/Hold Times for Clock Clk
Source Pad Setup to clk (edge) Hold to clk (edge)
Reset 2.700 0.000
SetKeyInp 2.700 0.000


Clock to Pad Timing

Clock SpeedKeyInp to Pad
Destination Pad Clock (edge) to Pad
OutSig 9.500

Clock Clk to Pad
Destination Pad Clock (edge) to Pad
Seg_A 17.500
Seg_B 17.500
Seg_C 17.500
Seg_D 17.500
Seg_E 17.500
Seg_F 17.500
Seg_G 17.500
OutSig 14.500
Seg_K 14.500
DSel0 14.200
DSel1 14.200
DSel2 14.200
DSel3 14.200
DirLed 4.500


Clock to Setup Times for Clocks

Clock to Setup for clock FDiv<6>.Q
Source Destination Delay
SetupKeyInstance/DelayCnt<0>.Q SetupKeyInstance/DelayCnt<1>.D 4.700
SetupKeyInstance/DelayCnt<0>.Q SetupKeyInstance/DelayCnt<2>.D 4.700
SetupKeyInstance/DelayCnt<0>.Q SetupKeyInstance/DelayCnt<3>.D 4.700
SetupKeyInstance/DelayCnt<0>.Q SetupKeyInstance/DelayCnt<4>.D 4.700
SetupKeyInstance/DelayCnt<1>.Q SetupKeyInstance/DelayCnt<2>.D 4.700
SetupKeyInstance/DelayCnt<1>.Q SetupKeyInstance/DelayCnt<3>.D 4.700
SetupKeyInstance/DelayCnt<1>.Q SetupKeyInstance/DelayCnt<4>.D 4.700
SetupKeyInstance/DelayCnt<2>.Q SetupKeyInstance/DelayCnt<3>.D 4.700
SetupKeyInstance/DelayCnt<2>.Q SetupKeyInstance/DelayCnt<4>.D 4.700
SetupKeyInstance/DelayCnt<3>.Q SetupKeyInstance/DelayCnt<4>.D 4.700

Clock to Setup for clock SetKeyStatus.Q
Source Destination Delay
LCmpReg<0>.Q LCmpReg<1>.D 5.000
LCmpReg<0>.Q LCmpReg<2>.D 5.000
LCmpReg<0>.Q LCmpReg<3>.D 5.000
LCmpReg<0>.Q LCmpReg<4>.D 5.000
LCmpReg<0>.Q LCmpReg<5>.D 5.000
LCmpReg<0>.Q LCmpReg<6>.D 5.000
LCmpReg<0>.Q LCmpReg<7>.D 5.000
LCmpReg<1>.Q LCmpReg<2>.D 5.000
LCmpReg<1>.Q LCmpReg<3>.D 5.000
LCmpReg<1>.Q LCmpReg<4>.D 5.000
LCmpReg<1>.Q LCmpReg<5>.D 5.000
LCmpReg<1>.Q LCmpReg<6>.D 5.000
LCmpReg<1>.Q LCmpReg<7>.D 5.000
LCmpReg<2>.Q LCmpReg<3>.D 5.000
LCmpReg<2>.Q LCmpReg<4>.D 5.000
LCmpReg<2>.Q LCmpReg<5>.D 5.000
LCmpReg<2>.Q LCmpReg<6>.D 5.000
LCmpReg<2>.Q LCmpReg<7>.D 5.000
LCmpReg<3>.Q LCmpReg<4>.D 5.000
LCmpReg<3>.Q LCmpReg<5>.D 5.000
LCmpReg<3>.Q LCmpReg<6>.D 5.000
LCmpReg<3>.Q LCmpReg<7>.D 5.000
LCmpReg<4>.Q LCmpReg<5>.D 5.000
LCmpReg<4>.Q LCmpReg<6>.D 5.000
LCmpReg<4>.Q LCmpReg<7>.D 5.000
LCmpReg<5>.Q LCmpReg<6>.D 5.000
LCmpReg<5>.Q LCmpReg<7>.D 5.000
LCmpReg<6>.Q LCmpReg<7>.D 5.000
UCmpReg<0>.Q UCmpReg<1>.D 5.000
UCmpReg<0>.Q UCmpReg<2>.D 5.000
UCmpReg<0>.Q UCmpReg<3>.D 5.000
UCmpReg<0>.Q UCmpReg<4>.D 5.000
UCmpReg<0>.Q UCmpReg<5>.D 5.000
UCmpReg<0>.Q UCmpReg<6>.D 5.000
UCmpReg<0>.Q UCmpReg<7>.D 5.000
UCmpReg<1>.Q UCmpReg<2>.D 5.000
UCmpReg<1>.Q UCmpReg<3>.D 5.000
UCmpReg<1>.Q UCmpReg<4>.D 5.000
UCmpReg<1>.Q UCmpReg<5>.D 5.000
UCmpReg<1>.Q UCmpReg<6>.D 5.000
UCmpReg<1>.Q UCmpReg<7>.D 5.000
UCmpReg<2>.Q UCmpReg<3>.D 5.000
UCmpReg<2>.Q UCmpReg<4>.D 5.000
UCmpReg<2>.Q UCmpReg<5>.D 5.000
UCmpReg<2>.Q UCmpReg<6>.D 5.000
UCmpReg<2>.Q UCmpReg<7>.D 5.000
UCmpReg<3>.Q UCmpReg<4>.D 5.000
UCmpReg<3>.Q UCmpReg<5>.D 5.000
UCmpReg<3>.Q UCmpReg<6>.D 5.000
UCmpReg<3>.Q UCmpReg<7>.D 5.000
UCmpReg<4>.Q UCmpReg<5>.D 5.000
UCmpReg<4>.Q UCmpReg<6>.D 5.000
UCmpReg<4>.Q UCmpReg<7>.D 5.000
UCmpReg<5>.Q UCmpReg<6>.D 5.000
UCmpReg<5>.Q UCmpReg<7>.D 5.000
UCmpReg<6>.Q UCmpReg<7>.D 5.000

Clock to Setup for clock SpeedKeyInp
Source Destination Delay
BinCnt<0>.Q BinCnt<0>.D 11.000
BinCnt<0>.Q BinCnt<1>.D 11.000
BinCnt<0>.Q BinCnt<2>.D 11.000
BinCnt<0>.Q BinCnt<3>.D 11.000
BinCnt<0>.Q BinCnt<4>.D 11.000
BinCnt<0>.Q BinCnt<5>.D 11.000
BinCnt<0>.Q BinCnt<6>.D 11.000
BinCnt<0>.Q BinCnt<7>.D 11.000
BinCnt<0>.Q OutSig.D 11.000
BinCnt<1>.Q BinCnt<0>.D 11.000
BinCnt<1>.Q BinCnt<1>.D 11.000
BinCnt<1>.Q BinCnt<2>.D 11.000
BinCnt<1>.Q BinCnt<3>.D 11.000
BinCnt<1>.Q BinCnt<4>.D 11.000
BinCnt<1>.Q BinCnt<5>.D 11.000
BinCnt<1>.Q BinCnt<6>.D 11.000
BinCnt<1>.Q BinCnt<7>.D 11.000
BinCnt<1>.Q OutSig.D 11.000
BinCnt<2>.Q BinCnt<0>.D 11.000
BinCnt<2>.Q BinCnt<1>.D 11.000
BinCnt<2>.Q BinCnt<2>.D 11.000
BinCnt<2>.Q BinCnt<3>.D 11.000
BinCnt<2>.Q BinCnt<4>.D 11.000
BinCnt<2>.Q BinCnt<5>.D 11.000
BinCnt<2>.Q BinCnt<6>.D 11.000
BinCnt<2>.Q BinCnt<7>.D 11.000
BinCnt<2>.Q OutSig.D 11.000
BinCnt<3>.Q BinCnt<0>.D 11.000
BinCnt<3>.Q BinCnt<1>.D 11.000
BinCnt<3>.Q BinCnt<2>.D 11.000
BinCnt<3>.Q BinCnt<3>.D 11.000
BinCnt<3>.Q BinCnt<4>.D 11.000
BinCnt<3>.Q BinCnt<5>.D 11.000
BinCnt<3>.Q BinCnt<6>.D 11.000
BinCnt<3>.Q BinCnt<7>.D 11.000
BinCnt<3>.Q OutSig.D 11.000
BinCnt<4>.Q BinCnt<0>.D 11.000
BinCnt<4>.Q BinCnt<1>.D 11.000
BinCnt<4>.Q BinCnt<2>.D 11.000
BinCnt<4>.Q BinCnt<3>.D 11.000
BinCnt<4>.Q BinCnt<4>.D 11.000
BinCnt<4>.Q BinCnt<5>.D 11.000
BinCnt<4>.Q BinCnt<6>.D 11.000
BinCnt<4>.Q BinCnt<7>.D 11.000
BinCnt<4>.Q OutSig.D 11.000
BinCnt<5>.Q BinCnt<0>.D 11.000
BinCnt<5>.Q BinCnt<1>.D 11.000
BinCnt<5>.Q BinCnt<2>.D 11.000
BinCnt<5>.Q BinCnt<3>.D 11.000
BinCnt<5>.Q BinCnt<4>.D 11.000
BinCnt<5>.Q BinCnt<5>.D 11.000
BinCnt<5>.Q BinCnt<6>.D 11.000
BinCnt<5>.Q BinCnt<7>.D 11.000
BinCnt<5>.Q OutSig.D 11.000
BinCnt<6>.Q BinCnt<0>.D 11.000
BinCnt<6>.Q BinCnt<1>.D 11.000
BinCnt<6>.Q BinCnt<2>.D 11.000
BinCnt<6>.Q BinCnt<3>.D 11.000
BinCnt<6>.Q BinCnt<4>.D 11.000
BinCnt<6>.Q BinCnt<5>.D 11.000
BinCnt<6>.Q BinCnt<6>.D 11.000
BinCnt<6>.Q BinCnt<7>.D 11.000
BinCnt<6>.Q OutSig.D 11.000
BinCnt<7>.Q BinCnt<0>.D 11.000
BinCnt<7>.Q BinCnt<1>.D 11.000
BinCnt<7>.Q BinCnt<2>.D 11.000
BinCnt<7>.Q BinCnt<3>.D 11.000
BinCnt<7>.Q BinCnt<4>.D 11.000
BinCnt<7>.Q BinCnt<5>.D 11.000
BinCnt<7>.Q BinCnt<6>.D 11.000
BinCnt<7>.Q BinCnt<7>.D 11.000
BinCnt<7>.Q OutSig.D 11.000
OutSig.Q BinCnt<0>.D 8.000
OutSig.Q BinCnt<1>.D 8.000
OutSig.Q BinCnt<2>.D 8.000
OutSig.Q BinCnt<3>.D 8.000
OutSig.Q BinCnt<4>.D 8.000
OutSig.Q BinCnt<5>.D 8.000
OutSig.Q BinCnt<6>.D 8.000
OutSig.Q BinCnt<7>.D 8.000
OutSig.Q OutSig.D 8.000

Clock to Setup for clock FDiv<4>.Q
Source Destination Delay
DirKeyInstance/ShRegister<0>.Q DirKeyInstance/ShRegister<1>.D 5.000
DirKeyInstance/ShRegister<1>.Q DirKeyInstance/ShRegister<2>.D 5.000
DirKeyInstance/ShRegister<2>.Q DirKeyInstance/ShRegister<3>.D 4.700
ModeKeyInstance/ShRegister<0>.Q ModeKeyInstance/ShRegister<1>.D 4.700
ModeKeyInstance/ShRegister<1>.Q ModeKeyInstance/ShRegister<2>.D 4.700
ModeKeyInstance/ShRegister<2>.Q ModeKeyInstance/ShRegister<3>.D 4.700

Clock to Setup for clock Clk
Source Destination Delay
BinCnt<0>.Q BinCnt<0>.D 11.000
BinCnt<0>.Q BinCnt<1>.D 11.000
BinCnt<0>.Q BinCnt<2>.D 11.000
BinCnt<0>.Q BinCnt<3>.D 11.000
BinCnt<0>.Q BinCnt<4>.D 11.000
BinCnt<0>.Q BinCnt<5>.D 11.000
BinCnt<0>.Q BinCnt<6>.D 11.000
BinCnt<0>.Q BinCnt<7>.D 11.000
BinCnt<0>.Q OutSig.D 11.000
BinCnt<1>.Q BinCnt<0>.D 11.000
BinCnt<1>.Q BinCnt<1>.D 11.000
BinCnt<1>.Q BinCnt<2>.D 11.000
BinCnt<1>.Q BinCnt<3>.D 11.000
BinCnt<1>.Q BinCnt<4>.D 11.000
BinCnt<1>.Q BinCnt<5>.D 11.000
BinCnt<1>.Q BinCnt<6>.D 11.000
BinCnt<1>.Q BinCnt<7>.D 11.000
BinCnt<1>.Q OutSig.D 11.000
BinCnt<2>.Q BinCnt<0>.D 11.000
BinCnt<2>.Q BinCnt<1>.D 11.000
BinCnt<2>.Q BinCnt<2>.D 11.000
BinCnt<2>.Q BinCnt<3>.D 11.000
BinCnt<2>.Q BinCnt<4>.D 11.000
BinCnt<2>.Q BinCnt<5>.D 11.000
BinCnt<2>.Q BinCnt<6>.D 11.000
BinCnt<2>.Q BinCnt<7>.D 11.000
BinCnt<2>.Q OutSig.D 11.000
BinCnt<3>.Q BinCnt<0>.D 11.000
BinCnt<3>.Q BinCnt<1>.D 11.000
BinCnt<3>.Q BinCnt<2>.D 11.000
BinCnt<3>.Q BinCnt<3>.D 11.000
BinCnt<3>.Q BinCnt<4>.D 11.000
BinCnt<3>.Q BinCnt<5>.D 11.000
BinCnt<3>.Q BinCnt<6>.D 11.000
BinCnt<3>.Q BinCnt<7>.D 11.000
BinCnt<3>.Q OutSig.D 11.000
BinCnt<4>.Q BinCnt<0>.D 11.000
BinCnt<4>.Q BinCnt<1>.D 11.000
BinCnt<4>.Q BinCnt<2>.D 11.000
BinCnt<4>.Q BinCnt<3>.D 11.000
BinCnt<4>.Q BinCnt<4>.D 11.000
BinCnt<4>.Q BinCnt<5>.D 11.000
BinCnt<4>.Q BinCnt<6>.D 11.000
BinCnt<4>.Q BinCnt<7>.D 11.000
BinCnt<4>.Q OutSig.D 11.000
BinCnt<5>.Q BinCnt<0>.D 11.000
BinCnt<5>.Q BinCnt<1>.D 11.000
BinCnt<5>.Q BinCnt<2>.D 11.000
BinCnt<5>.Q BinCnt<3>.D 11.000
BinCnt<5>.Q BinCnt<4>.D 11.000
BinCnt<5>.Q BinCnt<5>.D 11.000
BinCnt<5>.Q BinCnt<6>.D 11.000
BinCnt<5>.Q BinCnt<7>.D 11.000
BinCnt<5>.Q OutSig.D 11.000
BinCnt<6>.Q BinCnt<0>.D 11.000
BinCnt<6>.Q BinCnt<1>.D 11.000
BinCnt<6>.Q BinCnt<2>.D 11.000
BinCnt<6>.Q BinCnt<3>.D 11.000
BinCnt<6>.Q BinCnt<4>.D 11.000
BinCnt<6>.Q BinCnt<5>.D 11.000
BinCnt<6>.Q BinCnt<6>.D 11.000
BinCnt<6>.Q BinCnt<7>.D 11.000
BinCnt<6>.Q OutSig.D 11.000
BinCnt<7>.Q BinCnt<0>.D 11.000
BinCnt<7>.Q BinCnt<1>.D 11.000
BinCnt<7>.Q BinCnt<2>.D 11.000
BinCnt<7>.Q BinCnt<3>.D 11.000
BinCnt<7>.Q BinCnt<4>.D 11.000
BinCnt<7>.Q BinCnt<5>.D 11.000
BinCnt<7>.Q BinCnt<6>.D 11.000
BinCnt<7>.Q BinCnt<7>.D 11.000
BinCnt<7>.Q OutSig.D 11.000
Context_FFd1.Q BinCnt<3>.D 10.400
Context_FFd1.Q BinCnt<4>.D 10.400
Context_FFd1.Q BinCnt<5>.D 10.400
Context_FFd1.Q BinCnt<6>.D 10.400
Context_FFd1.Q BinCnt<7>.D 10.400
Context_FFd2.Q BinCnt<3>.D 10.400
Context_FFd2.Q BinCnt<4>.D 10.400
Context_FFd2.Q BinCnt<5>.D 10.400
Context_FFd2.Q BinCnt<6>.D 10.400
Context_FFd2.Q BinCnt<7>.D 10.400
OutSig.Q BinCnt<0>.D 8.000
OutSig.Q BinCnt<1>.D 8.000
OutSig.Q BinCnt<2>.D 8.000
OutSig.Q BinCnt<3>.D 8.000
OutSig.Q BinCnt<4>.D 8.000
OutSig.Q BinCnt<5>.D 8.000
OutSig.Q BinCnt<6>.D 8.000
OutSig.Q BinCnt<7>.D 8.000
OutSig.Q OutSig.D 8.000
Context_FFd1.Q BinCnt<2>.D 7.700
Context_FFd2.Q BinCnt<2>.D 7.700
Context_FFd1.Q BinCnt<0>.D 5.000
Context_FFd1.Q BinCnt<1>.D 5.000
Context_FFd1.Q OutSig.D 5.000
Context_FFd2.Q BinCnt<0>.D 5.000
Context_FFd2.Q BinCnt<1>.D 5.000
Context_FFd2.Q OutSig.D 5.000
MachineState_FFd1.Q Context_FFd1.CE 4.300
MachineState_FFd2.Q Context_FFd1.CE 4.300
Context_FFd1.Q Context_FFd2.D 4.200
Context_FFd2.Q Context_FFd1.D 4.200
Context_FFd2.Q Context_FFd2.D 4.200
MachineState_FFd1.Q Context_FFd2.D 4.200
MachineState_FFd1.Q MachineState_FFd1.D 4.200
MachineState_FFd1.Q MachineState_FFd2.D 4.200
MachineState_FFd2.Q Context_FFd2.D 4.200
MachineState_FFd2.Q MachineState_FFd1.D 4.200
MachineState_FFd2.Q MachineState_FFd2.D 4.200
SetKeyStatus.Q SetKeyStatus.D 4.200
SetupKeyInstance/AutomatState_FFd1.Q SetupKeyInstance/AutomatState_FFd1.D 4.200
SetupKeyInstance/AutomatState_FFd1.Q SetupKeyInstance/AutomatState_FFd2.D 4.200
SetupKeyInstance/AutomatState_FFd1.Q SetupKeyInstance/AutomatState_FFd3.D 4.200
SetupKeyInstance/AutomatState_FFd1.Q SetupKeyInstance/AutomatState_FFd4.D 4.200
SetupKeyInstance/AutomatState_FFd1.Q SetupKeyInstance/DelayCntClear.D 4.200
SetupKeyInstance/AutomatState_FFd1.Q SetupKeyInstance/DelayCntEnable.D 4.200
SetupKeyInstance/AutomatState_FFd2.Q SetKeyStatus.D 4.200
SetupKeyInstance/AutomatState_FFd2.Q SetupKeyInstance/AutomatState_FFd1.D 4.200
SetupKeyInstance/AutomatState_FFd2.Q SetupKeyInstance/AutomatState_FFd2.D 4.200
SetupKeyInstance/AutomatState_FFd2.Q SetupKeyInstance/AutomatState_FFd3.D 4.200
SetupKeyInstance/AutomatState_FFd2.Q SetupKeyInstance/AutomatState_FFd4.D 4.200
SetupKeyInstance/AutomatState_FFd2.Q SetupKeyInstance/DelayCntClear.D 4.200
SetupKeyInstance/AutomatState_FFd2.Q SetupKeyInstance/DelayCntEnable.D 4.200
SetupKeyInstance/AutomatState_FFd3.Q SetKeyStatus.D 4.200
SetupKeyInstance/AutomatState_FFd3.Q SetupKeyInstance/AutomatState_FFd1.D 4.200
SetupKeyInstance/AutomatState_FFd3.Q SetupKeyInstance/AutomatState_FFd2.D 4.200
SetupKeyInstance/AutomatState_FFd3.Q SetupKeyInstance/AutomatState_FFd3.D 4.200
SetupKeyInstance/AutomatState_FFd3.Q SetupKeyInstance/AutomatState_FFd4.D 4.200
SetupKeyInstance/AutomatState_FFd3.Q SetupKeyInstance/DelayCntClear.D 4.200
SetupKeyInstance/AutomatState_FFd3.Q SetupKeyInstance/DelayCntEnable.D 4.200
SetupKeyInstance/AutomatState_FFd4.Q SetKeyStatus.D 4.200
SetupKeyInstance/AutomatState_FFd4.Q SetupKeyInstance/AutomatState_FFd1.D 4.200
SetupKeyInstance/AutomatState_FFd4.Q SetupKeyInstance/AutomatState_FFd2.D 4.200
SetupKeyInstance/AutomatState_FFd4.Q SetupKeyInstance/AutomatState_FFd3.D 4.200
SetupKeyInstance/AutomatState_FFd4.Q SetupKeyInstance/AutomatState_FFd4.D 4.200
SetupKeyInstance/AutomatState_FFd4.Q SetupKeyInstance/DelayCntClear.D 4.200
SetupKeyInstance/AutomatState_FFd4.Q SetupKeyInstance/DelayCntEnable.D 4.200
SetupKeyInstance/DelayCntClear.Q SetupKeyInstance/DelayCntClear.D 4.200
SetupKeyInstance/DelayCntEnable.Q SetupKeyInstance/DelayCntEnable.D 4.200
FDivInstance/FDivCnt<0>.Q FClk.D 3.900
FDivInstance/FDivCnt<0>.Q FDivInstance/FDivCnt<1>.D 3.900
FDivInstance/FDivCnt<1>.Q FClk.D 3.900
MachineState_FFd1.Q DirLed.D 3.900
MachineState_FFd2.Q DirLed.D 3.900

Clock to Setup for clock FClk.Q
Source Destination Delay
FDiv<0>.Q FDiv<1>.D 5.000
FDiv<0>.Q FDiv<2>.D 5.000
FDiv<0>.Q FDiv<3>.D 5.000
FDiv<1>.Q FDiv<2>.D 5.000
FDiv<1>.Q FDiv<3>.D 5.000
FDiv<2>.Q FDiv<3>.D 5.000
FDiv<0>.Q FDiv<4>.D 4.700
FDiv<0>.Q FDiv<5>.D 4.700
FDiv<0>.Q FDiv<6>.D 4.700
FDiv<1>.Q FDiv<4>.D 4.700
FDiv<1>.Q FDiv<5>.D 4.700
FDiv<1>.Q FDiv<6>.D 4.700
FDiv<2>.Q FDiv<4>.D 4.700
FDiv<2>.Q FDiv<5>.D 4.700
FDiv<2>.Q FDiv<6>.D 4.700
FDiv<3>.Q FDiv<4>.D 4.700
FDiv<3>.Q FDiv<5>.D 4.700
FDiv<3>.Q FDiv<6>.D 4.700
FDiv<4>.Q FDiv<5>.D 4.700
FDiv<4>.Q FDiv<6>.D 4.700
FDiv<5>.Q FDiv<6>.D 4.700

Clock to Setup for clock FDiv<3>.Q
Source Destination Delay
BinCnt<0>.Q BinCnt<0>.D 11.000
BinCnt<0>.Q BinCnt<1>.D 11.000
BinCnt<0>.Q BinCnt<2>.D 11.000
BinCnt<0>.Q BinCnt<3>.D 11.000
BinCnt<0>.Q BinCnt<4>.D 11.000
BinCnt<0>.Q BinCnt<5>.D 11.000
BinCnt<0>.Q BinCnt<6>.D 11.000
BinCnt<0>.Q BinCnt<7>.D 11.000
BinCnt<0>.Q OutSig.D 11.000
BinCnt<1>.Q BinCnt<0>.D 11.000
BinCnt<1>.Q BinCnt<1>.D 11.000
BinCnt<1>.Q BinCnt<2>.D 11.000
BinCnt<1>.Q BinCnt<3>.D 11.000
BinCnt<1>.Q BinCnt<4>.D 11.000
BinCnt<1>.Q BinCnt<5>.D 11.000
BinCnt<1>.Q BinCnt<6>.D 11.000
BinCnt<1>.Q BinCnt<7>.D 11.000
BinCnt<1>.Q OutSig.D 11.000
BinCnt<2>.Q BinCnt<0>.D 11.000
BinCnt<2>.Q BinCnt<1>.D 11.000
BinCnt<2>.Q BinCnt<2>.D 11.000
BinCnt<2>.Q BinCnt<3>.D 11.000
BinCnt<2>.Q BinCnt<4>.D 11.000
BinCnt<2>.Q BinCnt<5>.D 11.000
BinCnt<2>.Q BinCnt<6>.D 11.000
BinCnt<2>.Q BinCnt<7>.D 11.000
BinCnt<2>.Q OutSig.D 11.000
BinCnt<3>.Q BinCnt<0>.D 11.000
BinCnt<3>.Q BinCnt<1>.D 11.000
BinCnt<3>.Q BinCnt<2>.D 11.000
BinCnt<3>.Q BinCnt<3>.D 11.000
BinCnt<3>.Q BinCnt<4>.D 11.000
BinCnt<3>.Q BinCnt<5>.D 11.000
BinCnt<3>.Q BinCnt<6>.D 11.000
BinCnt<3>.Q BinCnt<7>.D 11.000
BinCnt<3>.Q OutSig.D 11.000
BinCnt<4>.Q BinCnt<0>.D 11.000
BinCnt<4>.Q BinCnt<1>.D 11.000
BinCnt<4>.Q BinCnt<2>.D 11.000
BinCnt<4>.Q BinCnt<3>.D 11.000
BinCnt<4>.Q BinCnt<4>.D 11.000
BinCnt<4>.Q BinCnt<5>.D 11.000
BinCnt<4>.Q BinCnt<6>.D 11.000
BinCnt<4>.Q BinCnt<7>.D 11.000
BinCnt<4>.Q OutSig.D 11.000
BinCnt<5>.Q BinCnt<0>.D 11.000
BinCnt<5>.Q BinCnt<1>.D 11.000
BinCnt<5>.Q BinCnt<2>.D 11.000
BinCnt<5>.Q BinCnt<3>.D 11.000
BinCnt<5>.Q BinCnt<4>.D 11.000
BinCnt<5>.Q BinCnt<5>.D 11.000
BinCnt<5>.Q BinCnt<6>.D 11.000
BinCnt<5>.Q BinCnt<7>.D 11.000
BinCnt<5>.Q OutSig.D 11.000
BinCnt<6>.Q BinCnt<0>.D 11.000
BinCnt<6>.Q BinCnt<1>.D 11.000
BinCnt<6>.Q BinCnt<2>.D 11.000
BinCnt<6>.Q BinCnt<3>.D 11.000
BinCnt<6>.Q BinCnt<4>.D 11.000
BinCnt<6>.Q BinCnt<5>.D 11.000
BinCnt<6>.Q BinCnt<6>.D 11.000
BinCnt<6>.Q BinCnt<7>.D 11.000
BinCnt<6>.Q OutSig.D 11.000
BinCnt<7>.Q BinCnt<0>.D 11.000
BinCnt<7>.Q BinCnt<1>.D 11.000
BinCnt<7>.Q BinCnt<2>.D 11.000
BinCnt<7>.Q BinCnt<3>.D 11.000
BinCnt<7>.Q BinCnt<4>.D 11.000
BinCnt<7>.Q BinCnt<5>.D 11.000
BinCnt<7>.Q BinCnt<6>.D 11.000
BinCnt<7>.Q BinCnt<7>.D 11.000
BinCnt<7>.Q OutSig.D 11.000
OutSig.Q BinCnt<0>.D 8.000
OutSig.Q BinCnt<1>.D 8.000
OutSig.Q BinCnt<2>.D 8.000
OutSig.Q BinCnt<3>.D 8.000
OutSig.Q BinCnt<4>.D 8.000
OutSig.Q BinCnt<5>.D 8.000
OutSig.Q BinCnt<6>.D 8.000
OutSig.Q BinCnt<7>.D 8.000
OutSig.Q OutSig.D 8.000
MuxDisplInstance/SelCnt<0>.Q MuxDisplInstance/SelCnt<1>.D 4.700


Pad to Pad List

Source Pad Destination Pad Delay
SpeedKeyInp SpeedLed 5.700



Number of paths analyzed: 612
Number of Timing errors: 612
Analysis Completed: Tue Mar 30 23:18:42 2010