Equations

********** Mapped Logic **********
FTCPE_ClkLED: FTCPE port map (ClkLED,ClkLED_T,NOT Clk,NOT Reset,'0','1');
     ClkLED_T <= (FDiv(0) AND FDiv(6) AND FDiv(1) AND FDiv(2) AND
      FDiv(3) AND FDiv(4) AND FDiv(5) AND FDiv(10) AND FDiv(7) AND
      FDiv(8) AND FDiv(9) AND FDiv(11) AND FDiv(12) AND FDiv(13));
FTCPE_Cnt0: FTCPE port map (Cnt(0),'0',ClkLED,NOT Reset,'0','1');
FTCPE_Cnt1: FTCPE port map (Cnt(1),Cnt(0),ClkLED,NOT Reset,'0','1');
FTCPE_Cnt2: FTCPE port map (Cnt(2),Cnt_T(2),ClkLED,NOT Reset,'0','1');
     Cnt_T(2) <= (Cnt(1) AND Cnt(0));
FTCPE_Cnt3: FTCPE port map (Cnt(3),Cnt_T(3),ClkLED,NOT Reset,'0','1');
     Cnt_T(3) <= (Cnt(1) AND Cnt(0) AND Cnt(2));
FTCPE_Cnt4: FTCPE port map (Cnt(4),Cnt_T(4),ClkLED,NOT Reset,'0','1');
     Cnt_T(4) <= (Cnt(1) AND Cnt(0) AND Cnt(2) AND Cnt(3));
FTCPE_Cnt5: FTCPE port map (Cnt(5),Cnt_T(5),ClkLED,NOT Reset,'0','1');
     Cnt_T(5) <= (Cnt(1) AND Cnt(0) AND Cnt(2) AND Cnt(3) AND Cnt(4));
FTCPE_Cnt6: FTCPE port map (Cnt(6),Cnt_T(6),ClkLED,NOT Reset,'0','1');
     Cnt_T(6) <= (Cnt(1) AND Cnt(0) AND Cnt(5) AND Cnt(2) AND Cnt(3) AND
      Cnt(4));
FTCPE_Cnt7: FTCPE port map (Cnt(7),Cnt_T(7),ClkLED,NOT Reset,'0','1');
     Cnt_T(7) <= (Cnt(1) AND Cnt(0) AND Cnt(5) AND Cnt(2) AND Cnt(3) AND
      Cnt(4) AND Cnt(6));
FTDCPE_CntDE0: FTDCPE port map (CntDE(0),'0',ClkLED,NOT Reset,'0','1');
FTDCPE_CntDE1: FTDCPE port map (CntDE(1),CntDE(0),ClkLED,NOT Reset,'0','1');
FTDCPE_CntDE2: FTDCPE port map (CntDE(2),CntDE_T(2),ClkLED,NOT Reset,'0','1');
     CntDE_T(2) <= (CntDE(0) AND CntDE(1));
FTDCPE_CntDE3: FTDCPE port map (CntDE(3),CntDE_T(3),ClkLED,NOT Reset,'0','1');
     CntDE_T(3) <= (CntDE(0) AND CntDE(1) AND CntDE(2));
FTDCPE_CntDE4: FTDCPE port map (CntDE(4),CntDE_T(4),ClkLED,NOT Reset,'0','1');
     CntDE_T(4) <= (CntDE(0) AND CntDE(1) AND CntDE(2) AND CntDE(3));
FTDCPE_CntDE5: FTDCPE port map (CntDE(5),CntDE_T(5),ClkLED,NOT Reset,'0','1');
     CntDE_T(5) <= (CntDE(0) AND CntDE(1) AND CntDE(2) AND CntDE(3) AND
      CntDE(4));
FTDCPE_CntDE6: FTDCPE port map (CntDE(6),CntDE_T(6),ClkLED,NOT Reset,'0','1');
     CntDE_T(6) <= (CntDE(5) AND CntDE(0) AND CntDE(1) AND CntDE(2) AND
      CntDE(3) AND CntDE(4));
FTDCPE_CntDE7: FTDCPE port map (CntDE(7),CntDE_T(7),ClkLED,NOT Reset,'0','1');
     CntDE_T(7) <= (CntDE(5) AND CntDE(0) AND CntDE(1) AND CntDE(2) AND
      CntDE(3) AND CntDE(4) AND CntDE(6));
DSel0 <= (NOT MuxDisplInstance/SelCnt(0) AND
      NOT MuxDisplInstance/SelCnt(1));
DSel1 <= (MuxDisplInstance/SelCnt(0) AND
      NOT MuxDisplInstance/SelCnt(1));
DSel2 <= (NOT MuxDisplInstance/SelCnt(0) AND
      MuxDisplInstance/SelCnt(1));
DSel3 <= (MuxDisplInstance/SelCnt(0) AND
      MuxDisplInstance/SelCnt(1));
FTCPE_FDiv0: FTCPE port map (FDiv(0),'0',NOT Clk,NOT Reset,'0','1');
FTCPE_FDiv1: FTCPE port map (FDiv(1),FDiv(0),NOT Clk,NOT Reset,'0','1');
FTCPE_FDiv2: FTCPE port map (FDiv(2),FDiv_T(2),NOT Clk,NOT Reset,'0','1');
     FDiv_T(2) <= (FDiv(0) AND FDiv(1));
FTCPE_FDiv3: FTCPE port map (FDiv(3),FDiv_T(3),NOT Clk,NOT Reset,'0','1');
     FDiv_T(3) <= (FDiv(0) AND FDiv(1) AND FDiv(2));
FTCPE_FDiv4: FTCPE port map (FDiv(4),FDiv_T(4),NOT Clk,NOT Reset,'0','1');
     FDiv_T(4) <= (FDiv(0) AND FDiv(1) AND FDiv(2) AND FDiv(3));
FTCPE_FDiv5: FTCPE port map (FDiv(5),FDiv_T(5),NOT Clk,NOT Reset,'0','1');
     FDiv_T(5) <= (FDiv(0) AND FDiv(1) AND FDiv(2) AND FDiv(3) AND
      FDiv(4));
FTCPE_FDiv6: FTCPE port map (FDiv(6),FDiv_T(6),NOT Clk,NOT Reset,'0','1');
     FDiv_T(6) <= (FDiv(0) AND FDiv(1) AND FDiv(2) AND FDiv(3) AND
      FDiv(4) AND FDiv(5));
FTCPE_FDiv7: FTCPE port map (FDiv(7),FDiv_T(7),NOT Clk,NOT Reset,'0','1');
     FDiv_T(7) <= (FDiv(0) AND FDiv(6) AND FDiv(1) AND FDiv(2) AND
      FDiv(3) AND FDiv(4) AND FDiv(5));
FTCPE_FDiv8: FTCPE port map (FDiv(8),FDiv_T(8),NOT Clk,NOT Reset,'0','1');
     FDiv_T(8) <= (FDiv(0) AND FDiv(6) AND FDiv(1) AND FDiv(2) AND
      FDiv(3) AND FDiv(4) AND FDiv(5) AND FDiv(7));
FTCPE_FDiv9: FTCPE port map (FDiv(9),FDiv_T(9),NOT Clk,NOT Reset,'0','1');
     FDiv_T(9) <= (FDiv(0) AND FDiv(6) AND FDiv(1) AND FDiv(2) AND
      FDiv(3) AND FDiv(4) AND FDiv(5) AND FDiv(7) AND FDiv(8));
FTCPE_FDiv10: FTCPE port map (FDiv(10),FDiv_T(10),NOT Clk,NOT Reset,'0','1');
     FDiv_T(10) <= (FDiv(0) AND FDiv(6) AND FDiv(1) AND FDiv(2) AND
      FDiv(3) AND FDiv(4) AND FDiv(5) AND FDiv(7) AND FDiv(8) AND
      FDiv(9));
FTCPE_FDiv11: FTCPE port map (FDiv(11),FDiv_T(11),NOT Clk,NOT Reset,'0','1');
     FDiv_T(11) <= (FDiv(0) AND FDiv(6) AND FDiv(1) AND FDiv(2) AND
      FDiv(3) AND FDiv(4) AND FDiv(5) AND FDiv(10) AND FDiv(7) AND
      FDiv(8) AND FDiv(9));
FTCPE_FDiv12: FTCPE port map (FDiv(12),FDiv_T(12),NOT Clk,NOT Reset,'0','1');
     FDiv_T(12) <= (FDiv(0) AND FDiv(6) AND FDiv(1) AND FDiv(2) AND
      FDiv(3) AND FDiv(4) AND FDiv(5) AND FDiv(10) AND FDiv(7) AND
      FDiv(8) AND FDiv(9) AND FDiv(11));
FTCPE_FDiv13: FTCPE port map (FDiv(13),FDiv_T(13),NOT Clk,NOT Reset,'0','1');
     FDiv_T(13) <= (FDiv(0) AND FDiv(6) AND FDiv(1) AND FDiv(2) AND
      FDiv(3) AND FDiv(4) AND FDiv(5) AND FDiv(10) AND FDiv(7) AND
      FDiv(8) AND FDiv(9) AND FDiv(11) AND FDiv(12));
FTCPE_MuxDisplInstance/SelCnt0: FTCPE port map (MuxDisplInstance/SelCnt(0),'0',FDiv(6),NOT Reset,'0','1');
FTCPE_MuxDisplInstance/SelCnt1: FTCPE port map (MuxDisplInstance/SelCnt(1),MuxDisplInstance/SelCnt(0),FDiv(6),NOT Reset,'0','1');
MuxDisplInstance/Tetr(0) <= ((Cnt(0) AND Seg_K)
      OR (CntDE(0) AND DSel0)
      OR (CntDE(4) AND DSel1)
      OR (Cnt(4) AND DSel3));
MuxDisplInstance/Tetr(1) <= ((Cnt(1) AND Seg_K)
      OR (CntDE(5) AND DSel1)
      OR (CntDE(1) AND DSel0)
      OR (Cnt(5) AND DSel3));
MuxDisplInstance/Tetr(2) <= ((Seg_K AND Cnt(2))
      OR (CntDE(2) AND DSel0)
      OR (DSel1 AND CntDE(6))
      OR (DSel3 AND Cnt(6)));
MuxDisplInstance/Tetr(3) <= ((Seg_K AND Cnt(3))
      OR (CntDE(3) AND DSel0)
      OR (DSel1 AND CntDE(7))
      OR (DSel3 AND Cnt(7)));
Seg_A <= NOT ((NOT MuxDisplInstance/Tetr(1) AND
      MuxDisplInstance/Tetr(0))
      XOR ((NOT MuxDisplInstance/Tetr(1) AND
      MuxDisplInstance/Tetr(2) AND NOT MuxDisplInstance/Tetr(3))
      OR (MuxDisplInstance/Tetr(0) AND
      NOT MuxDisplInstance/Tetr(2) AND MuxDisplInstance/Tetr(3))));
Seg_B <= NOT ((NOT MuxDisplInstance/Tetr(0) AND
      MuxDisplInstance/Tetr(2))
      XOR ((MuxDisplInstance/Tetr(1) AND
      MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(3))
      OR (NOT MuxDisplInstance/Tetr(1) AND
      MuxDisplInstance/Tetr(2) AND NOT MuxDisplInstance/Tetr(3))));
Seg_C <= NOT (((MuxDisplInstance/Tetr(1) AND
      MuxDisplInstance/Tetr(2) AND MuxDisplInstance/Tetr(3))
      OR (NOT MuxDisplInstance/Tetr(0) AND
      MuxDisplInstance/Tetr(2) AND MuxDisplInstance/Tetr(3))
      OR (MuxDisplInstance/Tetr(1) AND
      NOT MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(2) AND
      NOT MuxDisplInstance/Tetr(3))));
Seg_D <= NOT (((MuxDisplInstance/Tetr(1) AND
      MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(2))
      OR (MuxDisplInstance/Tetr(1) AND
      NOT MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(2) AND
      MuxDisplInstance/Tetr(3))
      OR (NOT MuxDisplInstance/Tetr(1) AND
      MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(2) AND
      NOT MuxDisplInstance/Tetr(3))
      OR (NOT MuxDisplInstance/Tetr(1) AND
      NOT MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(2) AND
      NOT MuxDisplInstance/Tetr(3))));
Seg_E <= NOT (((MuxDisplInstance/Tetr(0) AND
      NOT MuxDisplInstance/Tetr(3))
      OR (NOT MuxDisplInstance/Tetr(1) AND
      MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(2))
      OR (NOT MuxDisplInstance/Tetr(1) AND
      MuxDisplInstance/Tetr(2) AND NOT MuxDisplInstance/Tetr(3))));
Seg_F <= NOT ((MuxDisplInstance/Tetr(0) AND
      NOT MuxDisplInstance/Tetr(3))
      XOR ((NOT MuxDisplInstance/Tetr(1) AND
      MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(2))
      OR (MuxDisplInstance/Tetr(1) AND
      NOT MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(2) AND
      NOT MuxDisplInstance/Tetr(3))));
Seg_G <= NOT (((NOT MuxDisplInstance/Tetr(1) AND
      NOT MuxDisplInstance/Tetr(2) AND NOT MuxDisplInstance/Tetr(3))
      OR (MuxDisplInstance/Tetr(1) AND
      MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(2) AND
      NOT MuxDisplInstance/Tetr(3))
      OR (NOT MuxDisplInstance/Tetr(1) AND
      NOT MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(2) AND
      MuxDisplInstance/Tetr(3))));
Seg_K <= (NOT MuxDisplInstance/SelCnt(0) AND
      MuxDisplInstance/SelCnt(1));
Register Legend:
      FDCPE (Q,D,C,CLR,PRE,CE);
      FDDCPE (Q,D,C,CLR,PRE,CE);
      FTCPE (Q,D,C,CLR,PRE,CE);
      FTDCPE (Q,D,C,CLR,PRE,CE);
      LDCP (Q,D,G,CLR,PRE);