cpldfit: version J.36 Xilinx Inc. Fitter Report Design Name: PushCnt Date: 4-13-2009, 11:27PM Device Used: XC2C256-6-VQ100 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 49 /256 ( 19%) 86 /896 ( 10%) 76 /640 ( 12%) 31 /256 ( 12%) 18 /80 ( 22%) ** Function Block Resources ** Function Mcells FB Inps Pterms IO CTC CTR CTS CTE Block Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot FB1 16/16* 22/40 26/56 0/ 5 1/1* 1/1* 0/1 0/1 FB2 16/16* 13/40 24/56 6/ 6* 1/1* 1/1* 0/1 0/1 FB3 8/16 26/40 22/56 0/ 4 1/1* 1/1* 1/1* 0/1 FB4 2/16 4/40 5/56 2/ 6 0/1 0/1 0/1 0/1 FB5 0/16 0/40 0/56 0/ 2 0/1 0/1 0/1 0/1 FB6 2/16 2/40 2/56 2/ 5 0/1 0/1 0/1 0/1 FB7 4/16 7/40 5/56 4/ 6 1/1* 1/1* 0/1 0/1 FB8 0/16 0/40 0/56 0/ 6 0/1 0/1 0/1 0/1 FB9 0/16 0/40 0/56 0/ 5 0/1 0/1 0/1 0/1 FB10 0/16 0/40 0/56 0/ 7 0/1 0/1 0/1 0/1 FB11 0/16 0/40 0/56 0/ 4 0/1 0/1 0/1 0/1 FB12 0/16 0/40 0/56 0/ 4 0/1 0/1 0/1 0/1 FB13 1/16 2/40 2/56 0/ 4 1/1* 0/1 1/1* 0/1 FB14 0/16 0/40 0/56 0/ 5 0/1 0/1 0/1 0/1 FB15 0/16 0/40 0/56 0/ 6 0/1 0/1 0/1 0/1 FB16 0/16 0/40 0/56 0/ 5 0/1 0/1 0/1 0/1 ----- ------- ------- ----- --- --- --- --- Total 49/256 76/640 86/896 14/80 5/16 4/16 2/16 0/16 CTC - Control Term Clock CTR - Control Term Reset CTS - Control Term Set CTE - Control Term Output Enable * - Resource is exhausted ** Global Control Resources ** GCK GSR GTS Used/Tot Used/Tot Used/Tot 1/3 0/1 0/4 Signal 'Clk' mapped onto global clock net GCK0. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 3 3 | I/O : 11 70 Output : 14 14 | GCK/IO : 2 3 Bidirectional : 0 0 | GTS/IO : 4 4 GCK : 1 1 | GSR/IO : 0 1 GTS : 0 0 | CDR/IO : 1 1 GSR : 0 0 | DGE/IO : 0 1 ---- ---- Total 18 18 End of Mapped Resource Summary ************************* Summary of Mapped Logic ************************ ** 14 Outputs ** Signal Total Total Loc Pin Pin Pin I/O I/O Slew Reg Reg Init Name Pts Inps No. Type Use STD Style Rate Use State Seg_K 0 0 FB2_1 1 GTS/I/O O LVCMOS18 FAST Seg_G 3 4 FB2_3 2 GTS/I/O O LVCMOS18 FAST Seg_F 3 4 FB2_5 3 GTS/I/O O LVCMOS18 FAST Seg_E 3 4 FB2_12 4 GTS/I/O O LVCMOS18 FAST Seg_D 4 4 FB2_14 6 I/O O LVCMOS18 FAST Seg_C 3 4 FB2_15 7 I/O O LVCMOS18 FAST Seg_A 3 4 FB4_1 8 I/O O LVCMOS18 FAST Seg_B 3 4 FB4_2 9 I/O O LVCMOS18 FAST DSel2 1 2 FB6_2 24 CDR/I/O O LVCMOS18 FAST DSel3 1 2 FB6_4 27 GCK/I/O O LVCMOS18 FAST DSel1 1 2 FB7_5 19 I/O O LVCMOS18 FAST DSel0 1 2 FB7_6 18 I/O O LVCMOS18 FAST KeyLed 2 4 FB7_11 17 I/O O LVCMOS18 FAST LATCH RESET ModeLed 1 1 FB7_12 16 I/O O LVCMOS18 FAST ** 35 Buried Nodes ** Signal Total Total Loc Reg Reg Init Name Pts Inps Use State Cnt10<2> 3 8 FB1_1 TFF RESET Cnt100<0> 3 10 FB1_2 TFF RESET MuxDisplInstance/Tetr<0> 4 8 FB1_3 Cnt10<3> 4 10 FB1_4 TFF RESET Cnt10<1> 5 10 FB1_5 TFF RESET Cnt1<2> 3 4 FB1_6 TFF RESET Cnt100<2> 3 12 FB1_7 TFF RESET Cnt1000<0> 3 14 FB1_8 TFF RESET Cnt100<3> 4 14 FB1_9 TFF RESET Cnt100<1> 5 14 FB1_10 TFF RESET Cnt1000<2> 3 16 FB1_11 TFF RESET Cnt10<0> 3 6 FB1_12 TFF RESET Cnt1<3> 4 6 FB1_13 TFF RESET Cnt1<1> 4 6 FB1_14 TFF RESET Cnt1000<3> 4 18 FB1_15 TFF RESET Cnt1000<1> 5 18 FB1_16 TFF RESET MuxDisplInstance/SelCnt<0> 2 2 FB2_2 TFF RESET FDiv<4> 3 6 FB2_4 TFF RESET FDiv<3> 3 5 FB2_6 TFF RESET FDiv<2> 3 4 FB2_7 TFF RESET FDiv<1> 3 3 FB2_8 TFF RESET FDiv<0> 2 2 FB2_9 TFF RESET Cnt1<0> 2 2 FB2_10 TFF RESET FClk 2 3 FB2_11 TFF RESET FDivInstance/FDivCnt<1> 2 2 FB2_13 TFF RESET FDivInstance/FDivCnt<0> 1 1 FB2_16 TFF RESET MuxDisplInstance/SelCnt<1> 3 3 FB3_6 TFF RESET Key0Instance/ShRegister<3> 3 3 FB3_7 DFF RESET Key0Instance/ShRegister<2> 3 3 FB3_8 DFF RESET Key0Instance/ShRegister<1> 3 3 FB3_9 DFF RESET N_PZ_198 2 3 FB3_10 MuxDisplInstance/Tetr<3> 4 8 FB3_11 MuxDisplInstance/Tetr<2> 4 8 FB3_13 MuxDisplInstance/Tetr<1> 4 8 FB3_15 Key0Instance/ShRegister<0> 2 2 FB13_6 DFF RESET ** 4 Inputs ** Signal Loc Pin Pin Pin I/O I/O Name No. Type Use STD Style Clk FB5_6 22 GCK/I/O GCK LVCMOS18 KPR Reset FB12_15 65 I/O I LVCMOS18 KPR PushKeyIn FB13_6 55 I/O I LVCMOS18 KPR ModeSw FB14_5 49 I/O I LVCMOS18 KPR Legend: Pin No. - ~ - User Assigned I/O Style - OD - OpenDrain - PU - Pullup - KPR - Keeper - S - SchmittTrigger - DG - DataGate Reg Use - LATCH - Transparent latch - DFF - D-flip-flop - DEFF - D-flip-flop with clock enable - TFF - T-flip-flop - TDFF - Dual-edge-triggered T-flip-flop - DDFF - Dual-edge-triggered flip-flop - DDEFF - Dual-edge-triggered flip-flop with clock enable /S (after any above flop/latch type) indicates initial state is Set ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset VRF - Vref Pin No. - ~ - User Assigned *********************************** FB1 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 22/18 Number of function block control terms used/remaining: 2/2 Number of PLA product terms used/remaining: 26/30 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use Cnt10<2> 3 FB1_1 (b) (b) + + Cnt100<0> 3 FB1_2 (b) (b) + + MuxDisplInstance/Tetr<0> 4 FB1_3 99 GSR/I/O (b) Cnt10<3> 4 FB1_4 (b) (b) + + Cnt10<1> 5 FB1_5 (b) (b) + + Cnt1<2> 3 FB1_6 97 I/O (b) + + Cnt100<2> 3 FB1_7 (b) (b) + + Cnt1000<0> 3 FB1_8 (b) (b) + + Cnt100<3> 4 FB1_9 (b) (b) + + Cnt100<1> 5 FB1_10 (b) (b) + + Cnt1000<2> 3 FB1_11 (b) (b) + + Cnt10<0> 3 FB1_12 96 I/O (b) + + Cnt1<3> 4 FB1_13 95 I/O (b) + + Cnt1<1> 4 FB1_14 94 I/O (b) + + Cnt1000<3> 4 FB1_15 (b) (b) + + Cnt1000<1> 5 FB1_16 (b) (b) + + Signals Used by Logic in Function Block 1: Cnt1000<0> 9: Cnt10<0> 16: Cnt1<3> 2: Cnt1000<1> 10: Cnt10<1> 17: DSel0 3: Cnt1000<2> 11: Cnt10<2> 18: DSel1 4: Cnt1000<3> 12: Cnt10<3> 19: DSel2 5: Cnt100<0> 13: Cnt1<0> 20: DSel3 6: Cnt100<1> 14: Cnt1<1> 21: N_PZ_198 7: Cnt100<2> 15: Cnt1<2> 22: Reset 8: Cnt100<3> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs Cnt10<2> ........XX..XXXX....XX.................. 8 Cnt100<0> ........XXXXXXXX....XX.................. 10 MuxDisplInstance/Tetr<0> X...X...X...X...XXXX.................... 8 Cnt10<3> ........XXXXXXXX....XX.................. 10 Cnt10<1> ........XXXXXXXX....XX.................. 10 Cnt1<2> ............XX......XX.................. 4 Cnt100<2> ....XX..XXXXXXXX....XX.................. 12 Cnt1000<0> ....XXXXXXXXXXXX....XX.................. 14 Cnt100<3> ....XXXXXXXXXXXX....XX.................. 14 Cnt100<1> ....XXXXXXXXXXXX....XX.................. 14 Cnt1000<2> XX..XXXXXXXXXXXX....XX.................. 16 Cnt10<0> ............XXXX....XX.................. 6 Cnt1<3> ............XXXX....XX.................. 6 Cnt1<1> ............XXXX....XX.................. 6 Cnt1000<3> XXXXXXXXXXXXXXXX....XX.................. 18 Cnt1000<1> XXXXXXXXXXXXXXXX....XX.................. 18 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB2 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 13/27 Number of function block control terms used/remaining: 2/2 Number of PLA product terms used/remaining: 24/32 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use Seg_K 0 FB2_1 1 GTS/I/O O MuxDisplInstance/SelCnt<0> 2 FB2_2 (b) (b) + Seg_G 3 FB2_3 2 GTS/I/O O FDiv<4> 3 FB2_4 (b) (b) + + Seg_F 3 FB2_5 3 GTS/I/O O FDiv<3> 3 FB2_6 (b) (b) + + FDiv<2> 3 FB2_7 (b) (b) + + FDiv<1> 3 FB2_8 (b) (b) + + FDiv<0> 2 FB2_9 (b) (b) + + Cnt1<0> 2 FB2_10 (b) (b) + FClk 2 FB2_11 (b) (b) + Seg_E 3 FB2_12 4 GTS/I/O O FDivInstance/FDivCnt<1> 2 FB2_13 (b) (b) + Seg_D 4 FB2_14 6 I/O O Seg_C 3 FB2_15 7 I/O O FDivInstance/FDivCnt<0> 1 FB2_16 (b) (b) + Signals Used by Logic in Function Block 1: FClk 6: FDivInstance/FDivCnt<0> 10: MuxDisplInstance/Tetr<2> 2: FDiv<0> 7: FDivInstance/FDivCnt<1> 11: MuxDisplInstance/Tetr<3> 3: FDiv<1> 8: MuxDisplInstance/Tetr<0> 12: N_PZ_198 4: FDiv<2> 9: MuxDisplInstance/Tetr<1> 13: Reset 5: FDiv<3> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs Seg_K ........................................ 0 MuxDisplInstance/SelCnt<0> ....X.......X........................... 2 Seg_G .......XXXX............................. 4 FDiv<4> XXXXX.......X........................... 6 Seg_F .......XXXX............................. 4 FDiv<3> XXXX........X........................... 5 FDiv<2> XXX.........X........................... 4 FDiv<1> XX..........X........................... 3 FDiv<0> X...........X........................... 2 Cnt1<0> ...........XX........................... 2 FClk .....XX.....X........................... 3 Seg_E .......XXXX............................. 4 FDivInstance/FDivCnt<1> .....X......X........................... 2 Seg_D .......XXXX............................. 4 Seg_C .......XXXX............................. 4 FDivInstance/FDivCnt<0> ............X........................... 1 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB3 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 26/14 Number of function block control terms used/remaining: 3/1 Number of PLA product terms used/remaining: 22/34 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB3_1 (b) (unused) 0 FB3_2 (b) (unused) 0 FB3_3 (b) (unused) 0 FB3_4 (b) (unused) 0 FB3_5 93 I/O MuxDisplInstance/SelCnt<1> 3 FB3_6 (b) (b) + Key0Instance/ShRegister<3> 3 FB3_7 (b) (b) + + Key0Instance/ShRegister<2> 3 FB3_8 (b) (b) + + Key0Instance/ShRegister<1> 3 FB3_9 (b) (b) + + N_PZ_198 2 FB3_10 (b) (b) MuxDisplInstance/Tetr<3> 4 FB3_11 (b) (b) (unused) 0 FB3_12 92 I/O MuxDisplInstance/Tetr<2> 4 FB3_13 (b) (b) (unused) 0 FB3_14 91 I/O MuxDisplInstance/Tetr<1> 4 FB3_15 (b) (b) (unused) 0 FB3_16 90 I/O Signals Used by Logic in Function Block 1: Cnt1000<1> 10: Cnt1<1> 19: Key0Instance/ShRegister<0> 2: Cnt1000<2> 11: Cnt1<2> 20: Key0Instance/ShRegister<1> 3: Cnt1000<3> 12: Cnt1<3> 21: Key0Instance/ShRegister<2> 4: Cnt100<1> 13: DSel0 22: KeyLed 5: Cnt100<2> 14: DSel1 23: ModeSw 6: Cnt100<3> 15: DSel2 24: MuxDisplInstance/SelCnt<0> 7: Cnt10<1> 16: DSel3 25: PushKeyIn 8: Cnt10<2> 17: FDiv<3> 26: Reset 9: Cnt10<3> 18: FDiv<4> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs MuxDisplInstance/SelCnt<1> ................X......X.X.............. 3 Key0Instance/ShRegister<3> .................X..X....X.............. 3 Key0Instance/ShRegister<2> .................X.X.....X.............. 3 Key0Instance/ShRegister<1> .................XX......X.............. 3 N_PZ_198 .....................XX.X............... 3 MuxDisplInstance/Tetr<3> ..X..X..X..XXXXX........................ 8 MuxDisplInstance/Tetr<2> .X..X..X..X.XXXX........................ 8 MuxDisplInstance/Tetr<1> X..X..X..X..XXXX........................ 8 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB4 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 4/36 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 5/51 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use Seg_A 3 FB4_1 8 I/O O Seg_B 3 FB4_2 9 I/O O (unused) 0 FB4_3 10 I/O (unused) 0 FB4_4 (b) (unused) 0 FB4_5 11 I/O (unused) 0 FB4_6 12 I/O (unused) 0 FB4_7 (b) (unused) 0 FB4_8 (b) (unused) 0 FB4_9 (b) (unused) 0 FB4_10 (b) (unused) 0 FB4_11 (b) (unused) 0 FB4_12 (b) (unused) 0 FB4_13 13 I/O (unused) 0 FB4_14 (b) (unused) 0 FB4_15 (b) (unused) 0 FB4_16 (b) Signals Used by Logic in Function Block 1: MuxDisplInstance/Tetr<0> 3: MuxDisplInstance/Tetr<2> 4: MuxDisplInstance/Tetr<3> 2: MuxDisplInstance/Tetr<1> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs Seg_A XXXX.................................... 4 Seg_B XXXX.................................... 4 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB5 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB5_1 (b) (unused) 0 FB5_2 (b) (unused) 0 FB5_3 (b) (unused) 0 FB5_4 23 GCK/I/O (unused) 0 FB5_5 (b) (unused) 0 FB5_6 22 GCK/I/O GCK (unused) 0 FB5_7 (b) (unused) 0 FB5_8 (b) (unused) 0 FB5_9 (b) (unused) 0 FB5_10 (b) (unused) 0 FB5_11 (b) (unused) 0 FB5_12 (b) (unused) 0 FB5_13 (b) (unused) 0 FB5_14 (b) (unused) 0 FB5_15 (b) (unused) 0 FB5_16 (b) *********************************** FB6 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 2/38 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 2/54 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB6_1 (b) DSel2 1 FB6_2 24 CDR/I/O O (unused) 0 FB6_3 (b) DSel3 1 FB6_4 27 GCK/I/O O (unused) 0 FB6_5 (b) (unused) 0 FB6_6 (b) (unused) 0 FB6_7 (b) (unused) 0 FB6_8 (b) (unused) 0 FB6_9 (b) (unused) 0 FB6_10 (b) (unused) 0 FB6_11 (b) (unused) 0 FB6_12 28 DGE/I/O (unused) 0 FB6_13 (b) (unused) 0 FB6_14 29 I/O (unused) 0 FB6_15 (b) (unused) 0 FB6_16 30 I/O Signals Used by Logic in Function Block 1: MuxDisplInstance/SelCnt<0> 2: MuxDisplInstance/SelCnt<1> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs DSel2 XX...................................... 2 DSel3 XX...................................... 2 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB7 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 7/33 Number of function block control terms used/remaining: 2/2 Number of PLA product terms used/remaining: 5/51 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB7_1 (b) (unused) 0 FB7_2 (b) (unused) 0 FB7_3 (b) (unused) 0 FB7_4 (b) DSel1 1 FB7_5 19 I/O O DSel0 1 FB7_6 18 I/O O (unused) 0 FB7_7 (b) (unused) 0 FB7_8 (b) (unused) 0 FB7_9 (b) (unused) 0 FB7_10 (b) KeyLed 2 FB7_11 17 I/O O + + ModeLed 1 FB7_12 16 I/O O (unused) 0 FB7_13 15 I/O (unused) 0 FB7_14 14 I/O (unused) 0 FB7_15 (b) (unused) 0 FB7_16 (b) Signals Used by Logic in Function Block 1: Key0Instance/ShRegister<0> 4: Key0Instance/ShRegister<3> 6: MuxDisplInstance/SelCnt<0> 2: Key0Instance/ShRegister<1> 5: ModeSw 7: MuxDisplInstance/SelCnt<1> 3: Key0Instance/ShRegister<2> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs DSel1 .....XX................................. 2 DSel0 .....XX................................. 2 KeyLed XXXX.................................... 4 ModeLed ....X................................... 1 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB8 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB8_1 (b) (unused) 0 FB8_2 (b) (unused) 0 FB8_3 (b) (unused) 0 FB8_4 (b) (unused) 0 FB8_5 (b) (unused) 0 FB8_6 32 I/O (unused) 0 FB8_7 (b) (unused) 0 FB8_8 (b) (unused) 0 FB8_9 (b) (unused) 0 FB8_10 (b) (unused) 0 FB8_11 33 I/O (unused) 0 FB8_12 34 I/O (unused) 0 FB8_13 35 I/O (unused) 0 FB8_14 36 I/O (unused) 0 FB8_15 37 I/O (unused) 0 FB8_16 (b) *********************************** FB9 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB9_1 78 I/O (unused) 0 FB9_2 79 I/O (unused) 0 FB9_3 (b) (unused) 0 FB9_4 80 I/O (unused) 0 FB9_5 (b) (unused) 0 FB9_6 81 I/O (unused) 0 FB9_7 (b) (unused) 0 FB9_8 (b) (unused) 0 FB9_9 (b) (unused) 0 FB9_10 (b) (unused) 0 FB9_11 (b) (unused) 0 FB9_12 82 I/O (unused) 0 FB9_13 (b) (unused) 0 FB9_14 (b) (unused) 0 FB9_15 (b) (unused) 0 FB9_16 (b) *********************************** FB10 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB10_1 77 I/O (unused) 0 FB10_2 76 I/O (unused) 0 FB10_3 74 I/O (unused) 0 FB10_4 73 I/O (unused) 0 FB10_5 72 I/O (unused) 0 FB10_6 71 I/O (unused) 0 FB10_7 (b) (unused) 0 FB10_8 (b) (unused) 0 FB10_9 (b) (unused) 0 FB10_10 (b) (unused) 0 FB10_11 (b) (unused) 0 FB10_12 70 I/O (unused) 0 FB10_13 (b) (unused) 0 FB10_14 (b) (unused) 0 FB10_15 (b) (unused) 0 FB10_16 (b) *********************************** FB11 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB11_1 (b) (unused) 0 FB11_2 (b) (unused) 0 FB11_3 (b) (unused) 0 FB11_4 (b) (unused) 0 FB11_5 (b) (unused) 0 FB11_6 (b) (unused) 0 FB11_7 (b) (unused) 0 FB11_8 (b) (unused) 0 FB11_9 (b) (unused) 0 FB11_10 (b) (unused) 0 FB11_11 85 I/O (unused) 0 FB11_12 86 I/O (unused) 0 FB11_13 87 I/O (unused) 0 FB11_14 89 I/O (unused) 0 FB11_15 (b) (unused) 0 FB11_16 (b) *********************************** FB12 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB12_1 (b) (unused) 0 FB12_2 (b) (unused) 0 FB12_3 (b) (unused) 0 FB12_4 (b) (unused) 0 FB12_5 (b) (unused) 0 FB12_6 (b) (unused) 0 FB12_7 (b) (unused) 0 FB12_8 (b) (unused) 0 FB12_9 (b) (unused) 0 FB12_10 (b) (unused) 0 FB12_11 68 I/O (unused) 0 FB12_12 (b) (unused) 0 FB12_13 67 I/O (unused) 0 FB12_14 66 I/O (unused) 0 FB12_15 65 I/O I (unused) 0 FB12_16 (b) *********************************** FB13 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 2/38 Number of function block control terms used/remaining: 2/2 Number of PLA product terms used/remaining: 2/54 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB13_1 (b) (unused) 0 FB13_2 53 I/O (unused) 0 FB13_3 (b) (unused) 0 FB13_4 54 I/O (unused) 0 FB13_5 (b) Key0Instance/ShRegister<0> 2 FB13_6 55 I/O I + + (unused) 0 FB13_7 (b) (unused) 0 FB13_8 (b) (unused) 0 FB13_9 (b) (unused) 0 FB13_10 (b) (unused) 0 FB13_11 (b) (unused) 0 FB13_12 (b) (unused) 0 FB13_13 56 I/O (unused) 0 FB13_14 (b) (unused) 0 FB13_15 (b) (unused) 0 FB13_16 (b) Signals Used by Logic in Function Block 1: FDiv<4> 2: Reset Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB14 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB14_1 52 I/O (unused) 0 FB14_2 (b) (unused) 0 FB14_3 50 I/O (unused) 0 FB14_4 (b) (unused) 0 FB14_5 49 I/O I (unused) 0 FB14_6 (b) (unused) 0 FB14_7 (b) (unused) 0 FB14_8 (b) (unused) 0 FB14_9 (b) (unused) 0 FB14_10 (b) (unused) 0 FB14_11 (b) (unused) 0 FB14_12 (b) (unused) 0 FB14_13 (b) (unused) 0 FB14_14 46 I/O (unused) 0 FB14_15 44 I/O (unused) 0 FB14_16 (b) *********************************** FB15 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB15_1 (b) (unused) 0 FB15_2 (b) (unused) 0 FB15_3 (b) (unused) 0 FB15_4 (b) (unused) 0 FB15_5 (b) (unused) 0 FB15_6 (b) (unused) 0 FB15_7 (b) (unused) 0 FB15_8 (b) (unused) 0 FB15_9 (b) (unused) 0 FB15_10 (b) (unused) 0 FB15_11 58 I/O (unused) 0 FB15_12 59 I/O (unused) 0 FB15_13 60 I/O (unused) 0 FB15_14 61 I/O (unused) 0 FB15_15 63 I/O (unused) 0 FB15_16 64 I/O *********************************** FB16 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB16_1 (b) (unused) 0 FB16_2 (b) (unused) 0 FB16_3 (b) (unused) 0 FB16_4 (b) (unused) 0 FB16_5 43 I/O (unused) 0 FB16_6 42 I/O (unused) 0 FB16_7 (b) (unused) 0 FB16_8 (b) (unused) 0 FB16_9 (b) (unused) 0 FB16_10 (b) (unused) 0 FB16_11 41 I/O (unused) 0 FB16_12 40 I/O (unused) 0 FB16_13 39 I/O (unused) 0 FB16_14 (b) (unused) 0 FB16_15 (b) (unused) 0 FB16_16 (b) ******************************* Equations ******************************** ********** Mapped Logic ********** FTCPE_Cnt10000: FTCPE port map (Cnt1000(0),Cnt1000_T(0),N_PZ_198,NOT Reset,'0','1'); Cnt1000_T(0) <= (NOT Cnt100(1) AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(2) AND Cnt100(3)); FTCPE_Cnt10001: FTCPE port map (Cnt1000(1),Cnt1000_T(1),N_PZ_198,NOT Reset,'0','1'); Cnt1000_T(1) <= ((NOT Cnt100(1) AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(2) AND Cnt100(3) AND Cnt1000(1) AND Cnt1000(0)) OR (NOT Cnt100(1) AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(2) AND Cnt100(3) AND Cnt1000(0) AND Cnt1000(2)) OR (NOT Cnt100(1) AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(2) AND Cnt100(3) AND Cnt1000(0) AND NOT Cnt1000(3))); FTCPE_Cnt10002: FTCPE port map (Cnt1000(2),Cnt1000_T(2),N_PZ_198,NOT Reset,'0','1'); Cnt1000_T(2) <= (NOT Cnt100(1) AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(2) AND Cnt100(3) AND Cnt1000(1) AND Cnt1000(0)); FTCPE_Cnt10003: FTCPE port map (Cnt1000(3),Cnt1000_T(3),N_PZ_198,NOT Reset,'0','1'); Cnt1000_T(3) <= ((NOT Cnt100(1) AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(2) AND Cnt100(3) AND Cnt1000(1) AND Cnt1000(0) AND Cnt1000(2)) OR (NOT Cnt100(1) AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(2) AND Cnt100(3) AND NOT Cnt1000(1) AND Cnt1000(0) AND NOT Cnt1000(2) AND Cnt1000(3))); FTCPE_Cnt1000: FTCPE port map (Cnt100(0),Cnt100_T(0),N_PZ_198,NOT Reset,'0','1'); Cnt100_T(0) <= (Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3)); FTCPE_Cnt1001: FTCPE port map (Cnt100(1),Cnt100_T(1),N_PZ_198,NOT Reset,'0','1'); Cnt100_T(1) <= ((Cnt100(1) AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3)) OR (Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3) AND Cnt100(2)) OR (Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(3))); FTCPE_Cnt1002: FTCPE port map (Cnt100(2),Cnt100_T(2),N_PZ_198,NOT Reset,'0','1'); Cnt100_T(2) <= (Cnt100(1) AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3)); FTCPE_Cnt1003: FTCPE port map (Cnt100(3),Cnt100_T(3),N_PZ_198,NOT Reset,'0','1'); Cnt100_T(3) <= ((Cnt100(1) AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3) AND Cnt100(2)) OR (NOT Cnt100(1) AND Cnt100(0) AND Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3) AND NOT Cnt100(2) AND Cnt100(3))); FTCPE_Cnt100: FTCPE port map (Cnt10(0),Cnt10_T(0),N_PZ_198,NOT Reset,'0','1'); Cnt10_T(0) <= (Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3)); FTCPE_Cnt101: FTCPE port map (Cnt10(1),Cnt10_T(1),N_PZ_198,NOT Reset,'0','1'); Cnt10_T(1) <= ((Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND Cnt10(1)) OR (Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND Cnt10(2)) OR (Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(3))); FTCPE_Cnt102: FTCPE port map (Cnt10(2),Cnt10_T(2),N_PZ_198,NOT Reset,'0','1'); Cnt10_T(2) <= (Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND Cnt10(1)); FTCPE_Cnt103: FTCPE port map (Cnt10(3),Cnt10_T(3),N_PZ_198,NOT Reset,'0','1'); Cnt10_T(3) <= ((Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND Cnt10(1) AND Cnt10(2)) OR (Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND NOT Cnt10(2) AND Cnt10(3))); FTCPE_Cnt10: FTCPE port map (Cnt1(0),'0',N_PZ_198,NOT Reset,'0','1'); FTCPE_Cnt11: FTCPE port map (Cnt1(1),Cnt1_T(1),N_PZ_198,NOT Reset,'0','1'); Cnt1_T(1) <= NOT (((NOT Cnt1(0)) OR (NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3)))); FTCPE_Cnt12: FTCPE port map (Cnt1(2),Cnt1_T(2),N_PZ_198,NOT Reset,'0','1'); Cnt1_T(2) <= (Cnt1(0) AND Cnt1(1)); FTCPE_Cnt13: FTCPE port map (Cnt1(3),Cnt1_T(3),N_PZ_198,NOT Reset,'0','1'); Cnt1_T(3) <= ((Cnt1(0) AND Cnt1(1) AND Cnt1(2)) OR (Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3))); DSel0 <= (NOT MuxDisplInstance/SelCnt(0) AND NOT MuxDisplInstance/SelCnt(1)); DSel1 <= (MuxDisplInstance/SelCnt(0) AND NOT MuxDisplInstance/SelCnt(1)); DSel2 <= (NOT MuxDisplInstance/SelCnt(0) AND MuxDisplInstance/SelCnt(1)); DSel3 <= (MuxDisplInstance/SelCnt(0) AND MuxDisplInstance/SelCnt(1)); FTCPE_FClk: FTCPE port map (FClk,FClk_T,NOT Clk,NOT Reset,'0','1'); FClk_T <= (FDivInstance/FDivCnt(0) AND FDivInstance/FDivCnt(1)); FTCPE_FDiv0: FTCPE port map (FDiv(0),'0',FClk,NOT Reset,'0','1'); FTCPE_FDiv1: FTCPE port map (FDiv(1),FDiv(0),FClk,NOT Reset,'0','1'); FTCPE_FDiv2: FTCPE port map (FDiv(2),FDiv_T(2),FClk,NOT Reset,'0','1'); FDiv_T(2) <= (FDiv(0) AND FDiv(1)); FTCPE_FDiv3: FTCPE port map (FDiv(3),FDiv_T(3),FClk,NOT Reset,'0','1'); FDiv_T(3) <= (FDiv(0) AND FDiv(1) AND FDiv(2)); FTCPE_FDiv4: FTCPE port map (FDiv(4),FDiv_T(4),FClk,NOT Reset,'0','1'); FDiv_T(4) <= (FDiv(3) AND FDiv(0) AND FDiv(1) AND FDiv(2)); FTCPE_FDivInstance/FDivCnt0: FTCPE port map (FDivInstance/FDivCnt(0),'0',NOT Clk,NOT Reset,'0','1'); FTCPE_FDivInstance/FDivCnt1: FTCPE port map (FDivInstance/FDivCnt(1),FDivInstance/FDivCnt(0),NOT Clk,NOT Reset,'0','1'); FDCPE_Key0Instance/ShRegister0: FDCPE port map (Key0Instance/ShRegister(0),PushKeyIn,FDiv(4),'0',NOT Reset,'1'); FDCPE_Key0Instance/ShRegister1: FDCPE port map (Key0Instance/ShRegister(1),Key0Instance/ShRegister(0),FDiv(4),'0',NOT Reset,'1'); FDCPE_Key0Instance/ShRegister2: FDCPE port map (Key0Instance/ShRegister(2),Key0Instance/ShRegister(1),FDiv(4),'0',NOT Reset,'1'); FDCPE_Key0Instance/ShRegister3: FDCPE port map (Key0Instance/ShRegister(3),Key0Instance/ShRegister(2),FDiv(4),'0',NOT Reset,'1'); LDCP_KeyLed: LDCP port map (KeyLed,NOT '0',,KeyLed_CLR,'0'); KeyLed_G <= (NOT Key0Instance/ShRegister(0) AND NOT Key0Instance/ShRegister(1) AND NOT Key0Instance/ShRegister(2) AND NOT Key0Instance/ShRegister(3)); KeyLed_CLR <= (Key0Instance/ShRegister(0) AND Key0Instance/ShRegister(1) AND Key0Instance/ShRegister(2) AND Key0Instance/ShRegister(3)); ModeLed <= ModeSw; FTCPE_MuxDisplInstance/SelCnt0: FTCPE port map (MuxDisplInstance/SelCnt(0),'0',FDiv(3),NOT Reset,'0','1'); FTCPE_MuxDisplInstance/SelCnt1: FTCPE port map (MuxDisplInstance/SelCnt(1),MuxDisplInstance/SelCnt(0),FDiv(3),NOT Reset,'0','1'); MuxDisplInstance/Tetr(0) <= ((Cnt100(0) AND DSel2) OR (Cnt10(0) AND DSel1) OR (Cnt1(0) AND DSel0) OR (Cnt1000(0) AND DSel3)); MuxDisplInstance/Tetr(1) <= ((Cnt100(1) AND DSel2) OR (Cnt1(1) AND DSel0) OR (Cnt10(1) AND DSel1) OR (Cnt1000(1) AND DSel3)); MuxDisplInstance/Tetr(2) <= ((Cnt1(2) AND DSel0) OR (Cnt10(2) AND DSel1) OR (Cnt100(2) AND DSel2) OR (Cnt1000(2) AND DSel3)); MuxDisplInstance/Tetr(3) <= ((Cnt1(3) AND DSel0) OR (Cnt10(3) AND DSel1) OR (Cnt100(3) AND DSel2) OR (Cnt1000(3) AND DSel3)); N_PZ_198 <= ((ModeSw AND KeyLed) OR (NOT ModeSw AND NOT PushKeyIn)); Seg_A <= NOT ((NOT MuxDisplInstance/Tetr(1) AND MuxDisplInstance/Tetr(0)) XOR ((NOT MuxDisplInstance/Tetr(1) AND MuxDisplInstance/Tetr(2) AND NOT MuxDisplInstance/Tetr(3)) OR (MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(2) AND MuxDisplInstance/Tetr(3)))); Seg_B <= NOT ((NOT MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(2)) XOR ((MuxDisplInstance/Tetr(1) AND MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(3)) OR (NOT MuxDisplInstance/Tetr(1) AND MuxDisplInstance/Tetr(2) AND NOT MuxDisplInstance/Tetr(3)))); Seg_C <= NOT (((MuxDisplInstance/Tetr(1) AND MuxDisplInstance/Tetr(2) AND MuxDisplInstance/Tetr(3)) OR (NOT MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(2) AND MuxDisplInstance/Tetr(3)) OR (MuxDisplInstance/Tetr(1) AND NOT MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(2) AND NOT MuxDisplInstance/Tetr(3)))); Seg_D <= NOT (((MuxDisplInstance/Tetr(1) AND MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(2)) OR (MuxDisplInstance/Tetr(1) AND NOT MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(2) AND MuxDisplInstance/Tetr(3)) OR (NOT MuxDisplInstance/Tetr(1) AND MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(2) AND NOT MuxDisplInstance/Tetr(3)) OR (NOT MuxDisplInstance/Tetr(1) AND NOT MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(2) AND NOT MuxDisplInstance/Tetr(3)))); Seg_E <= NOT (((MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(3)) OR (NOT MuxDisplInstance/Tetr(1) AND MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(2)) OR (NOT MuxDisplInstance/Tetr(1) AND MuxDisplInstance/Tetr(2) AND NOT MuxDisplInstance/Tetr(3)))); Seg_F <= NOT ((MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(3)) XOR ((NOT MuxDisplInstance/Tetr(1) AND MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(2)) OR (MuxDisplInstance/Tetr(1) AND NOT MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(2) AND NOT MuxDisplInstance/Tetr(3)))); Seg_G <= NOT (((NOT MuxDisplInstance/Tetr(1) AND NOT MuxDisplInstance/Tetr(2) AND NOT MuxDisplInstance/Tetr(3)) OR (MuxDisplInstance/Tetr(1) AND MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(2) AND NOT MuxDisplInstance/Tetr(3)) OR (NOT MuxDisplInstance/Tetr(1) AND NOT MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(2) AND MuxDisplInstance/Tetr(3)))); Seg_K <= '0'; Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FDDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); FTDCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC2C256-6-VQ100 -------------------------------------------------- /100 98 96 94 92 90 88 86 84 82 80 78 76 \ | 99 97 95 93 91 89 87 85 83 81 79 77 | | 1 75 | | 2 74 | | 3 73 | | 4 72 | | 5 71 | | 6 70 | | 7 69 | | 8 68 | | 9 67 | | 10 66 | | 11 65 | | 12 64 | | 13 XC2C256-6-VQ100 63 | | 14 62 | | 15 61 | | 16 60 | | 17 59 | | 18 58 | | 19 57 | | 20 56 | | 21 55 | | 22 54 | | 23 53 | | 24 52 | | 25 51 | | 27 29 31 33 35 37 39 41 43 45 47 49 | \26 28 30 32 34 36 38 40 42 44 46 48 50 / -------------------------------------------------- Pin Signal Pin Signal No. Name No. Name 1 Seg_K 51 VCCIO-1.8 2 Seg_G 52 PGND 3 Seg_F 53 PGND 4 Seg_E 54 PGND 5 VCCAUX 55 PushKeyIn 6 Seg_D 56 PGND 7 Seg_C 57 VCC 8 Seg_A 58 PGND 9 Seg_B 59 PGND 10 PGND 60 PGND 11 PGND 61 PGND 12 PGND 62 GND 13 PGND 63 PGND 14 PGND 64 PGND 15 PGND 65 Reset 16 ModeLed 66 PGND 17 KeyLed 67 PGND 18 DSel0 68 PGND 19 DSel1 69 GND 20 VCCIO-1.8 70 PGND 21 GND 71 PGND 22 Clk 72 PGND 23 PGND 73 PGND 24 DSel2 74 PGND 25 GND 75 GND 26 VCC 76 PGND 27 DSel3 77 PGND 28 PGND 78 PGND 29 PGND 79 PGND 30 PGND 80 PGND 31 GND 81 PGND 32 PGND 82 PGND 33 PGND 83 TDO 34 PGND 84 GND 35 PGND 85 PGND 36 PGND 86 PGND 37 PGND 87 PGND 38 VCCIO-1.8 88 VCCIO-1.8 39 PGND 89 PGND 40 PGND 90 PGND 41 PGND 91 PGND 42 PGND 92 PGND 43 PGND 93 PGND 44 PGND 94 PGND 45 TDI 95 PGND 46 PGND 96 PGND 47 TMS 97 PGND 48 TCK 98 VCCIO-1.8 49 ModeSw 99 PGND 50 PGND 100 GND Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin KPR = Unused I/O with weak keeper (leave unconnected) WPU = Unused I/O with weak pull up (leave unconnected) TIE = Unused I/O floating -- must tie to VCC, GND or other signal VCC = Dedicated Power Pin VCCAUX = Power supply for JTAG pins VCCIO-3.3 = I/O supply voltage for LVTTL, LVCMOS33, SSTL3_I VCCIO-2.5 = I/O supply voltage for LVCMOS25, SSTL2_I VCCIO-1.8 = I/O supply voltage for LVCMOS18 VCCIO-1.5 = I/O supply voltage for LVCMOS15, HSTL_I VREF = Reference voltage for indicated input standard *VREF = Reference voltage pin selected by software GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc2c256-6-VQ100 Optimization Method : DENSITY Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Set Unused I/O Pin Termination : GROUND Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Enable Input Registers : ON Function Block Fan-in Limit : 38 Use DATA_GATE Attribute : ON Set Tristate Outputs to Termination Mode : KEEPER Default Voltage Standard for All Outputs : LVCMOS18 Input Limit : 32 Pterm Limit : 28