cpldfit:  version J.36                              Xilinx Inc.
                                  Fitter Report
Design Name: DispLCD                             Date:  5-24-2009, 11:24PM
Device Used: XC2C256-6-VQ100
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
56 /256 ( 22%) 144 /896  ( 16%) 77  /640  ( 12%) 32 /256 ( 12%) 19 /80  ( 24%)

** Function Block Resources **

Function Mcells   FB Inps  Pterms   IO       CTC      CTR      CTS      CTE     
Block    Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot
FB1      16/16*    16/40    15/56     0/ 5    1/1*     1/1*     0/1      0/1
FB2      16/16*    17/40    51/56     6/ 6*   1/1*     1/1*     0/1      0/1
FB3      13/16     11/40    24/56     0/ 4    1/1*     1/1*     0/1      0/1
FB4       5/16     15/40    25/56     5/ 6    0/1      0/1      0/1      0/1
FB5       0/16      0/40     0/56     0/ 2    0/1      0/1      0/1      0/1
FB6       1/16      8/40     3/56     1/ 5    1/1*     1/1*     0/1      0/1
FB7       5/16     10/40    26/56     5/ 6    0/1      0/1      0/1      0/1
FB8       0/16      0/40     0/56     0/ 6    0/1      0/1      0/1      0/1
FB9       0/16      0/40     0/56     0/ 5    0/1      0/1      0/1      0/1
FB10      0/16      0/40     0/56     0/ 7    0/1      0/1      0/1      0/1
FB11      0/16      0/40     0/56     0/ 4    0/1      0/1      0/1      0/1
FB12      0/16      0/40     0/56     0/ 4    0/1      0/1      0/1      0/1
FB13      0/16      0/40     0/56     0/ 4    0/1      0/1      0/1      0/1
FB14      0/16      0/40     0/56     0/ 5    0/1      0/1      0/1      0/1
FB15      0/16      0/40     0/56     0/ 6    0/1      0/1      0/1      0/1
FB16      0/16      0/40     0/56     0/ 5    0/1      0/1      0/1      0/1
         -----    -------  -------   -----    ---      ---      ---      ---
Total    56/256    77/640  144/896   17/80    4/16     4/16     0/16     0/16

CTC - Control Term Clock
CTR - Control Term Reset
CTS - Control Term Set
CTE - Control Term Output Enable

* - Resource is exhausted

** Global Control Resources **

GCK         GSR         GTS         
Used/Tot    Used/Tot    Used/Tot    
1/3         0/1         0/4

Signal 'Clk' mapped onto global clock net GCK0.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :    1           1    |  I/O              :    13     70
Output        :   17          17    |  GCK/IO           :     2      3
Bidirectional :    0           0    |  GTS/IO           :     4      4
GCK           :    1           1    |  GSR/IO           :     0      1
GTS           :    0           0    |  CDR/IO           :     0      1
GSR           :    0           0    |  DGE/IO           :     0      1
                 ----        ----
        Total     19          19

End of Mapped Resource Summary
*************************  Summary of Mapped Logic  ************************

** 17 Outputs **

Signal                      Total Total Loc     Pin   Pin       Pin     I/O      I/O       Slew Reg     Reg Init
Name                        Pts   Inps          No.   Type      Use     STD      Style     Rate Use     State
LCD10_A                     7     9     FB2_1   1     GTS/I/O   O       LVCMOS18           FAST         
LCD10_B                     6     7     FB2_3   2     GTS/I/O   O       LVCMOS18           FAST         
LCD10_C                     6     9     FB2_5   3     GTS/I/O   O       LVCMOS18           FAST         
LCD10_D                     6     8     FB2_12  4     GTS/I/O   O       LVCMOS18           FAST         
LCD10_E                     5     8     FB2_14  6     I/O       O       LVCMOS18           FAST         
LCD10_F                     6     9     FB2_15  7     I/O       O       LVCMOS18           FAST         
LCD10_G                     7     7     FB4_1   8     I/O       O       LVCMOS18           FAST         
LCD10_DP                    2     2     FB4_2   9     I/O       O       LVCMOS18           FAST         
LCD1_A                      6     7     FB4_3   10    I/O       O       LVCMOS18           FAST         
LCD1_B                      5     7     FB4_5   11    I/O       O       LVCMOS18           FAST         
LCD1_C                      5     8     FB4_13  13    I/O       O       LVCMOS18           FAST         
LCD_BP                      3     8     FB6_4   27    GCK/I/O   O       LVCMOS18           FAST TFF     RESET
LCD1_DP                     2     2     FB7_6   18    I/O       O       LVCMOS18           FAST         
LCD1_G                      6     7     FB7_11  17    I/O       O       LVCMOS18           FAST         
LCD1_F                      6     9     FB7_12  16    I/O       O       LVCMOS18           FAST         
LCD1_E                      6     8     FB7_13  15    I/O       O       LVCMOS18           FAST         
LCD1_D                      6     8     FB7_14  14    I/O       O       LVCMOS18           FAST         

** 39 Buried Nodes **

Signal                      Total Total Loc     Reg     Reg Init
Name                        Pts   Inps          Use     State
FDiv<0>                     2     2     FB1_1   TFF     RESET
FDiv<1>                     3     3     FB1_2   TFF     RESET
LCDMuxInstance/RegLCD10<0>  3     3     FB1_3   DFF     RESET
FDiv<2>                     3     4     FB1_4   TFF     RESET
FDiv<3>                     3     5     FB1_5   TFF     RESET
FClk                        2     3     FB1_6   TFF     RESET
FDiv<4>                     3     6     FB1_7   TFF     RESET
FDiv<5>                     3     7     FB1_8   TFF     RESET
FDiv<7>                     3     9     FB1_9   TFF     RESET
FDiv<8>                     3     10    FB1_10  TFF     RESET
FDiv<9>                     3     11    FB1_11  TFF     RESET
FDivInstance/FDivCnt<1>     2     2     FB1_12  TFF     RESET
LCDMuxInstance/DotReg<0>    2     2     FB1_13  DFF     RESET
FDivInstance/FDivCnt<0>     1     1     FB1_14  TFF     RESET
FDiv<10>                    3     12    FB1_15  TFF     RESET
FDiv<11>                    3     13    FB1_16  TFF     RESET
Cnt1<2>                     3     4     FB2_2   TFF     RESET
Cnt1<0>                     2     2     FB2_4   TFF     RESET
N_PZ_286                    1     2     FB2_6           
N_PZ_310                    2     3     FB2_7           
N_PZ_288                    2     2     FB2_8           
N_PZ_314                    2     2     FB2_9           
N_PZ_287                    2     2     FB2_10          
N_PZ_285                    1     2     FB2_11          
N_PZ_305                    2     3     FB2_13          
N_PZ_289                    2     4     FB2_16          
LCDMuxInstance/RegLCD1<2>   3     3     FB3_1   DFF     RESET
LCDMuxInstance/RegLCD1<1>   3     3     FB3_2   DFF     RESET
LCDMuxInstance/RegLCD1<0>   3     3     FB3_3   DFF     RESET
LCDMuxInstance/RegLCD10<3>  3     3     FB3_4   DFF     RESET
LCDMuxInstance/RegLCD10<2>  3     3     FB3_6   DFF     RESET
LCDMuxInstance/RegLCD10<1>  3     3     FB3_7   DFF     RESET
Cnt1<1>                     4     6     FB3_8   TFF     RESET
Cnt1<3>                     4     6     FB3_9   TFF     RESET
Cnt10<0>                    3     6     FB3_10  TFF     RESET
Cnt10<2>                    3     8     FB3_11  TFF     RESET
Cnt10<3>                    4     10    FB3_13  TFF     RESET
Cnt10<1>                    5     10    FB3_15  TFF     RESET
LCDMuxInstance/RegLCD1<3>   3     3     FB3_16  DFF     RESET

** 2 Inputs **

Signal                      Loc     Pin   Pin       Pin     I/O      I/O
Name                                No.   Type      Use     STD      Style
Clk                         FB5_6   22    GCK/I/O   GCK     LVCMOS18 KPR
Reset                       FB12_15 65    I/O       I       LVCMOS18 KPR

Legend:
Pin No.   - ~     - User Assigned
I/O Style - OD    - OpenDrain
          - PU    - Pullup
          - KPR   - Keeper
          - S     - SchmittTrigger
          - DG    - DataGate
Reg Use   - LATCH - Transparent latch
          - DFF   - D-flip-flop
          - DEFF  - D-flip-flop with clock enable
          - TFF   - T-flip-flop
          - TDFF  - Dual-edge-triggered T-flip-flop
          - DDFF  - Dual-edge-triggered flip-flop
          - DDEFF - Dual-edge-triggered flip-flop with clock enable
          /S (after any above flop/latch type) indicates initial state is Set
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
              VRF - Vref
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               16/24
Number of function block control terms used/remaining:        2/2
Number of PLA product terms used/remaining:                   15/41
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
FDiv<0>                       2     FB1_1        (b)     (b)    +   +      
FDiv<1>                       3     FB1_2        (b)     (b)    +   +      
LCDMuxInstance/RegLCD10<0>    3     FB1_3   99   GSR/I/O (b)    +   +      
FDiv<2>                       3     FB1_4        (b)     (b)    +   +      
FDiv<3>                       3     FB1_5        (b)     (b)    +   +      
FClk                          2     FB1_6   97   I/O     (b)        +      
FDiv<4>                       3     FB1_7        (b)     (b)    +   +      
FDiv<5>                       3     FB1_8        (b)     (b)    +   +      
FDiv<7>                       3     FB1_9        (b)     (b)    +   +      
FDiv<8>                       3     FB1_10       (b)     (b)    +   +      
FDiv<9>                       3     FB1_11       (b)     (b)    +   +      
FDivInstance/FDivCnt<1>       2     FB1_12  96   I/O     (b)        +      
LCDMuxInstance/DotReg<0>      2     FB1_13  95   I/O     (b)    +   +      
FDivInstance/FDivCnt<0>       1     FB1_14  94   I/O     (b)        +      
FDiv<10>                      3     FB1_15       (b)     (b)    +   +      
FDiv<11>                      3     FB1_16       (b)     (b)    +   +      

Signals Used by Logic in Function Block
  1: Cnt10<0>           7: FDiv<3>           12: FDiv<9> 
  2: FClk               8: FDiv<4>           13: FDivInstance/FDivCnt<0> 
  3: FDiv<0>            9: FDiv<5>           14: FDivInstance/FDivCnt<1> 
  4: FDiv<10>          10: FDiv<7>           15: LCD_BP 
  5: FDiv<1>           11: FDiv<8>           16: Reset 
  6: FDiv<2>          

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
FDiv<0>           .X.............X........................ 2       
FDiv<1>           .XX............X........................ 3       
LCDMuxInstance/RegLCD10<0> 
                  XX.............X........................ 3       
FDiv<2>           .XX.X..........X........................ 4       
FDiv<3>           .XX.XX.........X........................ 5       
FClk              ............XX.X........................ 3       
FDiv<4>           .XX.XXX........X........................ 6       
FDiv<5>           .XX.XXXX.......X........................ 7       
FDiv<7>           .XX.XXXXX.....XX........................ 9       
FDiv<8>           .XX.XXXXXX....XX........................ 10      
FDiv<9>           .XX.XXXXXXX...XX........................ 11      
FDivInstance/FDivCnt<1> 
                  ............X..X........................ 2       
LCDMuxInstance/DotReg<0> 
                  .X.............X........................ 2       
FDivInstance/FDivCnt<0> 
                  ...............X........................ 1       
FDiv<10>          .XX.XXXXXXXX..XX........................ 12      
FDiv<11>          .XXXXXXXXXXX..XX........................ 13      
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB2  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               17/23
Number of function block control terms used/remaining:        2/2
Number of PLA product terms used/remaining:                   51/5
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
LCD10_A                       7     FB2_1   1    GTS/I/O O                 
Cnt1<2>                       3     FB2_2        (b)     (b)    +   +      
LCD10_B                       6     FB2_3   2    GTS/I/O O                 
Cnt1<0>                       2     FB2_4        (b)     (b)    +   +      
LCD10_C                       6     FB2_5   3    GTS/I/O O                 
N_PZ_286                      1     FB2_6        (b)     (b)               
N_PZ_310                      2     FB2_7        (b)     (b)               
N_PZ_288                      2     FB2_8        (b)     (b)               
N_PZ_314                      2     FB2_9        (b)     (b)               
N_PZ_287                      2     FB2_10       (b)     (b)               
N_PZ_285                      1     FB2_11       (b)     (b)               
LCD10_D                       6     FB2_12  4    GTS/I/O O                 
N_PZ_305                      2     FB2_13       (b)     (b)               
LCD10_E                       5     FB2_14  6    I/O     O                 
LCD10_F                       6     FB2_15  7    I/O     O                 
N_PZ_289                      2     FB2_16       (b)     (b)               

Signals Used by Logic in Function Block
  1: Cnt1<0>                      7: LCDMuxInstance/RegLCD10<3>  13: N_PZ_285 
  2: Cnt1<1>                      8: LCDMuxInstance/RegLCD1<0>   14: N_PZ_287 
  3: FDiv<11>                     9: LCDMuxInstance/RegLCD1<1>   15: N_PZ_289 
  4: LCDMuxInstance/RegLCD10<0>  10: LCDMuxInstance/RegLCD1<2>   16: N_PZ_305 
  5: LCDMuxInstance/RegLCD10<1>  11: LCDMuxInstance/RegLCD1<3>   17: Reset 
  6: LCDMuxInstance/RegLCD10<2>  12: LCD_BP                     

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
LCD10_A           ...XXXX....XXXXX........................ 9       
Cnt1<2>           XXX.............X....................... 4       
LCD10_B           ...X.XX....XX.XX........................ 7       
Cnt1<0>           ..X.............X....................... 2       
LCD10_C           ...XXXX....XXXXX........................ 9       
N_PZ_286          ........X.X............................. 2       
N_PZ_310          .......XX.X............................. 3       
N_PZ_288          .......X.X.............................. 2       
N_PZ_314          .........X.X............................ 2       
N_PZ_287          ...X.X.................................. 2       
N_PZ_285          ....X.X................................. 2       
LCD10_D           ...XX.X....XXXXX........................ 8       
N_PZ_305          ...XX.X................................. 3       
LCD10_E           ...XX.X....XXXXX........................ 8       
LCD10_F           ...XXXX....XXXXX........................ 9       
N_PZ_289          ....XXX.....X........................... 4       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB3  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               11/29
Number of function block control terms used/remaining:        2/2
Number of PLA product terms used/remaining:                   24/32
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
LCDMuxInstance/RegLCD1<2>     3     FB3_1        (b)     (b)    +   +      
LCDMuxInstance/RegLCD1<1>     3     FB3_2        (b)     (b)    +   +      
LCDMuxInstance/RegLCD1<0>     3     FB3_3        (b)     (b)    +   +      
LCDMuxInstance/RegLCD10<3>    3     FB3_4        (b)     (b)    +   +      
(unused)                      0     FB3_5   93   I/O           
LCDMuxInstance/RegLCD10<2>    3     FB3_6        (b)     (b)    +   +      
LCDMuxInstance/RegLCD10<1>    3     FB3_7        (b)     (b)    +   +      
Cnt1<1>                       4     FB3_8        (b)     (b)        +      
Cnt1<3>                       4     FB3_9        (b)     (b)        +      
Cnt10<0>                      3     FB3_10       (b)     (b)        +      
Cnt10<2>                      3     FB3_11       (b)     (b)        +      
(unused)                      0     FB3_12  92   I/O           
Cnt10<3>                      4     FB3_13       (b)     (b)        +      
(unused)                      0     FB3_14  91   I/O           
Cnt10<1>                      5     FB3_15       (b)     (b)        +      
LCDMuxInstance/RegLCD1<3>     3     FB3_16  90   I/O     (b)    +   +      

Signals Used by Logic in Function Block
  1: Cnt10<0>           5: Cnt1<0>            9: FClk 
  2: Cnt10<1>           6: Cnt1<1>           10: FDiv<11> 
  3: Cnt10<2>           7: Cnt1<2>           11: Reset 
  4: Cnt10<3>           8: Cnt1<3>          

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
LCDMuxInstance/RegLCD1<2> 
                  ......X.X.X............................. 3       
LCDMuxInstance/RegLCD1<1> 
                  .....X..X.X............................. 3       
LCDMuxInstance/RegLCD1<0> 
                  ....X...X.X............................. 3       
LCDMuxInstance/RegLCD10<3> 
                  ...X....X.X............................. 3       
LCDMuxInstance/RegLCD10<2> 
                  ..X.....X.X............................. 3       
LCDMuxInstance/RegLCD10<1> 
                  .X......X.X............................. 3       
Cnt1<1>           ....XXXX.XX............................. 6       
Cnt1<3>           ....XXXX.XX............................. 6       
Cnt10<0>          ....XXXX.XX............................. 6       
Cnt10<2>          XX..XXXX.XX............................. 8       
Cnt10<3>          XXXXXXXX.XX............................. 10      
Cnt10<1>          XXXXXXXX.XX............................. 10      
LCDMuxInstance/RegLCD1<3> 
                  .......XX.X............................. 3       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB4  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               15/25
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   25/31
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
LCD10_G                       7     FB4_1   8    I/O     O                 
LCD10_DP                      2     FB4_2   9    I/O     O                 
LCD1_A                        6     FB4_3   10   I/O     O                 
(unused)                      0     FB4_4        (b)           
LCD1_B                        5     FB4_5   11   I/O     O                 
(unused)                      0     FB4_6   12   I/O           
(unused)                      0     FB4_7        (b)           
(unused)                      0     FB4_8        (b)           
(unused)                      0     FB4_9        (b)           
(unused)                      0     FB4_10       (b)           
(unused)                      0     FB4_11       (b)           
(unused)                      0     FB4_12       (b)           
LCD1_C                        5     FB4_13  13   I/O     O                 
(unused)                      0     FB4_14       (b)           
(unused)                      0     FB4_15       (b)           
(unused)                      0     FB4_16       (b)           

Signals Used by Logic in Function Block
  1: LCDMuxInstance/DotReg<0>     6: LCDMuxInstance/RegLCD1<0>  11: N_PZ_286 
  2: LCDMuxInstance/RegLCD10<0>   7: LCDMuxInstance/RegLCD1<1>  12: N_PZ_288 
  3: LCDMuxInstance/RegLCD10<1>   8: LCDMuxInstance/RegLCD1<3>  13: N_PZ_289 
  4: LCDMuxInstance/RegLCD10<2>   9: LCD_BP                     14: N_PZ_310 
  5: LCDMuxInstance/RegLCD10<3>  10: N_PZ_285                   15: N_PZ_314 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
LCD10_G           .XXXX...XX..X........................... 7       
LCD10_DP          X.......X............................... 2       
LCD1_A            .....X.XX.XX.XX......................... 7       
LCD1_B            .....XX.X.XX.XX......................... 7       
LCD1_C            .....XXXX.XX.XX......................... 8       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB5  ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB5_1        (b)           
(unused)                      0     FB5_2        (b)           
(unused)                      0     FB5_3        (b)           
(unused)                      0     FB5_4   23   GCK/I/O       
(unused)                      0     FB5_5        (b)           
(unused)                      0     FB5_6   22   GCK/I/O GCK   
(unused)                      0     FB5_7        (b)           
(unused)                      0     FB5_8        (b)           
(unused)                      0     FB5_9        (b)           
(unused)                      0     FB5_10       (b)           
(unused)                      0     FB5_11       (b)           
(unused)                      0     FB5_12       (b)           
(unused)                      0     FB5_13       (b)           
(unused)                      0     FB5_14       (b)           
(unused)                      0     FB5_15       (b)           
(unused)                      0     FB5_16       (b)           
*********************************** FB6  ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               8/32
Number of function block control terms used/remaining:        2/2
Number of PLA product terms used/remaining:                   3/53
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB6_1        (b)           
(unused)                      0     FB6_2   24   CDR/I/O       
(unused)                      0     FB6_3        (b)           
LCD_BP                        3     FB6_4   27   GCK/I/O O      +   +      
(unused)                      0     FB6_5        (b)           
(unused)                      0     FB6_6        (b)           
(unused)                      0     FB6_7        (b)           
(unused)                      0     FB6_8        (b)           
(unused)                      0     FB6_9        (b)           
(unused)                      0     FB6_10       (b)           
(unused)                      0     FB6_11       (b)           
(unused)                      0     FB6_12  28   DGE/I/O       
(unused)                      0     FB6_13       (b)           
(unused)                      0     FB6_14  29   I/O           
(unused)                      0     FB6_15       (b)           
(unused)                      0     FB6_16  30   I/O           

Signals Used by Logic in Function Block
  1: FClk               4: FDiv<2>            7: FDiv<5> 
  2: FDiv<0>            5: FDiv<3>            8: Reset 
  3: FDiv<1>            6: FDiv<4>          

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
LCD_BP            XXXXXXXX................................ 8       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB7  ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               10/30
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   26/30
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB7_1        (b)           
(unused)                      0     FB7_2        (b)           
(unused)                      0     FB7_3        (b)           
(unused)                      0     FB7_4        (b)           
(unused)                      0     FB7_5   19   I/O           
LCD1_DP                       2     FB7_6   18   I/O     O                 
(unused)                      0     FB7_7        (b)           
(unused)                      0     FB7_8        (b)           
(unused)                      0     FB7_9        (b)           
(unused)                      0     FB7_10       (b)           
LCD1_G                        6     FB7_11  17   I/O     O                 
LCD1_F                        6     FB7_12  16   I/O     O                 
LCD1_E                        6     FB7_13  15   I/O     O                 
LCD1_D                        6     FB7_14  14   I/O     O                 
(unused)                      0     FB7_15       (b)           
(unused)                      0     FB7_16       (b)           

Signals Used by Logic in Function Block
  1: LCDMuxInstance/DotReg<0>    5: LCDMuxInstance/RegLCD1<3>   8: N_PZ_288 
  2: LCDMuxInstance/RegLCD1<0>   6: LCD_BP                      9: N_PZ_310 
  3: LCDMuxInstance/RegLCD1<1>   7: N_PZ_286                   10: N_PZ_314 
  4: LCDMuxInstance/RegLCD1<2> 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
LCD1_DP           X....X.................................. 2       
LCD1_G            .XXXXXX..X.............................. 7       
LCD1_F            .XXXXXXXXX.............................. 9       
LCD1_E            .X.XXXXXXX.............................. 8       
LCD1_D            .XX.XXXXXX.............................. 8       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB8  ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB8_1        (b)           
(unused)                      0     FB8_2        (b)           
(unused)                      0     FB8_3        (b)           
(unused)                      0     FB8_4        (b)           
(unused)                      0     FB8_5        (b)           
(unused)                      0     FB8_6   32   I/O           
(unused)                      0     FB8_7        (b)           
(unused)                      0     FB8_8        (b)           
(unused)                      0     FB8_9        (b)           
(unused)                      0     FB8_10       (b)           
(unused)                      0     FB8_11  33   I/O           
(unused)                      0     FB8_12  34   I/O           
(unused)                      0     FB8_13  35   I/O           
(unused)                      0     FB8_14  36   I/O           
(unused)                      0     FB8_15  37   I/O           
(unused)                      0     FB8_16       (b)           
*********************************** FB9  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB9_1   78   I/O           
(unused)                      0     FB9_2   79   I/O           
(unused)                      0     FB9_3        (b)           
(unused)                      0     FB9_4   80   I/O           
(unused)                      0     FB9_5        (b)           
(unused)                      0     FB9_6   81   I/O           
(unused)                      0     FB9_7        (b)           
(unused)                      0     FB9_8        (b)           
(unused)                      0     FB9_9        (b)           
(unused)                      0     FB9_10       (b)           
(unused)                      0     FB9_11       (b)           
(unused)                      0     FB9_12  82   I/O           
(unused)                      0     FB9_13       (b)           
(unused)                      0     FB9_14       (b)           
(unused)                      0     FB9_15       (b)           
(unused)                      0     FB9_16       (b)           
*********************************** FB10 ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB10_1  77   I/O           
(unused)                      0     FB10_2  76   I/O           
(unused)                      0     FB10_3  74   I/O           
(unused)                      0     FB10_4  73   I/O           
(unused)                      0     FB10_5  72   I/O           
(unused)                      0     FB10_6  71   I/O           
(unused)                      0     FB10_7       (b)           
(unused)                      0     FB10_8       (b)           
(unused)                      0     FB10_9       (b)           
(unused)                      0     FB10_10      (b)           
(unused)                      0     FB10_11      (b)           
(unused)                      0     FB10_12 70   I/O           
(unused)                      0     FB10_13      (b)           
(unused)                      0     FB10_14      (b)           
(unused)                      0     FB10_15      (b)           
(unused)                      0     FB10_16      (b)           
*********************************** FB11 ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB11_1       (b)           
(unused)                      0     FB11_2       (b)           
(unused)                      0     FB11_3       (b)           
(unused)                      0     FB11_4       (b)           
(unused)                      0     FB11_5       (b)           
(unused)                      0     FB11_6       (b)           
(unused)                      0     FB11_7       (b)           
(unused)                      0     FB11_8       (b)           
(unused)                      0     FB11_9       (b)           
(unused)                      0     FB11_10      (b)           
(unused)                      0     FB11_11 85   I/O           
(unused)                      0     FB11_12 86   I/O           
(unused)                      0     FB11_13 87   I/O           
(unused)                      0     FB11_14 89   I/O           
(unused)                      0     FB11_15      (b)           
(unused)                      0     FB11_16      (b)           
*********************************** FB12 ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB12_1       (b)           
(unused)                      0     FB12_2       (b)           
(unused)                      0     FB12_3       (b)           
(unused)                      0     FB12_4       (b)           
(unused)                      0     FB12_5       (b)           
(unused)                      0     FB12_6       (b)           
(unused)                      0     FB12_7       (b)           
(unused)                      0     FB12_8       (b)           
(unused)                      0     FB12_9       (b)           
(unused)                      0     FB12_10      (b)           
(unused)                      0     FB12_11 68   I/O           
(unused)                      0     FB12_12      (b)           
(unused)                      0     FB12_13 67   I/O           
(unused)                      0     FB12_14 66   I/O           
(unused)                      0     FB12_15 65   I/O     I     
(unused)                      0     FB12_16      (b)           
*********************************** FB13 ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB13_1       (b)           
(unused)                      0     FB13_2  53   I/O           
(unused)                      0     FB13_3       (b)           
(unused)                      0     FB13_4  54   I/O           
(unused)                      0     FB13_5       (b)           
(unused)                      0     FB13_6  55   I/O           
(unused)                      0     FB13_7       (b)           
(unused)                      0     FB13_8       (b)           
(unused)                      0     FB13_9       (b)           
(unused)                      0     FB13_10      (b)           
(unused)                      0     FB13_11      (b)           
(unused)                      0     FB13_12      (b)           
(unused)                      0     FB13_13 56   I/O           
(unused)                      0     FB13_14      (b)           
(unused)                      0     FB13_15      (b)           
(unused)                      0     FB13_16      (b)           
*********************************** FB14 ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB14_1  52   I/O           
(unused)                      0     FB14_2       (b)           
(unused)                      0     FB14_3  50   I/O           
(unused)                      0     FB14_4       (b)           
(unused)                      0     FB14_5  49   I/O           
(unused)                      0     FB14_6       (b)           
(unused)                      0     FB14_7       (b)           
(unused)                      0     FB14_8       (b)           
(unused)                      0     FB14_9       (b)           
(unused)                      0     FB14_10      (b)           
(unused)                      0     FB14_11      (b)           
(unused)                      0     FB14_12      (b)           
(unused)                      0     FB14_13      (b)           
(unused)                      0     FB14_14 46   I/O           
(unused)                      0     FB14_15 44   I/O           
(unused)                      0     FB14_16      (b)           
*********************************** FB15 ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB15_1       (b)           
(unused)                      0     FB15_2       (b)           
(unused)                      0     FB15_3       (b)           
(unused)                      0     FB15_4       (b)           
(unused)                      0     FB15_5       (b)           
(unused)                      0     FB15_6       (b)           
(unused)                      0     FB15_7       (b)           
(unused)                      0     FB15_8       (b)           
(unused)                      0     FB15_9       (b)           
(unused)                      0     FB15_10      (b)           
(unused)                      0     FB15_11 58   I/O           
(unused)                      0     FB15_12 59   I/O           
(unused)                      0     FB15_13 60   I/O           
(unused)                      0     FB15_14 61   I/O           
(unused)                      0     FB15_15 63   I/O           
(unused)                      0     FB15_16 64   I/O           
*********************************** FB16 ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB16_1       (b)           
(unused)                      0     FB16_2       (b)           
(unused)                      0     FB16_3       (b)           
(unused)                      0     FB16_4       (b)           
(unused)                      0     FB16_5  43   I/O           
(unused)                      0     FB16_6  42   I/O           
(unused)                      0     FB16_7       (b)           
(unused)                      0     FB16_8       (b)           
(unused)                      0     FB16_9       (b)           
(unused)                      0     FB16_10      (b)           
(unused)                      0     FB16_11 41   I/O           
(unused)                      0     FB16_12 40   I/O           
(unused)                      0     FB16_13 39   I/O           
(unused)                      0     FB16_14      (b)           
(unused)                      0     FB16_15      (b)           
(unused)                      0     FB16_16      (b)           
*******************************  Equations  ********************************

********** Mapped Logic **********

FTCPE_Cnt100: FTCPE port map (Cnt10(0),Cnt10_T(0),FDiv(11),NOT Reset,'0','1');
Cnt10_T(0) <= (Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3));

FTCPE_Cnt101: FTCPE port map (Cnt10(1),Cnt10_T(1),FDiv(11),NOT Reset,'0','1');
Cnt10_T(1) <= ((Cnt10(2) AND Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND 
	NOT Cnt1(2) AND Cnt1(3))
	OR (Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND 
	Cnt1(3) AND Cnt10(1))
	OR (Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND 
	Cnt1(3) AND NOT Cnt10(3)));

FTCPE_Cnt102: FTCPE port map (Cnt10(2),Cnt10_T(2),FDiv(11),NOT Reset,'0','1');
Cnt10_T(2) <= (Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND 
	Cnt1(3) AND Cnt10(1));

FTCPE_Cnt103: FTCPE port map (Cnt10(3),Cnt10_T(3),FDiv(11),NOT Reset,'0','1');
Cnt10_T(3) <= ((Cnt10(2) AND Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND 
	NOT Cnt1(2) AND Cnt1(3) AND Cnt10(1))
	OR (NOT Cnt10(2) AND Cnt10(0) AND Cnt1(0) AND NOT Cnt1(1) AND 
	NOT Cnt1(2) AND Cnt1(3) AND NOT Cnt10(1) AND Cnt10(3)));

FTCPE_Cnt10: FTCPE port map (Cnt1(0),'0',FDiv(11),NOT Reset,'0','1');

FTCPE_Cnt11: FTCPE port map (Cnt1(1),Cnt1_T(1),FDiv(11),NOT Reset,'0','1');
Cnt1_T(1) <= NOT (((NOT Cnt1(0))
	OR (NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3))));

FTCPE_Cnt12: FTCPE port map (Cnt1(2),Cnt1_T(2),FDiv(11),NOT Reset,'0','1');
Cnt1_T(2) <= (Cnt1(0) AND Cnt1(1));

FTCPE_Cnt13: FTCPE port map (Cnt1(3),Cnt1_T(3),FDiv(11),NOT Reset,'0','1');
Cnt1_T(3) <= ((Cnt1(0) AND Cnt1(1) AND Cnt1(2))
	OR (Cnt1(0) AND NOT Cnt1(1) AND NOT Cnt1(2) AND Cnt1(3)));

FTCPE_FClk: FTCPE port map (FClk,FClk_T,NOT Clk,NOT Reset,'0','1');
FClk_T <= (FDivInstance/FDivCnt(0) AND FDivInstance/FDivCnt(1));

FTCPE_FDiv0: FTCPE port map (FDiv(0),'0',FClk,NOT Reset,'0','1');

FTCPE_FDiv1: FTCPE port map (FDiv(1),FDiv(0),FClk,NOT Reset,'0','1');

FTCPE_FDiv2: FTCPE port map (FDiv(2),FDiv_T(2),FClk,NOT Reset,'0','1');
FDiv_T(2) <= (FDiv(0) AND FDiv(1));

FTCPE_FDiv3: FTCPE port map (FDiv(3),FDiv_T(3),FClk,NOT Reset,'0','1');
FDiv_T(3) <= (FDiv(0) AND FDiv(1) AND FDiv(2));

FTCPE_FDiv4: FTCPE port map (FDiv(4),FDiv_T(4),FClk,NOT Reset,'0','1');
FDiv_T(4) <= (FDiv(0) AND FDiv(1) AND FDiv(2) AND FDiv(3));

FTCPE_FDiv5: FTCPE port map (FDiv(5),FDiv_T(5),FClk,NOT Reset,'0','1');
FDiv_T(5) <= (FDiv(0) AND FDiv(1) AND FDiv(2) AND FDiv(3) AND 
	FDiv(4));

FTCPE_FDiv7: FTCPE port map (FDiv(7),FDiv_T(7),FClk,NOT Reset,'0','1');
FDiv_T(7) <= (FDiv(0) AND FDiv(1) AND FDiv(2) AND FDiv(3) AND 
	FDiv(4) AND FDiv(5) AND LCD_BP);

FTCPE_FDiv8: FTCPE port map (FDiv(8),FDiv_T(8),FClk,NOT Reset,'0','1');
FDiv_T(8) <= (FDiv(0) AND FDiv(1) AND FDiv(2) AND FDiv(3) AND 
	FDiv(4) AND FDiv(5) AND LCD_BP AND FDiv(7));

FTCPE_FDiv9: FTCPE port map (FDiv(9),FDiv_T(9),FClk,NOT Reset,'0','1');
FDiv_T(9) <= (FDiv(0) AND FDiv(1) AND FDiv(2) AND FDiv(3) AND 
	FDiv(4) AND FDiv(5) AND LCD_BP AND FDiv(7) AND FDiv(8));

FTCPE_FDiv10: FTCPE port map (FDiv(10),FDiv_T(10),FClk,NOT Reset,'0','1');
FDiv_T(10) <= (FDiv(0) AND FDiv(1) AND FDiv(2) AND FDiv(3) AND 
	FDiv(4) AND FDiv(5) AND LCD_BP AND FDiv(7) AND FDiv(8) AND FDiv(9));

FTCPE_FDiv11: FTCPE port map (FDiv(11),FDiv_T(11),FClk,NOT Reset,'0','1');
FDiv_T(11) <= (FDiv(0) AND FDiv(1) AND FDiv(2) AND FDiv(3) AND 
	FDiv(4) AND FDiv(5) AND LCD_BP AND FDiv(10) AND FDiv(7) AND 
	FDiv(8) AND FDiv(9));

FTCPE_FDivInstance/FDivCnt0: FTCPE port map (FDivInstance/FDivCnt(0),'0',NOT Clk,NOT Reset,'0','1');

FTCPE_FDivInstance/FDivCnt1: FTCPE port map (FDivInstance/FDivCnt(1),FDivInstance/FDivCnt(0),NOT Clk,NOT Reset,'0','1');


LCD10_A <= ((LCD_BP AND N_PZ_285 AND N_PZ_287)
	OR (NOT LCD_BP AND LCDMuxInstance/RegLCD10(2) AND 
	LCDMuxInstance/RegLCD10(1))
	OR (NOT LCD_BP AND NOT LCDMuxInstance/RegLCD10(2) AND N_PZ_305)
	OR (NOT LCD_BP AND NOT LCDMuxInstance/RegLCD10(0) AND NOT N_PZ_285)
	OR (NOT LCD_BP AND NOT LCDMuxInstance/RegLCD10(3) AND NOT N_PZ_287)
	OR (LCD_BP AND LCDMuxInstance/RegLCD10(2) AND 
	LCDMuxInstance/RegLCD10(3) AND N_PZ_305)
	OR (LCD_BP AND LCDMuxInstance/RegLCD10(0) AND N_PZ_287 AND 
	N_PZ_289));


LCD10_B <= ((NOT LCD_BP AND N_PZ_305)
	OR (LCD_BP AND LCDMuxInstance/RegLCD10(0) AND N_PZ_289)
	OR (NOT LCD_BP AND NOT LCDMuxInstance/RegLCD10(2) AND 
	NOT LCDMuxInstance/RegLCD10(0))
	OR (NOT LCD_BP AND NOT LCDMuxInstance/RegLCD10(2) AND 
	NOT LCDMuxInstance/RegLCD10(3))
	OR (NOT LCD_BP AND NOT LCDMuxInstance/RegLCD10(0) AND N_PZ_285)
	OR (LCD_BP AND LCDMuxInstance/RegLCD10(2) AND 
	NOT LCDMuxInstance/RegLCD10(0) AND NOT N_PZ_285));


LCD10_C <= ((NOT LCD_BP AND N_PZ_285)
	OR (NOT LCD_BP AND LCDMuxInstance/RegLCD10(2) AND 
	NOT LCDMuxInstance/RegLCD10(3))
	OR (NOT LCD_BP AND NOT LCDMuxInstance/RegLCD10(2) AND 
	LCDMuxInstance/RegLCD10(3))
	OR (NOT LCD_BP AND LCDMuxInstance/RegLCD10(0) AND NOT N_PZ_289)
	OR (LCD_BP AND LCDMuxInstance/RegLCD10(2) AND 
	LCDMuxInstance/RegLCD10(3) AND NOT N_PZ_305)
	OR (LCD_BP AND NOT LCDMuxInstance/RegLCD10(2) AND 
	LCDMuxInstance/RegLCD10(1) AND NOT N_PZ_287 AND NOT N_PZ_289));


LCD10_DP <= ((LCD_BP AND LCDMuxInstance/DotReg(0))
	OR (NOT LCD_BP AND NOT LCDMuxInstance/DotReg(0)));


LCD10_D <= NOT (((LCD_BP AND NOT N_PZ_285 AND N_PZ_287)
	OR (LCD_BP AND LCDMuxInstance/RegLCD10(3) AND NOT N_PZ_289)
	OR (NOT LCD_BP AND N_PZ_285 AND N_PZ_287)
	OR (LCD_BP AND NOT LCDMuxInstance/RegLCD10(3) AND NOT N_PZ_287 AND 
	NOT N_PZ_305)
	OR (NOT LCD_BP AND LCDMuxInstance/RegLCD10(1) AND 
	LCDMuxInstance/RegLCD10(0) AND NOT N_PZ_287)
	OR (NOT LCD_BP AND LCDMuxInstance/RegLCD10(1) AND NOT N_PZ_287 AND 
	N_PZ_289)));


LCD10_E <= ((LCD_BP AND LCDMuxInstance/RegLCD10(0) AND 
	NOT LCDMuxInstance/RegLCD10(3))
	OR (LCD_BP AND N_PZ_285 AND N_PZ_289)
	OR (LCD_BP AND N_PZ_287 AND N_PZ_305)
	OR (NOT LCD_BP AND NOT N_PZ_285 AND NOT N_PZ_305)
	OR (NOT LCD_BP AND NOT LCDMuxInstance/RegLCD10(1) AND NOT N_PZ_287 AND 
	NOT N_PZ_289));


LCD10_F <= ((LCD_BP AND NOT N_PZ_287 AND N_PZ_305)
	OR (NOT LCD_BP AND LCDMuxInstance/RegLCD10(2) AND NOT N_PZ_305)
	OR (NOT LCD_BP AND NOT LCDMuxInstance/RegLCD10(2) AND 
	LCDMuxInstance/RegLCD10(3))
	OR (NOT LCD_BP AND NOT LCDMuxInstance/RegLCD10(0) AND N_PZ_285)
	OR (LCD_BP AND NOT LCDMuxInstance/RegLCD10(2) AND 
	LCDMuxInstance/RegLCD10(1) AND NOT LCDMuxInstance/RegLCD10(3))
	OR (LCD_BP AND N_PZ_285 AND N_PZ_287 AND NOT N_PZ_289));


LCD10_G <= ((NOT LCD_BP AND N_PZ_289)
	OR (LCD_BP AND NOT LCDMuxInstance/RegLCD10(2) AND N_PZ_285)
	OR (NOT LCD_BP AND NOT LCDMuxInstance/RegLCD10(2) AND NOT N_PZ_285)
	OR (NOT LCD_BP AND LCDMuxInstance/RegLCD10(0) AND 
	LCDMuxInstance/RegLCD10(3))
	OR (NOT LCD_BP AND LCDMuxInstance/RegLCD10(2) AND 
	NOT LCDMuxInstance/RegLCD10(0) AND NOT LCDMuxInstance/RegLCD10(3))
	OR (LCD_BP AND LCDMuxInstance/RegLCD10(2) AND 
	LCDMuxInstance/RegLCD10(1) AND LCDMuxInstance/RegLCD10(0) AND 
	NOT LCDMuxInstance/RegLCD10(3))
	OR (LCD_BP AND LCDMuxInstance/RegLCD10(2) AND 
	NOT LCDMuxInstance/RegLCD10(1) AND NOT LCDMuxInstance/RegLCD10(0) AND 
	LCDMuxInstance/RegLCD10(3)));


LCD1_A <= ((LCD_BP AND N_PZ_286 AND N_PZ_288)
	OR (NOT LCD_BP AND NOT LCDMuxInstance/RegLCD1(3) AND NOT N_PZ_286)
	OR (NOT LCD_BP AND NOT N_PZ_286 AND NOT LCDMuxInstance/RegLCD1(0))
	OR (NOT LCD_BP AND NOT N_PZ_288 AND NOT N_PZ_310)
	OR (LCDMuxInstance/RegLCD1(3) AND 
	LCDMuxInstance/RegLCD1(0) AND N_PZ_310 AND NOT N_PZ_314)
	OR (LCDMuxInstance/RegLCD1(3) AND 
	LCDMuxInstance/RegLCD1(0) AND NOT N_PZ_310 AND N_PZ_314));


LCD1_B <= ((NOT LCD_BP AND N_PZ_310)
	OR (NOT LCD_BP AND N_PZ_286 AND N_PZ_288)
	OR (NOT N_PZ_286 AND NOT LCDMuxInstance/RegLCD1(0) AND NOT N_PZ_314)
	OR (NOT N_PZ_288 AND NOT N_PZ_310 AND NOT N_PZ_314)
	OR (LCD_BP AND LCDMuxInstance/RegLCD1(1) AND 
	LCDMuxInstance/RegLCD1(0) AND NOT N_PZ_310));


LCD1_C <= ((NOT LCD_BP AND N_PZ_286)
	OR (NOT LCD_BP AND NOT LCDMuxInstance/RegLCD1(3) AND N_PZ_288)
	OR (NOT LCD_BP AND NOT LCDMuxInstance/RegLCD1(1) AND 
	LCDMuxInstance/RegLCD1(0))
	OR (LCDMuxInstance/RegLCD1(3) AND NOT N_PZ_310 AND NOT N_PZ_314)
	OR (NOT LCDMuxInstance/RegLCD1(3) AND NOT N_PZ_286 AND NOT N_PZ_288 AND 
	N_PZ_314));


LCD1_DP <= ((LCD_BP AND LCDMuxInstance/DotReg(0))
	OR (NOT LCD_BP AND NOT LCDMuxInstance/DotReg(0)));


LCD1_D <= NOT (((LCD_BP AND NOT N_PZ_286 AND NOT LCDMuxInstance/RegLCD1(1))
	OR (LCD_BP AND NOT N_PZ_286 AND N_PZ_288)
	OR (NOT LCD_BP AND N_PZ_286 AND N_PZ_288)
	OR (LCDMuxInstance/RegLCD1(1) AND 
	LCDMuxInstance/RegLCD1(0) AND N_PZ_314)
	OR (LCD_BP AND NOT LCDMuxInstance/RegLCD1(3) AND NOT N_PZ_288 AND 
	NOT N_PZ_310)
	OR (NOT LCD_BP AND LCDMuxInstance/RegLCD1(3) AND 
	LCDMuxInstance/RegLCD1(1) AND NOT N_PZ_288)));


LCD1_E <= ((LCD_BP AND NOT LCDMuxInstance/RegLCD1(3) AND 
	LCDMuxInstance/RegLCD1(0))
	OR (NOT LCD_BP AND NOT N_PZ_286 AND NOT N_PZ_310)
	OR (NOT LCD_BP AND NOT N_PZ_288 AND NOT N_PZ_314)
	OR (LCDMuxInstance/RegLCD1(3) AND 
	LCDMuxInstance/RegLCD1(2) AND N_PZ_314)
	OR (N_PZ_286 AND LCDMuxInstance/RegLCD1(2) AND NOT N_PZ_314)
	OR (N_PZ_288 AND N_PZ_310 AND N_PZ_314));


LCD1_F <= ((NOT LCD_BP AND NOT LCDMuxInstance/RegLCD1(1) AND 
	NOT LCDMuxInstance/RegLCD1(0))
	OR (LCDMuxInstance/RegLCD1(3) AND 
	NOT LCDMuxInstance/RegLCD1(2) AND NOT N_PZ_314)
	OR (N_PZ_286 AND LCDMuxInstance/RegLCD1(0) AND N_PZ_314)
	OR (NOT N_PZ_288 AND N_PZ_310 AND NOT N_PZ_314)
	OR (LCDMuxInstance/RegLCD1(2) AND NOT N_PZ_310 AND N_PZ_314)
	OR (LCD_BP AND NOT LCDMuxInstance/RegLCD1(3) AND NOT N_PZ_286 AND 
	N_PZ_314));


LCD1_G <= ((N_PZ_286 AND N_PZ_314)
	OR (NOT LCD_BP AND LCDMuxInstance/RegLCD1(3) AND 
	LCDMuxInstance/RegLCD1(0))
	OR (NOT LCD_BP AND NOT N_PZ_286 AND NOT LCDMuxInstance/RegLCD1(2))
	OR (NOT LCD_BP AND LCDMuxInstance/RegLCD1(1) AND 
	NOT LCDMuxInstance/RegLCD1(0))
	OR (LCD_BP AND LCDMuxInstance/RegLCD1(3) AND 
	NOT LCDMuxInstance/RegLCD1(1) AND NOT LCDMuxInstance/RegLCD1(0) AND 
	LCDMuxInstance/RegLCD1(2))
	OR (LCD_BP AND NOT LCDMuxInstance/RegLCD1(3) AND 
	LCDMuxInstance/RegLCD1(1) AND LCDMuxInstance/RegLCD1(0) AND 
	LCDMuxInstance/RegLCD1(2)));

FDCPE_LCDMuxInstance/DotReg0: FDCPE port map (LCDMuxInstance/DotReg(0),NOT '0',FClk,NOT Reset,'0','1');

FDCPE_LCDMuxInstance/RegLCD100: FDCPE port map (LCDMuxInstance/RegLCD10(0),Cnt10(0),FClk,NOT Reset,'0','1');

FDCPE_LCDMuxInstance/RegLCD101: FDCPE port map (LCDMuxInstance/RegLCD10(1),Cnt10(1),FClk,NOT Reset,'0','1');

FDCPE_LCDMuxInstance/RegLCD102: FDCPE port map (LCDMuxInstance/RegLCD10(2),Cnt10(2),FClk,NOT Reset,'0','1');

FDCPE_LCDMuxInstance/RegLCD103: FDCPE port map (LCDMuxInstance/RegLCD10(3),Cnt10(3),FClk,NOT Reset,'0','1');

FDCPE_LCDMuxInstance/RegLCD10: FDCPE port map (LCDMuxInstance/RegLCD1(0),Cnt1(0),FClk,NOT Reset,'0','1');

FDCPE_LCDMuxInstance/RegLCD11: FDCPE port map (LCDMuxInstance/RegLCD1(1),Cnt1(1),FClk,NOT Reset,'0','1');

FDCPE_LCDMuxInstance/RegLCD12: FDCPE port map (LCDMuxInstance/RegLCD1(2),Cnt1(2),FClk,NOT Reset,'0','1');

FDCPE_LCDMuxInstance/RegLCD13: FDCPE port map (LCDMuxInstance/RegLCD1(3),Cnt1(3),FClk,NOT Reset,'0','1');

FTCPE_LCD_BP: FTCPE port map (LCD_BP,LCD_BP_T,FClk,NOT Reset,'0','1');
LCD_BP_T <= (FDiv(0) AND FDiv(1) AND FDiv(2) AND FDiv(3) AND 
	FDiv(4) AND FDiv(5));


N_PZ_285 <= (NOT LCDMuxInstance/RegLCD10(1) AND 
	NOT LCDMuxInstance/RegLCD10(3));


N_PZ_286 <= (NOT LCDMuxInstance/RegLCD1(3) AND 
	NOT LCDMuxInstance/RegLCD1(1));


N_PZ_287 <= ((LCDMuxInstance/RegLCD10(2) AND 
	NOT LCDMuxInstance/RegLCD10(0))
	OR (NOT LCDMuxInstance/RegLCD10(2) AND 
	LCDMuxInstance/RegLCD10(0)));


N_PZ_288 <= ((LCDMuxInstance/RegLCD1(0) AND 
	NOT LCDMuxInstance/RegLCD1(2))
	OR (NOT LCDMuxInstance/RegLCD1(0) AND 
	LCDMuxInstance/RegLCD1(2)));


N_PZ_289 <= ((LCDMuxInstance/RegLCD10(2) AND N_PZ_285)
	OR (LCDMuxInstance/RegLCD10(1) AND 
	LCDMuxInstance/RegLCD10(3)));


N_PZ_305 <= ((LCDMuxInstance/RegLCD10(1) AND 
	LCDMuxInstance/RegLCD10(0) AND NOT LCDMuxInstance/RegLCD10(3))
	OR (NOT LCDMuxInstance/RegLCD10(1) AND 
	LCDMuxInstance/RegLCD10(0) AND LCDMuxInstance/RegLCD10(3)));


N_PZ_310 <= ((LCDMuxInstance/RegLCD1(3) AND 
	NOT LCDMuxInstance/RegLCD1(1) AND LCDMuxInstance/RegLCD1(0))
	OR (NOT LCDMuxInstance/RegLCD1(3) AND 
	LCDMuxInstance/RegLCD1(1) AND LCDMuxInstance/RegLCD1(0)));


N_PZ_314 <= ((LCD_BP AND NOT LCDMuxInstance/RegLCD1(2))
	OR (NOT LCD_BP AND LCDMuxInstance/RegLCD1(2)));


Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE); 
 FDDCPE (Q,D,C,CLR,PRE,CE); 
 FTCPE (Q,D,C,CLR,PRE,CE); 
 FTDCPE (Q,D,C,CLR,PRE,CE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC2C256-6-VQ100


   --------------------------------------------------  
  /100 98  96  94  92  90  88  86  84  82  80  78  76  \
 |   99  97  95  93  91  89  87  85  83  81  79  77    |
 | 1                                               75  | 
 | 2                                               74  | 
 | 3                                               73  | 
 | 4                                               72  | 
 | 5                                               71  | 
 | 6                                               70  | 
 | 7                                               69  | 
 | 8                                               68  | 
 | 9                                               67  | 
 | 10                                              66  | 
 | 11                                              65  | 
 | 12                                              64  | 
 | 13                XC2C256-6-VQ100               63  | 
 | 14                                              62  | 
 | 15                                              61  | 
 | 16                                              60  | 
 | 17                                              59  | 
 | 18                                              58  | 
 | 19                                              57  | 
 | 20                                              56  | 
 | 21                                              55  | 
 | 22                                              54  | 
 | 23                                              53  | 
 | 24                                              52  | 
 | 25                                              51  | 
 |   27  29  31  33  35  37  39  41  43  45  47  49    |
  \26  28  30  32  34  36  38  40  42  44  46  48  50  /
   --------------------------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 LCD10_A                          51 VCCIO-1.8                     
  2 LCD10_B                          52 KPR                           
  3 LCD10_C                          53 KPR                           
  4 LCD10_D                          54 KPR                           
  5 VCCAUX                           55 KPR                           
  6 LCD10_E                          56 KPR                           
  7 LCD10_F                          57 VCC                           
  8 LCD10_G                          58 KPR                           
  9 LCD10_DP                         59 KPR                           
 10 LCD1_A                           60 KPR                           
 11 LCD1_B                           61 KPR                           
 12 KPR                              62 GND                           
 13 LCD1_C                           63 KPR                           
 14 LCD1_D                           64 KPR                           
 15 LCD1_E                           65 Reset                         
 16 LCD1_F                           66 KPR                           
 17 LCD1_G                           67 KPR                           
 18 LCD1_DP                          68 KPR                           
 19 KPR                              69 GND                           
 20 VCCIO-1.8                        70 KPR                           
 21 GND                              71 KPR                           
 22 Clk                              72 KPR                           
 23 KPR                              73 KPR                           
 24 KPR                              74 KPR                           
 25 GND                              75 GND                           
 26 VCC                              76 KPR                           
 27 LCD_BP                           77 KPR                           
 28 KPR                              78 KPR                           
 29 KPR                              79 KPR                           
 30 KPR                              80 KPR                           
 31 GND                              81 KPR                           
 32 KPR                              82 KPR                           
 33 KPR                              83 TDO                           
 34 KPR                              84 GND                           
 35 KPR                              85 KPR                           
 36 KPR                              86 KPR                           
 37 KPR                              87 KPR                           
 38 VCCIO-1.8                        88 VCCIO-1.8                     
 39 KPR                              89 KPR                           
 40 KPR                              90 KPR                           
 41 KPR                              91 KPR                           
 42 KPR                              92 KPR                           
 43 KPR                              93 KPR                           
 44 KPR                              94 KPR                           
 45 TDI                              95 KPR                           
 46 KPR                              96 KPR                           
 47 TMS                              97 KPR                           
 48 TCK                              98 VCCIO-1.8                     
 49 KPR                              99 KPR                           
 50 KPR                             100 GND                           


Legend :  NC  = Not Connected, unbonded pin
        PGND  = Unused I/O configured as additional Ground pin
         KPR  = Unused I/O with weak keeper (leave unconnected)
         WPU  = Unused I/O with weak pull up (leave unconnected)
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
      VCCAUX  = Power supply for JTAG pins
   VCCIO-3.3  = I/O supply voltage for LVTTL, LVCMOS33, SSTL3_I
   VCCIO-2.5  = I/O supply voltage for LVCMOS25, SSTL2_I
   VCCIO-1.8  = I/O supply voltage for LVCMOS18
   VCCIO-1.5  = I/O supply voltage for LVCMOS15, HSTL_I
        VREF  = Reference voltage for indicated input standard
       *VREF  = Reference voltage pin selected by software
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc2c256-6-VQ100
Optimization Method                         : DENSITY
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Set Unused I/O Pin Termination              : KEEPER
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
Enable Input Registers                      : ON
Function Block Fan-in Limit                 : 38
Use DATA_GATE Attribute                     : ON
Set Tristate Outputs to Termination Mode    : KEEPER
Default Voltage Standard for All Outputs    : LVCMOS18
Input Limit                                 : 32
Pterm Limit                                 : 28