cpldfit:  version J.36                              Xilinx Inc.
                                  Fitter Report
Design Name: Generator                           Date:  3-30-2010, 11:18PM
Device Used: XC2C256-6-VQ100
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
95 /256 ( 37%) 284 /896  ( 32%) 193 /640  ( 30%) 64 /256 ( 25%) 21 /80  ( 26%)

** Function Block Resources **

Function Mcells   FB Inps  Pterms   IO       CTC      CTR      CTS      CTE     
Block    Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot
FB1      16/16*    34/40    54/56     0/ 5    1/1*     1/1*     1/1*     0/1
FB2      10/16     28/40    56/56*    6/ 6*   0/1      1/1*     0/1      0/1
FB3      16/16*    31/40    48/56     0/ 4    1/1*     1/1*     0/1      0/1
FB4       9/16     38/40*   36/56     3/ 6    1/1*     1/1*     0/1      0/1
FB5      16/16*    19/40    48/56     0/ 2    1/1*     1/1*     0/1      0/1
FB6      16/16*    24/40    24/56     2/ 5    1/1*     1/1*     1/1*     0/1
FB7      10/16     15/40    14/56     4/ 6    1/1*     1/1*     1/1*     0/1
FB8       0/16      0/40     0/56     0/ 6    0/1      0/1      0/1      0/1
FB9       0/16      0/40     0/56     0/ 5    0/1      0/1      0/1      0/1
FB10      0/16      0/40     0/56     0/ 7    0/1      0/1      0/1      0/1
FB11      0/16      0/40     0/56     0/ 4    0/1      0/1      0/1      0/1
FB12      0/16      0/40     0/56     0/ 4    0/1      0/1      0/1      0/1
FB13      1/16      2/40     2/56     0/ 4    1/1*     0/1      1/1*     0/1
FB14      0/16      0/40     0/56     0/ 5    0/1      0/1      0/1      0/1
FB15      1/16      2/40     2/56     0/ 6    1/1*     0/1      1/1*     0/1
FB16      0/16      0/40     0/56     0/ 5    0/1      0/1      0/1      0/1
         -----    -------  -------   -----    ---      ---      ---      ---
Total    95/256   193/640  284/896   15/80    8/16     7/16     5/16     0/16

CTC - Control Term Clock
CTR - Control Term Reset
CTS - Control Term Set
CTE - Control Term Output Enable

* - Resource is exhausted

** Global Control Resources **

GCK         GSR         GTS         
Used/Tot    Used/Tot    Used/Tot    
1/3         0/1         0/4

Signal 'Clk' mapped onto global clock net GCK0.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :    5           5    |  I/O              :    14     70
Output        :   15          15    |  GCK/IO           :     2      3
Bidirectional :    0           0    |  GTS/IO           :     4      4
GCK           :    1           1    |  GSR/IO           :     0      1
GTS           :    0           0    |  CDR/IO           :     1      1
GSR           :    0           0    |  DGE/IO           :     0      1
                 ----        ----
        Total     21          21

End of Mapped Resource Summary
*************************  Summary of Mapped Logic  ************************

** 15 Outputs **

Signal                                Total Total Loc     Pin   Pin       Pin     I/O      I/O       Slew Reg     Reg Init
Name                                  Pts   Inps          No.   Type      Use     STD      Style     Rate Use     State
Seg_K                                 2     3     FB2_1   1     GTS/I/O   O       LVCMOS18           FAST         
Seg_G                                 11    19    FB2_3   2     GTS/I/O   O       LVCMOS18           FAST         
Seg_F                                 11    20    FB2_5   3     GTS/I/O   O       LVCMOS18           FAST         
Seg_E                                 11    18    FB2_12  4     GTS/I/O   O       LVCMOS18           FAST         
Seg_D                                 12    20    FB2_14  6     I/O       O       LVCMOS18           FAST         
Seg_C                                 10    19    FB2_15  7     I/O       O       LVCMOS18           FAST         
Seg_A                                 11    21    FB4_1   8     I/O       O       LVCMOS18           FAST         
Seg_B                                 13    21    FB4_2   9     I/O       O       LVCMOS18           FAST         
OutSig                                3     5     FB4_3   10    I/O       O       LVCMOS18           FAST TFF     RESET
DSel2                                 1     2     FB6_2   24    CDR/I/O   O       LVCMOS18           FAST         
DSel3                                 1     2     FB6_4   27    GCK/I/O   O       LVCMOS18           FAST         
DSel1                                 1     2     FB7_5   19    I/O       O       LVCMOS18           FAST         
DSel0                                 1     2     FB7_6   18    I/O       O       LVCMOS18           FAST         
DirLed                                2     3     FB7_11  17    I/O       O       LVCMOS18           FAST TFF/S   SET
SpeedLed                              1     1     FB7_12  16    I/O       O       LVCMOS18           FAST         

** 80 Buried Nodes **

Signal                                Total Total Loc     Reg     Reg Init
Name                                  Pts   Inps          Use     State
UCmpReg<5>                            4     9     FB1_1   TFF     RESET
LCmpReg<5>                            4     9     FB1_2   TFF     RESET
BinCnt<7>                             6     10    FB1_3   TFF     RESET
UCmpReg<6>                            4     10    FB1_4   TFF     RESET
UCmpReg<7>                            4     11    FB1_5   TFF     RESET
UCmpReg<3>                            4     7     FB1_6   TFF     RESET
LCmpReg<6>                            4     10    FB1_7   TFF     RESET
LCmpReg<7>                            4     11    FB1_8   TFF     RESET
Mcompar_BinCnt_cmp_eq0000_AEB_or0000  16    16    FB1_9           
N_PZ_556                              2     10    FB1_10          
N_PZ_542                              2     10    FB1_11          
LCmpReg<3>                            4     7     FB1_12  TFF     RESET
UCmpReg<4>                            4     8     FB1_13  TFF     RESET
LCmpReg<4>                            4     8     FB1_14  TFF     RESET
N_PZ_540                              2     10    FB1_15          
N_PZ_592                              4     18    FB1_16          
FDivInstance/FDivCnt<1>               2     2     FB2_10  TFF     RESET
FDivInstance/FDivCnt<0>               1     1     FB2_11  TFF     RESET
Context_FFd1                          3     4     FB2_13  DEFF    RESET
Context_FFd2                          3     5     FB2_16  TFF     RESET
LCmpReg<1>                            4     5     FB3_1   TFF     RESET
UCmpReg<1>                            4     5     FB3_2   TFF     RESET
UCmpReg<2>                            4     6     FB3_3   TFF     RESET
BinCnt<6>                             6     9     FB3_4   TFF     RESET
UCmpReg<0>                            3     3     FB3_5   TFF     RESET
BinCnt<5>                             6     8     FB3_6   DFF     RESET
BinCnt<4>                             5     7     FB3_7   DFF     RESET
BinCnt<3>                             6     9     FB3_8   DFF     RESET
BinCnt<2>                             5     7     FB3_9   DFF     RESET
BinCnt<0>                             4     6     FB3_10  TFF     RESET
BinCnt<1>                             4     7     FB3_11  TFF     RESET
LCmpReg<0>                            3     3     FB3_12  TFF     RESET
N_PZ_429                              1     4     FB3_13          
N_PZ_528                              1     3     FB3_14          
N_PZ_514                              9     16    FB3_15          
LCmpReg<2>                            4     6     FB3_16  TFF     RESET
SetKeyStatus                          3     5     FB4_10  DFF     RESET
MachineState_FFd2                     3     5     FB4_11  DFF     RESET
MachineState_FFd1                     3     5     FB4_12  DFF     RESET
FClk                                  2     3     FB4_14  TFF     RESET

Signal                                Total Total Loc     Reg     Reg Init
Name                                  Pts   Inps          Use     State
MuxDisplInstance/SelCnt<0>            2     2     FB4_15  TFF     RESET
MuxDisplInstance/SelCnt<1>            3     3     FB4_16  TFF     RESET
FDiv<1>                               3     3     FB5_1   TFF     RESET
FDiv<0>                               2     2     FB5_2   TFF     RESET
N_PZ_732                              1     2     FB5_3           
FDiv<3>                               3     5     FB5_4   TFF     RESET
SetupKeyInstance/DelayCnt<0>          3     3     FB5_5   TFF     RESET
FDiv<2>                               3     4     FB5_6   TFF     RESET
SetupKeyInstance/DelayCnt<1>          3     4     FB5_7   TFF     RESET
SetupKeyInstance/DelayCnt<2>          3     5     FB5_8   TFF     RESET
SetupKeyInstance/DelayCnt<3>          3     6     FB5_9   TFF     RESET
SetupKeyInstance/DelayCnt<4>          3     7     FB5_10  TFF     RESET
SetupKeyInstance/AutomatState_FFd1    7     11    FB5_11  DFF     RESET
SetupKeyInstance/AutomatState_FFd3    6     11    FB5_12  TFF     RESET
SetupKeyInstance/AutomatState_FFd4    10    11    FB5_13  DFF     RESET
SetupKeyInstance/AutomatState_FFd2    4     10    FB5_14  DFF     RESET
SetupKeyInstance/DelayCntEnable       3     6     FB5_15  DFF     RESET
SetupKeyInstance/DelayCntClear        3     6     FB5_16  DFF     RESET
FDiv<5>                               3     7     FB6_1   TFF     RESET
FDiv<4>                               3     6     FB6_3   TFF     RESET
N_PZ_445                              2     3     FB6_5           
N_PZ_513                              2     2     FB6_6           
N_PZ_428                              2     2     FB6_7           
OutFF_or000049                        1     2     FB6_8           
OutFF_or000041                        1     2     FB6_9           
OutFF_or000048                        1     2     FB6_10          
OutFF_or000040                        1     2     FB6_11          
DirKeyInstance/ShRegister<2>          3     3     FB6_12  DFF     RESET
OutFF_or000047                        1     2     FB6_13          
DirKeyInstance/ShRegister<1>          3     3     FB6_14  DFF     RESET
OutFF_or000039                        1     2     FB6_15          
FDiv<6>                               3     8     FB6_16  TFF     RESET
DirKeyStatus                          2     4     FB7_7   LATCH   RESET
ModeKeyStatus                         2     4     FB7_8   LATCH   RESET
ModeKeyInstance/ShRegister<3>         3     3     FB7_9   DFF     RESET
ModeKeyInstance/ShRegister<2>         3     3     FB7_10  DFF     RESET
ModeKeyInstance/ShRegister<1>         3     3     FB7_15  DFF     RESET
DirKeyInstance/ShRegister<3>          3     3     FB7_16  DFF     RESET
ModeKeyInstance/ShRegister<0>         2     2     FB13_13 DFF     RESET
DirKeyInstance/ShRegister<0>          2     2     FB15_11 DFF     RESET

** 6 Inputs **

Signal                                Loc     Pin   Pin       Pin     I/O      I/O
Name                                          No.   Type      Use     STD      Style
Clk                                   FB5_6   22    GCK/I/O   GCK/I   LVCMOS18 KPR
Reset                                 FB12_15 65    I/O       I       LVCMOS18 KPR
SetKeyInp                             FB13_6  55    I/O       I       LVCMOS18 KPR
ModeKeyInp                            FB13_13 56    I/O       I       LVCMOS18 KPR
SpeedKeyInp                           FB14_5  49    I/O       I       LVCMOS18 KPR
DirKeyInp                             FB15_11 58    I/O       I       LVCMOS18 KPR

Legend:
Pin No.   - ~     - User Assigned
I/O Style - OD    - OpenDrain
          - PU    - Pullup
          - KPR   - Keeper
          - S     - SchmittTrigger
          - DG    - DataGate
Reg Use   - LATCH - Transparent latch
          - DFF   - D-flip-flop
          - DEFF  - D-flip-flop with clock enable
          - TFF   - T-flip-flop
          - TDFF  - Dual-edge-triggered T-flip-flop
          - DDFF  - Dual-edge-triggered flip-flop
          - DDEFF - Dual-edge-triggered flip-flop with clock enable
          /S (after any above flop/latch type) indicates initial state is Set
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
              VRF - Vref
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               34/6
Number of function block control terms used/remaining:        3/1
Number of PLA product terms used/remaining:                   54/2
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
UCmpReg<5>                    4     FB1_1        (b)     (b)    +   +      
LCmpReg<5>                    4     FB1_2        (b)     (b)    +   +      
BinCnt<7>                     6     FB1_3   99   GSR/I/O (b)        +      
UCmpReg<6>                    4     FB1_4        (b)     (b)    +   +      
UCmpReg<7>                    4     FB1_5        (b)     (b)    +       +  
UCmpReg<3>                    4     FB1_6   97   I/O     (b)    +   +      
LCmpReg<6>                    4     FB1_7        (b)     (b)    +   +      
LCmpReg<7>                    4     FB1_8        (b)     (b)    +       +  
Mcompar_BinCnt_cmp_eq0000_AEB_or0000
                              16    FB1_9        (b)     (b)               
N_PZ_556                      2     FB1_10       (b)     (b)               
N_PZ_542                      2     FB1_11       (b)     (b)               
LCmpReg<3>                    4     FB1_12  96   I/O     (b)    +   +      
UCmpReg<4>                    4     FB1_13  95   I/O     (b)    +   +      
LCmpReg<4>                    4     FB1_14  94   I/O     (b)    +   +      
N_PZ_540                      2     FB1_15       (b)     (b)               
N_PZ_592                      4     FB1_16       (b)     (b)               

Signals Used by Logic in Function Block
  1: BinCnt<0>         13: LCmpReg<1>                  24: N_PZ_528 
  2: BinCnt<1>         14: LCmpReg<2>                  25: Reset 
  3: BinCnt<2>         15: LCmpReg<3>                  26: SetKeyStatus 
  4: BinCnt<3>         16: LCmpReg<4>                  27: UCmpReg<0> 
  5: BinCnt<4>         17: LCmpReg<5>                  28: UCmpReg<1> 
  6: BinCnt<5>         18: LCmpReg<6>                  29: UCmpReg<2> 
  7: BinCnt<6>         19: LCmpReg<7>                  30: UCmpReg<3> 
  8: BinCnt<7>         20: MuxDisplInstance/SelCnt<0>  31: UCmpReg<4> 
  9: Context_FFd1      21: MuxDisplInstance/SelCnt<1>  32: UCmpReg<5> 
 10: Context_FFd2      22: N_PZ_445                    33: UCmpReg<6> 
 11: DirLed            23: N_PZ_514                    34: UCmpReg<7> 
 12: LCmpReg<0>       

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
UCmpReg<5>        ........X.X.............XXXXXXX......... 9       
LCmpReg<5>        .........XXXXXXX........XX.............. 9       
BinCnt<7>         ....XXXXXX...........XXXX............... 10      
UCmpReg<6>        ........X.X.............XXXXXXXX........ 10      
UCmpReg<7>        ........X.X.............XXXXXXXXX....... 11      
UCmpReg<3>        ........X.X.............XXXXX........... 7       
LCmpReg<6>        .........XXXXXXXX.......XX.............. 10      
LCmpReg<7>        .........XXXXXXXXX......XX.............. 11      
Mcompar_BinCnt_cmp_eq0000_AEB_or0000 
                  XXXXXXXX...XXXXXXXX..................... 16      
N_PZ_556          ...............XXXXXX.....XXXX.......... 10      
N_PZ_542          ...............XXXXXX.........XXXX...... 10      
LCmpReg<3>        .........XXXXX..........XX.............. 7       
UCmpReg<4>        ........X.X.............XXXXXX.......... 8       
LCmpReg<4>        .........XXXXXX.........XX.............. 8       
N_PZ_540          ...............XXXXXX.....XXXX.......... 10      
N_PZ_592          ...........XXXXXXXXXX.....XXXXXXXX...... 18      
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB2  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               28/12
Number of function block control terms used/remaining:        1/3
Number of PLA product terms used/remaining:                   56/0
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
Seg_K                         2     FB2_1   1    GTS/I/O O                 
(unused)                      0     FB2_2        (b)           
Seg_G                         11    FB2_3   2    GTS/I/O O                 
(unused)                      0     FB2_4        (b)           
Seg_F                         11    FB2_5   3    GTS/I/O O                 
(unused)                      0     FB2_6        (b)           
(unused)                      0     FB2_7        (b)           
(unused)                      0     FB2_8        (b)           
(unused)                      0     FB2_9        (b)           
FDivInstance/FDivCnt<1>       2     FB2_10       (b)     (b)        +      
FDivInstance/FDivCnt<0>       1     FB2_11       (b)     (b)        +      
Seg_E                         11    FB2_12  4    GTS/I/O O                 
Context_FFd1                  3     FB2_13       (b)     (b)        +      
Seg_D                         12    FB2_14  6    I/O     O                 
Seg_C                         10    FB2_15  7    I/O     O                 
Context_FFd2                  3     FB2_16       (b)     (b)        +      

Signals Used by Logic in Function Block
  1: Context_FFd1             11: LCmpReg<7>                  20: Reset 
  2: Context_FFd2             12: MachineState_FFd1           21: UCmpReg<0> 
  3: FDivInstance/FDivCnt<0>  13: MachineState_FFd2           22: UCmpReg<1> 
  4: LCmpReg<0>               14: MuxDisplInstance/SelCnt<0>  23: UCmpReg<2> 
  5: LCmpReg<1>               15: MuxDisplInstance/SelCnt<1>  24: UCmpReg<3> 
  6: LCmpReg<2>               16: N_PZ_540                    25: UCmpReg<4> 
  7: LCmpReg<3>               17: N_PZ_542                    26: UCmpReg<5> 
  8: LCmpReg<4>               18: N_PZ_556                    27: UCmpReg<6> 
  9: LCmpReg<5>               19: N_PZ_592                    28: UCmpReg<7> 
 10: LCmpReg<6>              

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
Seg_K             XX............X......................... 3       
Seg_G             ...XXXXXXXX..XX.X...XXXXXXXX............ 19      
Seg_F             ...XXXX.XXX..XXXX.X.XXXXXXXX............ 20      
FDivInstance/FDivCnt<1> 
                  ..X................X.................... 2       
FDivInstance/FDivCnt<0> 
                  ...................X.................... 1       
Seg_E             ...XXXXXX.X..XXX.X..XX.XXXXX............ 18      
Context_FFd1      .X.........XX......X.................... 4       
Seg_D             ...XXXXXXXX..XX..XX.XXXXXXXX............ 20      
Seg_C             ...XXXXXXXX..XXX....XXXXXXXX............ 19      
Context_FFd2      XX.........XX......X.................... 5       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB3  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               31/9
Number of function block control terms used/remaining:        2/2
Number of PLA product terms used/remaining:                   48/8
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
LCmpReg<1>                    4     FB3_1        (b)     (b)        +      
UCmpReg<1>                    4     FB3_2        (b)     (b)        +      
UCmpReg<2>                    4     FB3_3        (b)     (b)        +      
BinCnt<6>                     6     FB3_4        (b)     (b)    +   +      
UCmpReg<0>                    3     FB3_5   93   I/O     (b)        +      
BinCnt<5>                     6     FB3_6        (b)     (b)    +   +      
BinCnt<4>                     5     FB3_7        (b)     (b)    +   +      
BinCnt<3>                     6     FB3_8        (b)     (b)    +   +      
BinCnt<2>                     5     FB3_9        (b)     (b)    +   +      
BinCnt<0>                     4     FB3_10       (b)     (b)    +   +      
BinCnt<1>                     4     FB3_11       (b)     (b)    +   +      
LCmpReg<0>                    3     FB3_12  92   I/O     (b)        +      
N_PZ_429                      1     FB3_13       (b)     (b)               
N_PZ_528                      1     FB3_14  91   I/O     (b)               
N_PZ_514                      9     FB3_15       (b)     (b)               
LCmpReg<2>                    4     FB3_16  90   I/O     (b)        +      

Signals Used by Logic in Function Block
  1: BinCnt<0>         12: LCmpReg<1>                            22: OutFF_or000041 
  2: BinCnt<1>         13: Mcompar_BinCnt_cmp_eq0000_AEB_or0000  23: OutFF_or000047 
  3: BinCnt<2>         14: N_PZ_428                              24: OutFF_or000048 
  4: BinCnt<3>         15: N_PZ_429                              25: OutFF_or000049 
  5: BinCnt<4>         16: N_PZ_445                              26: OutSig 
  6: BinCnt<5>         17: N_PZ_513                              27: Reset 
  7: BinCnt<6>         18: N_PZ_514                              28: SetKeyStatus 
  8: Context_FFd1      19: N_PZ_528                              29: UCmpReg<0> 
  9: Context_FFd2      20: OutFF_or000039                        30: UCmpReg<1> 
 10: DirLed            21: OutFF_or000040                        31: UCmpReg<2> 
 11: LCmpReg<0>       

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
LCmpReg<1>        ........XXX...............XX............ 5       
UCmpReg<1>        .......X.X................XXX........... 5       
UCmpReg<2>        .......X.X................XXXX.......... 6       
BinCnt<6>         ....XXXXX......X.XX.......X............. 9       
UCmpReg<0>        .......X..................XX............ 3       
BinCnt<5>         ....XX.XX......X.XX.......X............. 8       
BinCnt<4>         ....X..XX......X.XX.......X............. 7       
BinCnt<3>         ..XX...XX.....XX.XX.......X............. 9       
BinCnt<2>         ..X....XX.....XX.X........X............. 7       
BinCnt<0>         X......XX......X.X........X............. 6       
BinCnt<1>         XX.....XX......X.X........X............. 7       
LCmpReg<0>        ........X.................XX............ 3       
N_PZ_429          XX.....XX............................... 4       
N_PZ_528          ..XX..........X......................... 3       
N_PZ_514          XXX.........XX..X..XXXXXXX..XXX......... 16      
LCmpReg<2>        ........XXXX..............XX............ 6       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB4  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               38/2
Number of function block control terms used/remaining:        2/2
Number of PLA product terms used/remaining:                   36/20
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
Seg_A                         11    FB4_1   8    I/O     O                 
Seg_B                         13    FB4_2   9    I/O     O                 
OutSig                        3     FB4_3   10   I/O     O          +      
(unused)                      0     FB4_4        (b)           
(unused)                      0     FB4_5   11   I/O           
(unused)                      0     FB4_6   12   I/O           
(unused)                      0     FB4_7        (b)           
(unused)                      0     FB4_8        (b)           
(unused)                      0     FB4_9        (b)           
SetKeyStatus                  3     FB4_10       (b)     (b)               
MachineState_FFd2             3     FB4_11       (b)     (b)        +      
MachineState_FFd1             3     FB4_12       (b)     (b)        +      
(unused)                      0     FB4_13  13   I/O           
FClk                          2     FB4_14       (b)     (b)        +      
MuxDisplInstance/SelCnt<0>    2     FB4_15       (b)     (b)    +   +      
MuxDisplInstance/SelCnt<1>    3     FB4_16       (b)     (b)    +   +      

Signals Used by Logic in Function Block
  1: Context_FFd1             14: LCmpReg<7>                  27: SetKeyStatus 
  2: Context_FFd2             15: MachineState_FFd1           28: SetupKeyInstance/AutomatState_FFd2 
  3: DirKeyStatus             16: MachineState_FFd2           29: SetupKeyInstance/AutomatState_FFd3 
  4: FDiv<3>                  17: ModeKeyStatus               30: SetupKeyInstance/AutomatState_FFd4 
  5: FDivInstance/FDivCnt<0>  18: MuxDisplInstance/SelCnt<0>  31: UCmpReg<0> 
  6: FDivInstance/FDivCnt<1>  19: MuxDisplInstance/SelCnt<1>  32: UCmpReg<1> 
  7: LCmpReg<0>               20: N_PZ_445                    33: UCmpReg<2> 
  8: LCmpReg<1>               21: N_PZ_514                    34: UCmpReg<3> 
  9: LCmpReg<2>               22: N_PZ_540                    35: UCmpReg<4> 
 10: LCmpReg<3>               23: N_PZ_542                    36: UCmpReg<5> 
 11: LCmpReg<4>               24: N_PZ_556                    37: UCmpReg<6> 
 12: LCmpReg<5>               25: N_PZ_592                    38: UCmpReg<7> 
 13: LCmpReg<6>               26: Reset                      

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
Seg_A             ......XXXXXXXX...XX..X.XX.....XXXXXXXX.. 21      
Seg_B             ......XXXXXXXX...XX..XXX......XXXXXXXX.. 21      
OutSig            XX.................XX....X.............. 5       
SetKeyStatus      .........................XXXXX.......... 5       
MachineState_FFd2 
                  ..X...........XXX........X.............. 5       
MachineState_FFd1 
                  ..X...........XXX........X.............. 5       
FClk              ....XX...................X.............. 3       
MuxDisplInstance/SelCnt<0> 
                  ...X.....................X.............. 2       
MuxDisplInstance/SelCnt<1> 
                  ...X.............X.......X.............. 3       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB5  ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               19/21
Number of function block control terms used/remaining:        2/2
Number of PLA product terms used/remaining:                   48/8
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
FDiv<1>                       3     FB5_1        (b)     (b)        +      
FDiv<0>                       2     FB5_2        (b)     (b)        +      
N_PZ_732                      1     FB5_3        (b)     (b)               
FDiv<3>                       3     FB5_4   23   GCK/I/O (b)        +      
SetupKeyInstance/DelayCnt<0>  3     FB5_5        (b)     (b)    +          
FDiv<2>                       3     FB5_6   22   GCK/I/O GCK/I      +      
SetupKeyInstance/DelayCnt<1>  3     FB5_7        (b)     (b)    +          
SetupKeyInstance/DelayCnt<2>  3     FB5_8        (b)     (b)    +          
SetupKeyInstance/DelayCnt<3>  3     FB5_9        (b)     (b)    +          
SetupKeyInstance/DelayCnt<4>  3     FB5_10       (b)     (b)    +          
SetupKeyInstance/AutomatState_FFd1
                              7     FB5_11       (b)     (b)        +      
SetupKeyInstance/AutomatState_FFd3
                              6     FB5_12       (b)     (b)        +      
SetupKeyInstance/AutomatState_FFd4
                              10    FB5_13       (b)     (b)        +      
SetupKeyInstance/AutomatState_FFd2
                              4     FB5_14       (b)     (b)        +      
SetupKeyInstance/DelayCntEnable
                              3     FB5_15       (b)     (b)               
SetupKeyInstance/DelayCntClear
                              3     FB5_16       (b)     (b)               

Signals Used by Logic in Function Block
  1: FClk               8: SetKeyInp                           14: SetupKeyInstance/DelayCnt<1> 
  2: FDiv<0>            9: SetupKeyInstance/AutomatState_FFd1  15: SetupKeyInstance/DelayCnt<2> 
  3: FDiv<1>           10: SetupKeyInstance/AutomatState_FFd2  16: SetupKeyInstance/DelayCnt<3> 
  4: FDiv<2>           11: SetupKeyInstance/AutomatState_FFd3  17: SetupKeyInstance/DelayCnt<4> 
  5: FDiv<6>           12: SetupKeyInstance/AutomatState_FFd4  18: SetupKeyInstance/DelayCntClear 
  6: N_PZ_732          13: SetupKeyInstance/DelayCnt<0>        19: SetupKeyInstance/DelayCntEnable 
  7: Reset            

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
FDiv<1>           XX....X................................. 3       
FDiv<0>           X.....X................................. 2       
N_PZ_732          ......X..........X...................... 2       
FDiv<3>           XXXX..X................................. 5       
SetupKeyInstance/DelayCnt<0> 
                  ....XX............X..................... 3       
FDiv<2>           XXX...X................................. 4       
SetupKeyInstance/DelayCnt<1> 
                  ....XX......X.....X..................... 4       
SetupKeyInstance/DelayCnt<2> 
                  ....XX......XX....X..................... 5       
SetupKeyInstance/DelayCnt<3> 
                  ....XX......XXX...X..................... 6       
SetupKeyInstance/DelayCnt<4> 
                  ....XX......XXXX..X..................... 7       
SetupKeyInstance/AutomatState_FFd1 
                  ......XXXXXXXXXXX....................... 11      
SetupKeyInstance/AutomatState_FFd3 
                  ......XXXXXXXXXXX....................... 11      
SetupKeyInstance/AutomatState_FFd4 
                  ......XXXXXXXXXXX....................... 11      
SetupKeyInstance/AutomatState_FFd2 
                  ......X.XXXXXXXXX....................... 10      
SetupKeyInstance/DelayCntEnable 
                  ......X.XXXX......X..................... 6       
SetupKeyInstance/DelayCntClear 
                  ......X.XXXX.....X...................... 6       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB6  ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               24/16
Number of function block control terms used/remaining:        3/1
Number of PLA product terms used/remaining:                   24/32
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
FDiv<5>                       3     FB6_1        (b)     (b)    +   +      
DSel2                         1     FB6_2   24   CDR/I/O O                 
FDiv<4>                       3     FB6_3        (b)     (b)    +   +      
DSel3                         1     FB6_4   27   GCK/I/O O                 
N_PZ_445                      2     FB6_5        (b)     (b)               
N_PZ_513                      2     FB6_6        (b)     (b)               
N_PZ_428                      2     FB6_7        (b)     (b)               
OutFF_or000049                1     FB6_8        (b)     (b)               
OutFF_or000041                1     FB6_9        (b)     (b)               
OutFF_or000048                1     FB6_10       (b)     (b)               
OutFF_or000040                1     FB6_11       (b)     (b)               
DirKeyInstance/ShRegister<2>  3     FB6_12  28   DGE/I/O (b)            +  
OutFF_or000047                1     FB6_13       (b)     (b)               
DirKeyInstance/ShRegister<1>  3     FB6_14  29   I/O     (b)            +  
OutFF_or000039                1     FB6_15       (b)     (b)               
FDiv<6>                       3     FB6_16  30   I/O     (b)    +   +      

Signals Used by Logic in Function Block
  1: BinCnt<3>                      9: FClk                        17: MuxDisplInstance/SelCnt<1> 
  2: BinCnt<4>                     10: FDiv<0>                     18: Reset 
  3: BinCnt<5>                     11: FDiv<1>                     19: SpeedKeyInp 
  4: BinCnt<6>                     12: FDiv<2>                     20: UCmpReg<3> 
  5: BinCnt<7>                     13: FDiv<3>                     21: UCmpReg<4> 
  6: Clk                           14: FDiv<4>                     22: UCmpReg<5> 
  7: DirKeyInstance/ShRegister<0>  15: FDiv<5>                     23: UCmpReg<6> 
  8: DirKeyInstance/ShRegister<1>  16: MuxDisplInstance/SelCnt<0>  24: UCmpReg<7> 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
FDiv<5>           ........XXXXXX...X...................... 7       
DSel2             ...............XX....................... 2       
FDiv<4>           ........XXXXX....X...................... 6       
DSel3             ...............XX....................... 2       
N_PZ_445          .....X......X.....X..................... 3       
N_PZ_513          .X..................X................... 2       
N_PZ_428          X..................X.................... 2       
OutFF_or000049    ....X..................X................ 2       
OutFF_or000041    ....X..................X................ 2       
OutFF_or000048    ...X..................X................. 2       
OutFF_or000040    ...X..................X................. 2       
DirKeyInstance/ShRegister<2> 
                  .......X.....X...X...................... 3       
OutFF_or000047    ..X..................X.................. 2       
DirKeyInstance/ShRegister<1> 
                  ......X......X...X...................... 3       
OutFF_or000039    ..X..................X.................. 2       
FDiv<6>           ........XXXXXXX..X...................... 8       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB7  ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               15/25
Number of function block control terms used/remaining:        3/1
Number of PLA product terms used/remaining:                   14/42
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB7_1        (b)           
(unused)                      0     FB7_2        (b)           
(unused)                      0     FB7_3        (b)           
(unused)                      0     FB7_4        (b)           
DSel1                         1     FB7_5   19   I/O     O                 
DSel0                         1     FB7_6   18   I/O     O                 
DirKeyStatus                  2     FB7_7        (b)     (b)        +      
ModeKeyStatus                 2     FB7_8        (b)     (b)               
ModeKeyInstance/ShRegister<3> 3     FB7_9        (b)     (b)    +       +  
ModeKeyInstance/ShRegister<2> 3     FB7_10       (b)     (b)    +       +  
DirLed                        2     FB7_11  17   I/O     O              +  
SpeedLed                      1     FB7_12  16   I/O     O                 
(unused)                      0     FB7_13  15   I/O           
(unused)                      0     FB7_14  14   I/O           
ModeKeyInstance/ShRegister<1> 3     FB7_15       (b)     (b)    +       +  
DirKeyInstance/ShRegister<3>  3     FB7_16       (b)     (b)    +       +  

Signals Used by Logic in Function Block
  1: DirKeyInstance/ShRegister<0>   6: MachineState_FFd1              11: ModeKeyInstance/ShRegister<3> 
  2: DirKeyInstance/ShRegister<1>   7: MachineState_FFd2              12: MuxDisplInstance/SelCnt<0> 
  3: DirKeyInstance/ShRegister<2>   8: ModeKeyInstance/ShRegister<0>  13: MuxDisplInstance/SelCnt<1> 
  4: DirKeyInstance/ShRegister<3>   9: ModeKeyInstance/ShRegister<1>  14: Reset 
  5: FDiv<4>                       10: ModeKeyInstance/ShRegister<2>  15: SpeedKeyInp 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
DSel1             ...........XX........................... 2       
DSel0             ...........XX........................... 2       
DirKeyStatus      XXXX.................................... 4       
ModeKeyStatus     .......XXXX............................. 4       
ModeKeyInstance/ShRegister<3> 
                  ....X....X...X.......................... 3       
ModeKeyInstance/ShRegister<2> 
                  ....X...X....X.......................... 3       
DirLed            .....XX......X.......................... 3       
SpeedLed          ..............X......................... 1       
ModeKeyInstance/ShRegister<1> 
                  ....X..X.....X.......................... 3       
DirKeyInstance/ShRegister<3> 
                  ..X.X........X.......................... 3       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB8  ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB8_1        (b)           
(unused)                      0     FB8_2        (b)           
(unused)                      0     FB8_3        (b)           
(unused)                      0     FB8_4        (b)           
(unused)                      0     FB8_5        (b)           
(unused)                      0     FB8_6   32   I/O           
(unused)                      0     FB8_7        (b)           
(unused)                      0     FB8_8        (b)           
(unused)                      0     FB8_9        (b)           
(unused)                      0     FB8_10       (b)           
(unused)                      0     FB8_11  33   I/O           
(unused)                      0     FB8_12  34   I/O           
(unused)                      0     FB8_13  35   I/O           
(unused)                      0     FB8_14  36   I/O           
(unused)                      0     FB8_15  37   I/O           
(unused)                      0     FB8_16       (b)           
*********************************** FB9  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB9_1   78   I/O           
(unused)                      0     FB9_2   79   I/O           
(unused)                      0     FB9_3        (b)           
(unused)                      0     FB9_4   80   I/O           
(unused)                      0     FB9_5        (b)           
(unused)                      0     FB9_6   81   I/O           
(unused)                      0     FB9_7        (b)           
(unused)                      0     FB9_8        (b)           
(unused)                      0     FB9_9        (b)           
(unused)                      0     FB9_10       (b)           
(unused)                      0     FB9_11       (b)           
(unused)                      0     FB9_12  82   I/O           
(unused)                      0     FB9_13       (b)           
(unused)                      0     FB9_14       (b)           
(unused)                      0     FB9_15       (b)           
(unused)                      0     FB9_16       (b)           
*********************************** FB10 ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB10_1  77   I/O           
(unused)                      0     FB10_2  76   I/O           
(unused)                      0     FB10_3  74   I/O           
(unused)                      0     FB10_4  73   I/O           
(unused)                      0     FB10_5  72   I/O           
(unused)                      0     FB10_6  71   I/O           
(unused)                      0     FB10_7       (b)           
(unused)                      0     FB10_8       (b)           
(unused)                      0     FB10_9       (b)           
(unused)                      0     FB10_10      (b)           
(unused)                      0     FB10_11      (b)           
(unused)                      0     FB10_12 70   I/O           
(unused)                      0     FB10_13      (b)           
(unused)                      0     FB10_14      (b)           
(unused)                      0     FB10_15      (b)           
(unused)                      0     FB10_16      (b)           
*********************************** FB11 ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB11_1       (b)           
(unused)                      0     FB11_2       (b)           
(unused)                      0     FB11_3       (b)           
(unused)                      0     FB11_4       (b)           
(unused)                      0     FB11_5       (b)           
(unused)                      0     FB11_6       (b)           
(unused)                      0     FB11_7       (b)           
(unused)                      0     FB11_8       (b)           
(unused)                      0     FB11_9       (b)           
(unused)                      0     FB11_10      (b)           
(unused)                      0     FB11_11 85   I/O           
(unused)                      0     FB11_12 86   I/O           
(unused)                      0     FB11_13 87   I/O           
(unused)                      0     FB11_14 89   I/O           
(unused)                      0     FB11_15      (b)           
(unused)                      0     FB11_16      (b)           
*********************************** FB12 ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB12_1       (b)           
(unused)                      0     FB12_2       (b)           
(unused)                      0     FB12_3       (b)           
(unused)                      0     FB12_4       (b)           
(unused)                      0     FB12_5       (b)           
(unused)                      0     FB12_6       (b)           
(unused)                      0     FB12_7       (b)           
(unused)                      0     FB12_8       (b)           
(unused)                      0     FB12_9       (b)           
(unused)                      0     FB12_10      (b)           
(unused)                      0     FB12_11 68   I/O           
(unused)                      0     FB12_12      (b)           
(unused)                      0     FB12_13 67   I/O           
(unused)                      0     FB12_14 66   I/O           
(unused)                      0     FB12_15 65   I/O     I     
(unused)                      0     FB12_16      (b)           
*********************************** FB13 ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               2/38
Number of function block control terms used/remaining:        2/2
Number of PLA product terms used/remaining:                   2/54
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB13_1       (b)           
(unused)                      0     FB13_2  53   I/O           
(unused)                      0     FB13_3       (b)           
(unused)                      0     FB13_4  54   I/O           
(unused)                      0     FB13_5       (b)           
(unused)                      0     FB13_6  55   I/O     I     
(unused)                      0     FB13_7       (b)           
(unused)                      0     FB13_8       (b)           
(unused)                      0     FB13_9       (b)           
(unused)                      0     FB13_10      (b)           
(unused)                      0     FB13_11      (b)           
(unused)                      0     FB13_12      (b)           
ModeKeyInstance/ShRegister<0> 2     FB13_13 56   I/O     I      +       +  
(unused)                      0     FB13_14      (b)           
(unused)                      0     FB13_15      (b)           
(unused)                      0     FB13_16      (b)           

Signals Used by Logic in Function Block
  1: FDiv<4>            2: Reset            

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB14 ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB14_1  52   I/O           
(unused)                      0     FB14_2       (b)           
(unused)                      0     FB14_3  50   I/O           
(unused)                      0     FB14_4       (b)           
(unused)                      0     FB14_5  49   I/O     I     
(unused)                      0     FB14_6       (b)           
(unused)                      0     FB14_7       (b)           
(unused)                      0     FB14_8       (b)           
(unused)                      0     FB14_9       (b)           
(unused)                      0     FB14_10      (b)           
(unused)                      0     FB14_11      (b)           
(unused)                      0     FB14_12      (b)           
(unused)                      0     FB14_13      (b)           
(unused)                      0     FB14_14 46   I/O           
(unused)                      0     FB14_15 44   I/O           
(unused)                      0     FB14_16      (b)           
*********************************** FB15 ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               2/38
Number of function block control terms used/remaining:        2/2
Number of PLA product terms used/remaining:                   2/54
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB15_1       (b)           
(unused)                      0     FB15_2       (b)           
(unused)                      0     FB15_3       (b)           
(unused)                      0     FB15_4       (b)           
(unused)                      0     FB15_5       (b)           
(unused)                      0     FB15_6       (b)           
(unused)                      0     FB15_7       (b)           
(unused)                      0     FB15_8       (b)           
(unused)                      0     FB15_9       (b)           
(unused)                      0     FB15_10      (b)           
DirKeyInstance/ShRegister<0>  2     FB15_11 58   I/O     I      +       +  
(unused)                      0     FB15_12 59   I/O           
(unused)                      0     FB15_13 60   I/O           
(unused)                      0     FB15_14 61   I/O           
(unused)                      0     FB15_15 63   I/O           
(unused)                      0     FB15_16 64   I/O           

Signals Used by Logic in Function Block
  1: FDiv<4>            2: Reset            

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB16 ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB16_1       (b)           
(unused)                      0     FB16_2       (b)           
(unused)                      0     FB16_3       (b)           
(unused)                      0     FB16_4       (b)           
(unused)                      0     FB16_5  43   I/O           
(unused)                      0     FB16_6  42   I/O           
(unused)                      0     FB16_7       (b)           
(unused)                      0     FB16_8       (b)           
(unused)                      0     FB16_9       (b)           
(unused)                      0     FB16_10      (b)           
(unused)                      0     FB16_11 41   I/O           
(unused)                      0     FB16_12 40   I/O           
(unused)                      0     FB16_13 39   I/O           
(unused)                      0     FB16_14      (b)           
(unused)                      0     FB16_15      (b)           
(unused)                      0     FB16_16      (b)           
*******************************  Equations  ********************************

********** Mapped Logic **********

FTCPE_BinCnt0: FTCPE port map (BinCnt(0),BinCnt_T(0),N_PZ_445,NOT Reset,'0','1');
BinCnt_T(0) <= ((NOT Context_FFd2 AND NOT Context_FFd1 AND NOT N_PZ_514)
	OR (NOT Context_FFd2 AND NOT Context_FFd1 AND BinCnt(0)));

FTCPE_BinCnt1: FTCPE port map (BinCnt(1),BinCnt_T(1),N_PZ_445,NOT Reset,'0','1');
BinCnt_T(1) <= ((NOT Context_FFd2 AND NOT Context_FFd1 AND N_PZ_514 AND 
	BinCnt(1))
	OR (NOT Context_FFd2 AND NOT Context_FFd1 AND NOT N_PZ_514 AND 
	BinCnt(0)));

FDCPE_BinCnt2: FDCPE port map (BinCnt(2),BinCnt_D(2),N_PZ_445,NOT Reset,'0','1');
BinCnt_D(2) <= NOT (((BinCnt(2) AND N_PZ_429)
	OR (NOT BinCnt(2) AND NOT N_PZ_429)
	OR (NOT Context_FFd2 AND NOT Context_FFd1 AND N_PZ_514)));

FDCPE_BinCnt3: FDCPE port map (BinCnt(3),BinCnt_D(3),N_PZ_445,NOT Reset,'0','1');
BinCnt_D(3) <= NOT (((N_PZ_528)
	OR (NOT BinCnt(2) AND NOT BinCnt(3))
	OR (NOT N_PZ_429 AND NOT BinCnt(3))
	OR (NOT Context_FFd2 AND NOT Context_FFd1 AND N_PZ_514)));

FDCPE_BinCnt4: FDCPE port map (BinCnt(4),BinCnt_D(4),N_PZ_445,NOT Reset,'0','1');
BinCnt_D(4) <= NOT (((N_PZ_528 AND BinCnt(4))
	OR (NOT N_PZ_528 AND NOT BinCnt(4))
	OR (NOT Context_FFd2 AND NOT Context_FFd1 AND N_PZ_514)));

FDCPE_BinCnt5: FDCPE port map (BinCnt(5),BinCnt_D(5),N_PZ_445,NOT Reset,'0','1');
BinCnt_D(5) <= NOT (((NOT N_PZ_528 AND NOT BinCnt(5))
	OR (NOT BinCnt(4) AND NOT BinCnt(5))
	OR (NOT Context_FFd2 AND NOT Context_FFd1 AND N_PZ_514)
	OR (N_PZ_528 AND BinCnt(4) AND BinCnt(5))));

FTCPE_BinCnt6: FTCPE port map (BinCnt(6),BinCnt_T(6),N_PZ_445,NOT Reset,'0','1');
BinCnt_T(6) <= ((Context_FFd2 AND N_PZ_528 AND BinCnt(4) AND BinCnt(5))
	OR (NOT Context_FFd2 AND NOT Context_FFd1 AND N_PZ_514 AND 
	BinCnt(6))
	OR (Context_FFd1 AND N_PZ_528 AND BinCnt(4) AND BinCnt(5))
	OR (NOT N_PZ_514 AND N_PZ_528 AND BinCnt(4) AND BinCnt(5)));

FTCPE_BinCnt7: FTCPE port map (BinCnt(7),BinCnt_T(7),N_PZ_445,NOT Reset,'0','1');
BinCnt_T(7) <= ((NOT Context_FFd2 AND NOT Context_FFd1 AND N_PZ_514 AND 
	BinCnt(7))
	OR (Context_FFd2 AND N_PZ_528 AND BinCnt(4) AND BinCnt(5) AND 
	BinCnt(6))
	OR (Context_FFd1 AND N_PZ_528 AND BinCnt(4) AND BinCnt(5) AND 
	BinCnt(6))
	OR (NOT N_PZ_514 AND N_PZ_528 AND BinCnt(4) AND BinCnt(5) AND 
	BinCnt(6)));

FDCPE_Context_FFd1: FDCPE port map (Context_FFd1,Context_FFd2,NOT Clk,NOT Reset,'0',Context_FFd1_CE);
Context_FFd1_CE <= (NOT MachineState_FFd1 AND MachineState_FFd2);

FTCPE_Context_FFd2: FTCPE port map (Context_FFd2,Context_FFd2_T,NOT Clk,NOT Reset,'0','1');
Context_FFd2_T <= ((NOT MachineState_FFd1 AND MachineState_FFd2 AND 
	Context_FFd2)
	OR (NOT MachineState_FFd1 AND MachineState_FFd2 AND 
	NOT Context_FFd1));


DSel0 <= (NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1));


DSel1 <= (MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1));


DSel2 <= (NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1));


DSel3 <= (MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1));

FDCPE_DirKeyInstance/ShRegister0: FDCPE port map (DirKeyInstance/ShRegister(0),DirKeyInp,FDiv(4),'0',NOT Reset,'1');

FDCPE_DirKeyInstance/ShRegister1: FDCPE port map (DirKeyInstance/ShRegister(1),DirKeyInstance/ShRegister(0),FDiv(4),'0',NOT Reset,'1');

FDCPE_DirKeyInstance/ShRegister2: FDCPE port map (DirKeyInstance/ShRegister(2),DirKeyInstance/ShRegister(1),FDiv(4),'0',NOT Reset,'1');

FDCPE_DirKeyInstance/ShRegister3: FDCPE port map (DirKeyInstance/ShRegister(3),DirKeyInstance/ShRegister(2),FDiv(4),'0',NOT Reset,'1');

LDCP_DirKeyStatus: LDCP port map (DirKeyStatus,NOT '0',,DirKeyStatus_CLR,'0');
DirKeyStatus_G <= (NOT DirKeyInstance/ShRegister(0) AND 
	NOT DirKeyInstance/ShRegister(1) AND NOT DirKeyInstance/ShRegister(2) AND 
	NOT DirKeyInstance/ShRegister(3));
DirKeyStatus_CLR <= (DirKeyInstance/ShRegister(0) AND 
	DirKeyInstance/ShRegister(1) AND DirKeyInstance/ShRegister(2) AND 
	DirKeyInstance/ShRegister(3));

FTCPE_DirLed: FTCPE port map (DirLed,DirLed_T,NOT Clk,'0',NOT Reset,'1');
DirLed_T <= (MachineState_FFd1 AND MachineState_FFd2);

FTCPE_FClk: FTCPE port map (FClk,FClk_T,NOT Clk,NOT Reset,'0','1');
FClk_T <= (FDivInstance/FDivCnt(0) AND FDivInstance/FDivCnt(1));

FTCPE_FDiv0: FTCPE port map (FDiv(0),'0',FClk,NOT Reset,'0','1');

FTCPE_FDiv1: FTCPE port map (FDiv(1),FDiv(0),FClk,NOT Reset,'0','1');

FTCPE_FDiv2: FTCPE port map (FDiv(2),FDiv_T(2),FClk,NOT Reset,'0','1');
FDiv_T(2) <= (FDiv(0) AND FDiv(1));

FTCPE_FDiv3: FTCPE port map (FDiv(3),FDiv_T(3),FClk,NOT Reset,'0','1');
FDiv_T(3) <= (FDiv(0) AND FDiv(1) AND FDiv(2));

FTCPE_FDiv4: FTCPE port map (FDiv(4),FDiv_T(4),FClk,NOT Reset,'0','1');
FDiv_T(4) <= (FDiv(3) AND FDiv(0) AND FDiv(1) AND FDiv(2));

FTCPE_FDiv5: FTCPE port map (FDiv(5),FDiv_T(5),FClk,NOT Reset,'0','1');
FDiv_T(5) <= (FDiv(3) AND FDiv(0) AND FDiv(1) AND FDiv(2) AND 
	FDiv(4));

FTCPE_FDiv6: FTCPE port map (FDiv(6),FDiv_T(6),FClk,NOT Reset,'0','1');
FDiv_T(6) <= (FDiv(3) AND FDiv(0) AND FDiv(1) AND FDiv(2) AND 
	FDiv(4) AND FDiv(5));

FTCPE_FDivInstance/FDivCnt0: FTCPE port map (FDivInstance/FDivCnt(0),'0',NOT Clk,NOT Reset,'0','1');

FTCPE_FDivInstance/FDivCnt1: FTCPE port map (FDivInstance/FDivCnt(1),FDivInstance/FDivCnt(0),NOT Clk,NOT Reset,'0','1');

FTCPE_LCmpReg0: FTCPE port map (LCmpReg(0),Context_FFd2,SetKeyStatus,NOT Reset,'0','1');

FTCPE_LCmpReg1: FTCPE port map (LCmpReg(1),LCmpReg_T(1),SetKeyStatus,NOT Reset,'0','1');
LCmpReg_T(1) <= ((Context_FFd2 AND LCmpReg(0) AND DirLed)
	OR (Context_FFd2 AND NOT LCmpReg(0) AND NOT DirLed));

FTCPE_LCmpReg2: FTCPE port map (LCmpReg(2),LCmpReg_T(2),SetKeyStatus,NOT Reset,'0','1');
LCmpReg_T(2) <= ((Context_FFd2 AND LCmpReg(0) AND LCmpReg(1) AND DirLed)
	OR (Context_FFd2 AND NOT LCmpReg(0) AND NOT LCmpReg(1) AND NOT DirLed));

FTCPE_LCmpReg3: FTCPE port map (LCmpReg(3),LCmpReg_T(3),SetKeyStatus,NOT Reset,'0','1');
LCmpReg_T(3) <= ((Context_FFd2 AND LCmpReg(0) AND LCmpReg(1) AND DirLed AND 
	LCmpReg(2))
	OR (Context_FFd2 AND NOT LCmpReg(0) AND NOT LCmpReg(1) AND NOT DirLed AND 
	NOT LCmpReg(2)));

FTCPE_LCmpReg4: FTCPE port map (LCmpReg(4),LCmpReg_T(4),SetKeyStatus,NOT Reset,'0','1');
LCmpReg_T(4) <= ((Context_FFd2 AND LCmpReg(0) AND LCmpReg(1) AND DirLed AND 
	LCmpReg(2) AND LCmpReg(3))
	OR (Context_FFd2 AND NOT LCmpReg(0) AND NOT LCmpReg(1) AND NOT DirLed AND 
	NOT LCmpReg(2) AND NOT LCmpReg(3)));

FTCPE_LCmpReg5: FTCPE port map (LCmpReg(5),LCmpReg_T(5),SetKeyStatus,NOT Reset,'0','1');
LCmpReg_T(5) <= ((Context_FFd2 AND LCmpReg(0) AND LCmpReg(1) AND DirLed AND 
	LCmpReg(2) AND LCmpReg(3) AND LCmpReg(4))
	OR (Context_FFd2 AND NOT LCmpReg(0) AND NOT LCmpReg(1) AND NOT DirLed AND 
	NOT LCmpReg(2) AND NOT LCmpReg(3) AND NOT LCmpReg(4)));

FTCPE_LCmpReg6: FTCPE port map (LCmpReg(6),LCmpReg_T(6),SetKeyStatus,NOT Reset,'0','1');
LCmpReg_T(6) <= ((Context_FFd2 AND LCmpReg(0) AND LCmpReg(1) AND DirLed AND 
	LCmpReg(2) AND LCmpReg(3) AND LCmpReg(4) AND LCmpReg(5))
	OR (Context_FFd2 AND NOT LCmpReg(0) AND NOT LCmpReg(1) AND NOT DirLed AND 
	NOT LCmpReg(2) AND NOT LCmpReg(3) AND NOT LCmpReg(4) AND NOT LCmpReg(5)));

FTCPE_LCmpReg7: FTCPE port map (LCmpReg(7),LCmpReg_T(7),SetKeyStatus,'0',NOT Reset,'1');
LCmpReg_T(7) <= ((Context_FFd2 AND LCmpReg(0) AND LCmpReg(1) AND DirLed AND 
	LCmpReg(2) AND LCmpReg(3) AND LCmpReg(4) AND LCmpReg(5) AND 
	LCmpReg(6))
	OR (Context_FFd2 AND NOT LCmpReg(0) AND NOT LCmpReg(1) AND NOT DirLed AND 
	NOT LCmpReg(2) AND NOT LCmpReg(3) AND NOT LCmpReg(4) AND NOT LCmpReg(5) AND 
	NOT LCmpReg(6)));

FDCPE_MachineState_FFd1: FDCPE port map (MachineState_FFd1,MachineState_FFd1_D,NOT Clk,NOT Reset,'0','1');
MachineState_FFd1_D <= NOT (((NOT MachineState_FFd1 AND NOT MachineState_FFd2 AND 
	ModeKeyStatus)
	OR (NOT MachineState_FFd2 AND NOT ModeKeyStatus AND NOT DirKeyStatus)));

FDCPE_MachineState_FFd2: FDCPE port map (MachineState_FFd2,MachineState_FFd2_D,NOT Clk,NOT Reset,'0','1');
MachineState_FFd2_D <= ((NOT MachineState_FFd1 AND NOT MachineState_FFd2 AND 
	ModeKeyStatus)
	OR (NOT MachineState_FFd1 AND NOT MachineState_FFd2 AND 
	DirKeyStatus));


Mcompar_BinCnt_cmp_eq0000_AEB_or0000 <= ((BinCnt(0) AND NOT LCmpReg(0))
	OR (NOT BinCnt(0) AND LCmpReg(0))
	OR (BinCnt(1) AND NOT LCmpReg(1))
	OR (NOT BinCnt(1) AND LCmpReg(1))
	OR (BinCnt(2) AND NOT LCmpReg(2))
	OR (NOT BinCnt(2) AND LCmpReg(2))
	OR (BinCnt(3) AND NOT LCmpReg(3))
	OR (NOT BinCnt(3) AND LCmpReg(3))
	OR (BinCnt(4) AND NOT LCmpReg(4))
	OR (NOT BinCnt(4) AND LCmpReg(4))
	OR (BinCnt(5) AND NOT LCmpReg(5))
	OR (NOT BinCnt(5) AND LCmpReg(5))
	OR (BinCnt(6) AND NOT LCmpReg(6))
	OR (NOT BinCnt(6) AND LCmpReg(6))
	OR (BinCnt(7) AND NOT LCmpReg(7))
	OR (NOT BinCnt(7) AND LCmpReg(7)));

FDCPE_ModeKeyInstance/ShRegister0: FDCPE port map (ModeKeyInstance/ShRegister(0),ModeKeyInp,FDiv(4),'0',NOT Reset,'1');

FDCPE_ModeKeyInstance/ShRegister1: FDCPE port map (ModeKeyInstance/ShRegister(1),ModeKeyInstance/ShRegister(0),FDiv(4),'0',NOT Reset,'1');

FDCPE_ModeKeyInstance/ShRegister2: FDCPE port map (ModeKeyInstance/ShRegister(2),ModeKeyInstance/ShRegister(1),FDiv(4),'0',NOT Reset,'1');

FDCPE_ModeKeyInstance/ShRegister3: FDCPE port map (ModeKeyInstance/ShRegister(3),ModeKeyInstance/ShRegister(2),FDiv(4),'0',NOT Reset,'1');

LDCP_ModeKeyStatus: LDCP port map (ModeKeyStatus,NOT '0',,ModeKeyStatus_CLR,'0');
ModeKeyStatus_G <= (NOT ModeKeyInstance/ShRegister(0) AND 
	NOT ModeKeyInstance/ShRegister(1) AND NOT ModeKeyInstance/ShRegister(2) AND 
	NOT ModeKeyInstance/ShRegister(3));
ModeKeyStatus_CLR <= (ModeKeyInstance/ShRegister(0) AND 
	ModeKeyInstance/ShRegister(1) AND ModeKeyInstance/ShRegister(2) AND 
	ModeKeyInstance/ShRegister(3));

FTCPE_MuxDisplInstance/SelCnt0: FTCPE port map (MuxDisplInstance/SelCnt(0),'0',FDiv(3),NOT Reset,'0','1');

FTCPE_MuxDisplInstance/SelCnt1: FTCPE port map (MuxDisplInstance/SelCnt(1),MuxDisplInstance/SelCnt(0),FDiv(3),NOT Reset,'0','1');


N_PZ_428 <= ((BinCnt(3) AND NOT UCmpReg(3))
	OR (NOT BinCnt(3) AND UCmpReg(3)));


N_PZ_429 <= (NOT Context_FFd2 AND NOT Context_FFd1 AND BinCnt(0) AND 
	BinCnt(1));


N_PZ_445 <= ((FDiv(3) AND NOT SpeedKeyInp)
	OR (Clk AND SpeedKeyInp));


N_PZ_513 <= ((BinCnt(4) AND NOT UCmpReg(4))
	OR (NOT BinCnt(4) AND UCmpReg(4)));


N_PZ_514 <= ((NOT OutSig AND NOT Mcompar_BinCnt_cmp_eq0000_AEB_or0000)
	OR (OutSig AND BinCnt(0) AND BinCnt(1) AND BinCnt(2) AND 
	UCmpReg(0) AND UCmpReg(1) AND UCmpReg(2) AND NOT OutFF_or000039 AND 
	NOT OutFF_or000040 AND NOT OutFF_or000041 AND NOT OutFF_or000047 AND NOT OutFF_or000048 AND 
	NOT OutFF_or000049 AND NOT N_PZ_428 AND NOT N_PZ_513)
	OR (OutSig AND BinCnt(0) AND BinCnt(1) AND NOT BinCnt(2) AND 
	UCmpReg(0) AND UCmpReg(1) AND NOT UCmpReg(2) AND NOT OutFF_or000039 AND 
	NOT OutFF_or000040 AND NOT OutFF_or000041 AND NOT OutFF_or000047 AND NOT OutFF_or000048 AND 
	NOT OutFF_or000049 AND NOT N_PZ_428 AND NOT N_PZ_513)
	OR (OutSig AND BinCnt(0) AND NOT BinCnt(1) AND BinCnt(2) AND 
	UCmpReg(0) AND NOT UCmpReg(1) AND UCmpReg(2) AND NOT OutFF_or000039 AND 
	NOT OutFF_or000040 AND NOT OutFF_or000041 AND NOT OutFF_or000047 AND NOT OutFF_or000048 AND 
	NOT OutFF_or000049 AND NOT N_PZ_428 AND NOT N_PZ_513)
	OR (OutSig AND BinCnt(0) AND NOT BinCnt(1) AND NOT BinCnt(2) AND 
	UCmpReg(0) AND NOT UCmpReg(1) AND NOT UCmpReg(2) AND NOT OutFF_or000039 AND 
	NOT OutFF_or000040 AND NOT OutFF_or000041 AND NOT OutFF_or000047 AND NOT OutFF_or000048 AND 
	NOT OutFF_or000049 AND NOT N_PZ_428 AND NOT N_PZ_513)
	OR (OutSig AND NOT BinCnt(0) AND BinCnt(1) AND BinCnt(2) AND 
	NOT UCmpReg(0) AND UCmpReg(1) AND UCmpReg(2) AND NOT OutFF_or000039 AND 
	NOT OutFF_or000040 AND NOT OutFF_or000041 AND NOT OutFF_or000047 AND NOT OutFF_or000048 AND 
	NOT OutFF_or000049 AND NOT N_PZ_428 AND NOT N_PZ_513)
	OR (OutSig AND NOT BinCnt(0) AND BinCnt(1) AND NOT BinCnt(2) AND 
	NOT UCmpReg(0) AND UCmpReg(1) AND NOT UCmpReg(2) AND NOT OutFF_or000039 AND 
	NOT OutFF_or000040 AND NOT OutFF_or000041 AND NOT OutFF_or000047 AND NOT OutFF_or000048 AND 
	NOT OutFF_or000049 AND NOT N_PZ_428 AND NOT N_PZ_513)
	OR (OutSig AND NOT BinCnt(0) AND NOT BinCnt(1) AND BinCnt(2) AND 
	NOT UCmpReg(0) AND NOT UCmpReg(1) AND UCmpReg(2) AND NOT OutFF_or000039 AND 
	NOT OutFF_or000040 AND NOT OutFF_or000041 AND NOT OutFF_or000047 AND NOT OutFF_or000048 AND 
	NOT OutFF_or000049 AND NOT N_PZ_428 AND NOT N_PZ_513)
	OR (OutSig AND NOT BinCnt(0) AND NOT BinCnt(1) AND NOT BinCnt(2) AND 
	NOT UCmpReg(0) AND NOT UCmpReg(1) AND NOT UCmpReg(2) AND NOT OutFF_or000039 AND 
	NOT OutFF_or000040 AND NOT OutFF_or000041 AND NOT OutFF_or000047 AND NOT OutFF_or000048 AND 
	NOT OutFF_or000049 AND NOT N_PZ_428 AND NOT N_PZ_513));


N_PZ_528 <= (BinCnt(2) AND N_PZ_429 AND BinCnt(3));


N_PZ_540 <= ((MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND LCmpReg(4) AND NOT LCmpReg(5) AND LCmpReg(6) AND 
	LCmpReg(7))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND UCmpReg(0) AND NOT UCmpReg(1) AND UCmpReg(2) AND 
	UCmpReg(3)));


N_PZ_542 <= ((MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND UCmpReg(5) AND UCmpReg(4) AND UCmpReg(6) AND 
	NOT UCmpReg(7))
	OR (MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND LCmpReg(4) AND LCmpReg(5) AND LCmpReg(6) AND 
	NOT LCmpReg(7)));


N_PZ_556 <= ((MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND NOT LCmpReg(4) AND NOT LCmpReg(5) AND LCmpReg(6) AND 
	NOT LCmpReg(7))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND NOT UCmpReg(0) AND NOT UCmpReg(1) AND UCmpReg(2) AND 
	NOT UCmpReg(3)));


N_PZ_592 <= ((MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND NOT UCmpReg(5) AND UCmpReg(4) AND NOT UCmpReg(6) AND 
	NOT UCmpReg(7))
	OR (MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND LCmpReg(4) AND NOT LCmpReg(5) AND NOT LCmpReg(6) AND 
	NOT LCmpReg(7))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND UCmpReg(0) AND NOT UCmpReg(1) AND NOT UCmpReg(2) AND 
	NOT UCmpReg(3))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND LCmpReg(0) AND NOT LCmpReg(1) AND NOT LCmpReg(2) AND 
	NOT LCmpReg(3)));


N_PZ_732 <= (Reset AND SetupKeyInstance/DelayCntClear);


OutFF_or000039 <= (BinCnt(5) AND NOT UCmpReg(5));


OutFF_or000040 <= (BinCnt(6) AND NOT UCmpReg(6));


OutFF_or000041 <= (BinCnt(7) AND NOT UCmpReg(7));


OutFF_or000047 <= (NOT BinCnt(5) AND UCmpReg(5));


OutFF_or000048 <= (NOT BinCnt(6) AND UCmpReg(6));


OutFF_or000049 <= (NOT BinCnt(7) AND UCmpReg(7));

FTCPE_OutSig: FTCPE port map (OutSig,OutSig_T,N_PZ_445,NOT Reset,'0','1');
OutSig_T <= (NOT Context_FFd2 AND NOT Context_FFd1 AND N_PZ_514);


Seg_A <= NOT (((N_PZ_540)
	OR (N_PZ_556)
	OR (N_PZ_592)
	OR (MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND UCmpReg(5) AND UCmpReg(4) AND NOT UCmpReg(6) AND 
	UCmpReg(7))
	OR (MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND NOT UCmpReg(5) AND UCmpReg(4) AND UCmpReg(6) AND 
	UCmpReg(7))
	OR (MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND NOT UCmpReg(5) AND NOT UCmpReg(4) AND UCmpReg(6) AND 
	NOT UCmpReg(7))
	OR (MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND LCmpReg(4) AND LCmpReg(5) AND NOT LCmpReg(6) AND 
	LCmpReg(7))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND UCmpReg(0) AND UCmpReg(1) AND NOT UCmpReg(2) AND 
	UCmpReg(3))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND LCmpReg(0) AND LCmpReg(1) AND NOT LCmpReg(2) AND 
	LCmpReg(3))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND LCmpReg(0) AND NOT LCmpReg(1) AND LCmpReg(2) AND 
	LCmpReg(3))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND NOT LCmpReg(0) AND NOT LCmpReg(1) AND LCmpReg(2) AND 
	NOT LCmpReg(3))));


Seg_B <= NOT (((MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND UCmpReg(5) AND UCmpReg(4) AND UCmpReg(7))
	OR (MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND UCmpReg(5) AND UCmpReg(6) AND NOT N_PZ_542)
	OR (MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND NOT UCmpReg(4) AND UCmpReg(6) AND UCmpReg(7))
	OR (MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND LCmpReg(4) AND LCmpReg(5) AND LCmpReg(7))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND UCmpReg(0) AND UCmpReg(1) AND UCmpReg(3))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND NOT UCmpReg(0) AND UCmpReg(2) AND NOT N_PZ_556)
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND LCmpReg(0) AND LCmpReg(1) AND LCmpReg(3))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND NOT LCmpReg(0) AND LCmpReg(1) AND LCmpReg(2))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND NOT LCmpReg(0) AND LCmpReg(2) AND LCmpReg(3))
	OR (MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND UCmpReg(4) AND UCmpReg(6) AND NOT UCmpReg(7) AND NOT N_PZ_542)
	OR (MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND LCmpReg(6) AND NOT N_PZ_540 AND NOT N_PZ_556 AND NOT N_PZ_542)
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND NOT UCmpReg(1) AND UCmpReg(2) AND NOT N_PZ_540 AND NOT N_PZ_556)
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND LCmpReg(0) AND NOT LCmpReg(1) AND LCmpReg(2) AND 
	NOT LCmpReg(3))));


Seg_C <= NOT (((MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND UCmpReg(5) AND UCmpReg(6) AND UCmpReg(7))
	OR (MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND NOT UCmpReg(4) AND UCmpReg(6) AND UCmpReg(7))
	OR (MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND LCmpReg(6) AND LCmpReg(7) AND NOT N_PZ_540)
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND UCmpReg(2) AND UCmpReg(3) AND NOT N_PZ_540)
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND NOT LCmpReg(0) AND LCmpReg(2) AND LCmpReg(3))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND LCmpReg(1) AND LCmpReg(2) AND LCmpReg(3))
	OR (MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND UCmpReg(5) AND NOT UCmpReg(4) AND NOT UCmpReg(6) AND 
	NOT UCmpReg(7))
	OR (MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND NOT LCmpReg(4) AND LCmpReg(5) AND NOT LCmpReg(6) AND 
	NOT LCmpReg(7))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND NOT UCmpReg(0) AND UCmpReg(1) AND NOT UCmpReg(2) AND 
	NOT UCmpReg(3))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND NOT LCmpReg(0) AND LCmpReg(1) AND NOT LCmpReg(2) AND 
	NOT LCmpReg(3))));


Seg_D <= NOT (((N_PZ_556)
	OR (N_PZ_592)
	OR (MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND UCmpReg(5) AND UCmpReg(4) AND UCmpReg(6))
	OR (MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND LCmpReg(4) AND LCmpReg(5) AND LCmpReg(6))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND UCmpReg(0) AND UCmpReg(1) AND UCmpReg(2))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND LCmpReg(0) AND LCmpReg(1) AND LCmpReg(2))
	OR (MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND UCmpReg(5) AND NOT UCmpReg(4) AND NOT UCmpReg(6) AND 
	UCmpReg(7))
	OR (MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND NOT UCmpReg(5) AND NOT UCmpReg(4) AND UCmpReg(6) AND 
	NOT UCmpReg(7))
	OR (MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND NOT LCmpReg(4) AND LCmpReg(5) AND NOT LCmpReg(6) AND 
	LCmpReg(7))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND NOT UCmpReg(0) AND UCmpReg(1) AND NOT UCmpReg(2) AND 
	UCmpReg(3))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND NOT LCmpReg(0) AND LCmpReg(1) AND NOT LCmpReg(2) AND 
	LCmpReg(3))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND NOT LCmpReg(0) AND NOT LCmpReg(1) AND LCmpReg(2) AND 
	NOT LCmpReg(3))));


Seg_E <= NOT (((N_PZ_556)
	OR (MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND UCmpReg(4) AND NOT UCmpReg(7))
	OR (MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND LCmpReg(4) AND NOT LCmpReg(7))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND UCmpReg(0) AND NOT UCmpReg(3))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND LCmpReg(0) AND NOT LCmpReg(3))
	OR (MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND NOT UCmpReg(5) AND UCmpReg(4) AND NOT UCmpReg(6))
	OR (MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND LCmpReg(4) AND NOT LCmpReg(5) AND NOT N_PZ_540)
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND UCmpReg(0) AND NOT UCmpReg(1) AND NOT N_PZ_540)
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND LCmpReg(0) AND NOT LCmpReg(1) AND NOT LCmpReg(2))
	OR (MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND NOT UCmpReg(5) AND NOT UCmpReg(4) AND UCmpReg(6) AND 
	NOT UCmpReg(7))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND NOT LCmpReg(0) AND NOT LCmpReg(1) AND LCmpReg(2) AND 
	NOT LCmpReg(3))));


Seg_F <= NOT (((N_PZ_540)
	OR (N_PZ_592)
	OR (N_PZ_542)
	OR (MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND UCmpReg(5) AND NOT UCmpReg(6) AND NOT UCmpReg(7))
	OR (MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND LCmpReg(5) AND NOT LCmpReg(6) AND NOT LCmpReg(7))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND UCmpReg(1) AND NOT UCmpReg(2) AND NOT UCmpReg(3))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND LCmpReg(1) AND NOT LCmpReg(2) AND NOT LCmpReg(3))
	OR (MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND NOT UCmpReg(5) AND UCmpReg(4) AND UCmpReg(6) AND 
	UCmpReg(7))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND UCmpReg(0) AND UCmpReg(1) AND UCmpReg(2) AND 
	NOT UCmpReg(3))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND LCmpReg(0) AND LCmpReg(1) AND LCmpReg(2) AND 
	NOT LCmpReg(3))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND LCmpReg(0) AND NOT LCmpReg(1) AND LCmpReg(2) AND 
	LCmpReg(3))));


Seg_G <= NOT (((N_PZ_542)
	OR (MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND NOT UCmpReg(5) AND NOT UCmpReg(6) AND NOT UCmpReg(7))
	OR (MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND NOT LCmpReg(5) AND NOT LCmpReg(6) AND NOT LCmpReg(7))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND NOT UCmpReg(1) AND NOT UCmpReg(2) AND NOT UCmpReg(3))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND NOT LCmpReg(1) AND NOT LCmpReg(2) AND NOT LCmpReg(3))
	OR (MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND NOT UCmpReg(5) AND NOT UCmpReg(4) AND UCmpReg(6) AND 
	UCmpReg(7))
	OR (MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND NOT LCmpReg(4) AND NOT LCmpReg(5) AND LCmpReg(6) AND 
	LCmpReg(7))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND UCmpReg(0) AND UCmpReg(1) AND UCmpReg(2) AND 
	NOT UCmpReg(3))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND NOT UCmpReg(0) AND NOT UCmpReg(1) AND UCmpReg(2) AND 
	UCmpReg(3))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND LCmpReg(0) AND LCmpReg(1) AND LCmpReg(2) AND 
	NOT LCmpReg(3))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND NOT LCmpReg(0) AND NOT LCmpReg(1) AND LCmpReg(2) AND 
	LCmpReg(3))));


Seg_K <= NOT (((MuxDisplInstance/SelCnt(1) AND NOT Context_FFd1)
	OR (NOT MuxDisplInstance/SelCnt(1) AND NOT Context_FFd2)));

FDCPE_SetKeyStatus: FDCPE port map (SetKeyStatus,SetKeyStatus_D,Clk,'0','0','1');
SetKeyStatus_D <= ((NOT Reset AND SetKeyStatus)
	OR (Reset AND SetupKeyInstance/AutomatState_FFd4 AND 
	SetupKeyInstance/AutomatState_FFd2 AND NOT SetupKeyInstance/AutomatState_FFd3)
	OR (Reset AND NOT SetupKeyInstance/AutomatState_FFd4 AND 
	NOT SetupKeyInstance/AutomatState_FFd2 AND SetupKeyInstance/AutomatState_FFd3));

FDCPE_SetupKeyInstance/AutomatState_FFd1: FDCPE port map (SetupKeyInstance/AutomatState_FFd1,SetupKeyInstance/AutomatState_FFd1_D,Clk,NOT Reset,'0','1');
SetupKeyInstance/AutomatState_FFd1_D <= ((SetupKeyInstance/AutomatState_FFd4 AND 
	SetupKeyInstance/AutomatState_FFd2 AND NOT SetupKeyInstance/AutomatState_FFd3)
	OR (NOT SetKeyInp AND SetupKeyInstance/AutomatState_FFd1 AND 
	SetupKeyInstance/DelayCnt(0))
	OR (NOT SetKeyInp AND SetupKeyInstance/AutomatState_FFd1 AND 
	SetupKeyInstance/DelayCnt(1))
	OR (NOT SetKeyInp AND SetupKeyInstance/AutomatState_FFd1 AND 
	NOT SetupKeyInstance/DelayCnt(2))
	OR (NOT SetKeyInp AND SetupKeyInstance/AutomatState_FFd1 AND 
	SetupKeyInstance/DelayCnt(3))
	OR (NOT SetKeyInp AND SetupKeyInstance/AutomatState_FFd1 AND 
	SetupKeyInstance/DelayCnt(4)));

FDCPE_SetupKeyInstance/AutomatState_FFd2: FDCPE port map (SetupKeyInstance/AutomatState_FFd2,SetupKeyInstance/AutomatState_FFd2_D,Clk,NOT Reset,'0','1');
SetupKeyInstance/AutomatState_FFd2_D <= NOT (((SetupKeyInstance/AutomatState_FFd4 AND 
	NOT SetupKeyInstance/AutomatState_FFd2 AND NOT SetupKeyInstance/AutomatState_FFd1)
	OR (NOT SetupKeyInstance/AutomatState_FFd2 AND 
	NOT SetupKeyInstance/AutomatState_FFd1 AND NOT SetupKeyInstance/AutomatState_FFd3)
	OR (NOT SetupKeyInstance/AutomatState_FFd4 AND 
	NOT SetupKeyInstance/AutomatState_FFd1 AND NOT SetupKeyInstance/AutomatState_FFd3 AND 
	SetupKeyInstance/DelayCnt(0) AND SetupKeyInstance/DelayCnt(1) AND 
	NOT SetupKeyInstance/DelayCnt(2) AND NOT SetupKeyInstance/DelayCnt(3) AND 
	NOT SetupKeyInstance/DelayCnt(4))));

FTCPE_SetupKeyInstance/AutomatState_FFd3: FTCPE port map (SetupKeyInstance/AutomatState_FFd3,SetupKeyInstance/AutomatState_FFd3_T,Clk,NOT Reset,'0','1');
SetupKeyInstance/AutomatState_FFd3_T <= ((SetupKeyInstance/AutomatState_FFd4 AND 
	NOT SetupKeyInstance/AutomatState_FFd2 AND NOT SetupKeyInstance/AutomatState_FFd3)
	OR (SetKeyInp AND SetupKeyInstance/AutomatState_FFd1 AND 
	NOT SetupKeyInstance/AutomatState_FFd3)
	OR (SetupKeyInstance/AutomatState_FFd4 AND SetKeyInp AND 
	NOT SetupKeyInstance/AutomatState_FFd1 AND SetupKeyInstance/AutomatState_FFd3)
	OR (SetupKeyInstance/AutomatState_FFd4 AND NOT SetKeyInp AND 
	SetupKeyInstance/AutomatState_FFd2 AND SetupKeyInstance/AutomatState_FFd3)
	OR (NOT SetKeyInp AND SetupKeyInstance/AutomatState_FFd2 AND 
	SetupKeyInstance/AutomatState_FFd3 AND NOT SetupKeyInstance/DelayCnt(0) AND 
	NOT SetupKeyInstance/DelayCnt(1) AND SetupKeyInstance/DelayCnt(2) AND 
	SetupKeyInstance/DelayCnt(3) AND SetupKeyInstance/DelayCnt(4)));

FDCPE_SetupKeyInstance/AutomatState_FFd4: FDCPE port map (SetupKeyInstance/AutomatState_FFd4,SetupKeyInstance/AutomatState_FFd4_D,Clk,NOT Reset,'0','1');
SetupKeyInstance/AutomatState_FFd4_D <= (SetupKeyInstance/AutomatState_FFd4 AND NOT SetKeyInp AND 
	NOT SetupKeyInstance/AutomatState_FFd2)
	XOR ((SetKeyInp AND SetupKeyInstance/AutomatState_FFd1)
	OR (SetupKeyInstance/AutomatState_FFd4 AND SetKeyInp AND 
	NOT SetupKeyInstance/AutomatState_FFd2 AND NOT SetupKeyInstance/AutomatState_FFd3)
	OR (NOT SetupKeyInstance/AutomatState_FFd4 AND SetKeyInp AND 
	SetupKeyInstance/AutomatState_FFd2 AND SetupKeyInstance/AutomatState_FFd3)
	OR (NOT SetupKeyInstance/AutomatState_FFd4 AND NOT SetKeyInp AND 
	NOT SetupKeyInstance/AutomatState_FFd2 AND NOT SetupKeyInstance/AutomatState_FFd3)
	OR (NOT SetupKeyInstance/AutomatState_FFd4 AND 
	SetupKeyInstance/AutomatState_FFd1 AND NOT SetupKeyInstance/DelayCnt(0) AND 
	NOT SetupKeyInstance/DelayCnt(1) AND SetupKeyInstance/DelayCnt(2) AND 
	NOT SetupKeyInstance/DelayCnt(3) AND NOT SetupKeyInstance/DelayCnt(4))
	OR (SetupKeyInstance/AutomatState_FFd2 AND 
	SetupKeyInstance/AutomatState_FFd1 AND NOT SetupKeyInstance/DelayCnt(0) AND 
	NOT SetupKeyInstance/DelayCnt(1) AND SetupKeyInstance/DelayCnt(2) AND 
	NOT SetupKeyInstance/DelayCnt(3) AND NOT SetupKeyInstance/DelayCnt(4))
	OR (NOT SetupKeyInstance/AutomatState_FFd4 AND 
	SetupKeyInstance/AutomatState_FFd2 AND SetupKeyInstance/AutomatState_FFd3 AND 
	NOT SetupKeyInstance/DelayCnt(0) AND NOT SetupKeyInstance/DelayCnt(1) AND 
	SetupKeyInstance/DelayCnt(2) AND SetupKeyInstance/DelayCnt(3) AND 
	SetupKeyInstance/DelayCnt(4))
	OR (SetupKeyInstance/AutomatState_FFd4 AND NOT SetKeyInp AND 
	NOT SetupKeyInstance/AutomatState_FFd2 AND SetupKeyInstance/AutomatState_FFd3 AND 
	SetupKeyInstance/DelayCnt(0) AND SetupKeyInstance/DelayCnt(1) AND 
	NOT SetupKeyInstance/DelayCnt(2) AND NOT SetupKeyInstance/DelayCnt(3) AND 
	NOT SetupKeyInstance/DelayCnt(4)));

FTCPE_SetupKeyInstance/DelayCnt0: FTCPE port map (SetupKeyInstance/DelayCnt(0),SetupKeyInstance/DelayCntEnable,FDiv(6),NOT N_PZ_732,'0','1');

FTCPE_SetupKeyInstance/DelayCnt1: FTCPE port map (SetupKeyInstance/DelayCnt(1),SetupKeyInstance/DelayCnt_T(1),FDiv(6),NOT N_PZ_732,'0','1');
SetupKeyInstance/DelayCnt_T(1) <= (SetupKeyInstance/DelayCnt(0) AND 
	SetupKeyInstance/DelayCntEnable);

FTCPE_SetupKeyInstance/DelayCnt2: FTCPE port map (SetupKeyInstance/DelayCnt(2),SetupKeyInstance/DelayCnt_T(2),FDiv(6),NOT N_PZ_732,'0','1');
SetupKeyInstance/DelayCnt_T(2) <= (SetupKeyInstance/DelayCnt(0) AND 
	SetupKeyInstance/DelayCntEnable AND SetupKeyInstance/DelayCnt(1));

FTCPE_SetupKeyInstance/DelayCnt3: FTCPE port map (SetupKeyInstance/DelayCnt(3),SetupKeyInstance/DelayCnt_T(3),FDiv(6),NOT N_PZ_732,'0','1');
SetupKeyInstance/DelayCnt_T(3) <= (SetupKeyInstance/DelayCnt(0) AND 
	SetupKeyInstance/DelayCntEnable AND SetupKeyInstance/DelayCnt(1) AND 
	SetupKeyInstance/DelayCnt(2));

FTCPE_SetupKeyInstance/DelayCnt4: FTCPE port map (SetupKeyInstance/DelayCnt(4),SetupKeyInstance/DelayCnt_T(4),FDiv(6),NOT N_PZ_732,'0','1');
SetupKeyInstance/DelayCnt_T(4) <= (SetupKeyInstance/DelayCnt(0) AND 
	SetupKeyInstance/DelayCntEnable AND SetupKeyInstance/DelayCnt(1) AND 
	SetupKeyInstance/DelayCnt(2) AND SetupKeyInstance/DelayCnt(3));

FDCPE_SetupKeyInstance/DelayCntClear: FDCPE port map (SetupKeyInstance/DelayCntClear,SetupKeyInstance/DelayCntClear_D,Clk,'0','0','1');
SetupKeyInstance/DelayCntClear_D <= NOT (((NOT Reset AND NOT SetupKeyInstance/DelayCntClear)
	OR (Reset AND SetupKeyInstance/AutomatState_FFd4 AND 
	SetupKeyInstance/AutomatState_FFd2 AND NOT SetupKeyInstance/AutomatState_FFd1)
	OR (Reset AND SetupKeyInstance/AutomatState_FFd4 AND 
	NOT SetupKeyInstance/AutomatState_FFd1 AND NOT SetupKeyInstance/AutomatState_FFd3)));

FDCPE_SetupKeyInstance/DelayCntEnable: FDCPE port map (SetupKeyInstance/DelayCntEnable,SetupKeyInstance/DelayCntEnable_D,Clk,'0','0','1');
SetupKeyInstance/DelayCntEnable_D <= NOT (((NOT Reset AND NOT SetupKeyInstance/DelayCntEnable)
	OR (Reset AND SetupKeyInstance/AutomatState_FFd4 AND 
	SetupKeyInstance/AutomatState_FFd2 AND NOT SetupKeyInstance/AutomatState_FFd1)
	OR (Reset AND NOT SetupKeyInstance/AutomatState_FFd2 AND 
	NOT SetupKeyInstance/AutomatState_FFd1 AND NOT SetupKeyInstance/AutomatState_FFd3)));


SpeedLed <= SpeedKeyInp;

FTCPE_UCmpReg0: FTCPE port map (UCmpReg(0),Context_FFd1,SetKeyStatus,NOT Reset,'0','1');

FTCPE_UCmpReg1: FTCPE port map (UCmpReg(1),UCmpReg_T(1),SetKeyStatus,NOT Reset,'0','1');
UCmpReg_T(1) <= ((Context_FFd1 AND DirLed AND UCmpReg(0))
	OR (Context_FFd1 AND NOT DirLed AND NOT UCmpReg(0)));

FTCPE_UCmpReg2: FTCPE port map (UCmpReg(2),UCmpReg_T(2),SetKeyStatus,NOT Reset,'0','1');
UCmpReg_T(2) <= ((Context_FFd1 AND DirLed AND UCmpReg(0) AND UCmpReg(1))
	OR (Context_FFd1 AND NOT DirLed AND NOT UCmpReg(0) AND NOT UCmpReg(1)));

FTCPE_UCmpReg3: FTCPE port map (UCmpReg(3),UCmpReg_T(3),SetKeyStatus,NOT Reset,'0','1');
UCmpReg_T(3) <= ((Context_FFd1 AND DirLed AND UCmpReg(0) AND UCmpReg(1) AND 
	UCmpReg(2))
	OR (Context_FFd1 AND NOT DirLed AND NOT UCmpReg(0) AND NOT UCmpReg(1) AND 
	NOT UCmpReg(2)));

FTCPE_UCmpReg4: FTCPE port map (UCmpReg(4),UCmpReg_T(4),SetKeyStatus,NOT Reset,'0','1');
UCmpReg_T(4) <= ((Context_FFd1 AND DirLed AND UCmpReg(0) AND UCmpReg(1) AND 
	UCmpReg(2) AND UCmpReg(3))
	OR (Context_FFd1 AND NOT DirLed AND NOT UCmpReg(0) AND NOT UCmpReg(1) AND 
	NOT UCmpReg(2) AND NOT UCmpReg(3)));

FTCPE_UCmpReg5: FTCPE port map (UCmpReg(5),UCmpReg_T(5),SetKeyStatus,NOT Reset,'0','1');
UCmpReg_T(5) <= ((Context_FFd1 AND DirLed AND UCmpReg(0) AND UCmpReg(1) AND 
	UCmpReg(2) AND UCmpReg(3) AND UCmpReg(4))
	OR (Context_FFd1 AND NOT DirLed AND NOT UCmpReg(0) AND NOT UCmpReg(1) AND 
	NOT UCmpReg(2) AND NOT UCmpReg(3) AND NOT UCmpReg(4)));

FTCPE_UCmpReg6: FTCPE port map (UCmpReg(6),UCmpReg_T(6),SetKeyStatus,NOT Reset,'0','1');
UCmpReg_T(6) <= ((Context_FFd1 AND DirLed AND UCmpReg(0) AND UCmpReg(1) AND 
	UCmpReg(2) AND UCmpReg(5) AND UCmpReg(3) AND UCmpReg(4))
	OR (Context_FFd1 AND NOT DirLed AND NOT UCmpReg(0) AND NOT UCmpReg(1) AND 
	NOT UCmpReg(2) AND NOT UCmpReg(5) AND NOT UCmpReg(3) AND NOT UCmpReg(4)));

FTCPE_UCmpReg7: FTCPE port map (UCmpReg(7),UCmpReg_T(7),SetKeyStatus,'0',NOT Reset,'1');
UCmpReg_T(7) <= ((Context_FFd1 AND DirLed AND UCmpReg(0) AND UCmpReg(1) AND 
	UCmpReg(2) AND UCmpReg(5) AND UCmpReg(3) AND UCmpReg(4) AND 
	UCmpReg(6))
	OR (Context_FFd1 AND NOT DirLed AND NOT UCmpReg(0) AND NOT UCmpReg(1) AND 
	NOT UCmpReg(2) AND NOT UCmpReg(5) AND NOT UCmpReg(3) AND NOT UCmpReg(4) AND 
	NOT UCmpReg(6)));


Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE); 
 FDDCPE (Q,D,C,CLR,PRE,CE); 
 FTCPE (Q,D,C,CLR,PRE,CE); 
 FTDCPE (Q,D,C,CLR,PRE,CE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC2C256-6-VQ100


   --------------------------------------------------  
  /100 98  96  94  92  90  88  86  84  82  80  78  76  \
 |   99  97  95  93  91  89  87  85  83  81  79  77    |
 | 1                                               75  | 
 | 2                                               74  | 
 | 3                                               73  | 
 | 4                                               72  | 
 | 5                                               71  | 
 | 6                                               70  | 
 | 7                                               69  | 
 | 8                                               68  | 
 | 9                                               67  | 
 | 10                                              66  | 
 | 11                                              65  | 
 | 12                                              64  | 
 | 13                XC2C256-6-VQ100               63  | 
 | 14                                              62  | 
 | 15                                              61  | 
 | 16                                              60  | 
 | 17                                              59  | 
 | 18                                              58  | 
 | 19                                              57  | 
 | 20                                              56  | 
 | 21                                              55  | 
 | 22                                              54  | 
 | 23                                              53  | 
 | 24                                              52  | 
 | 25                                              51  | 
 |   27  29  31  33  35  37  39  41  43  45  47  49    |
  \26  28  30  32  34  36  38  40  42  44  46  48  50  /
   --------------------------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 Seg_K                            51 VCCIO-1.8                     
  2 Seg_G                            52 PGND                          
  3 Seg_F                            53 PGND                          
  4 Seg_E                            54 PGND                          
  5 VCCAUX                           55 SetKeyInp                     
  6 Seg_D                            56 ModeKeyInp                    
  7 Seg_C                            57 VCC                           
  8 Seg_A                            58 DirKeyInp                     
  9 Seg_B                            59 PGND                          
 10 OutSig                           60 PGND                          
 11 PGND                             61 PGND                          
 12 PGND                             62 GND                           
 13 PGND                             63 PGND                          
 14 PGND                             64 PGND                          
 15 PGND                             65 Reset                         
 16 SpeedLed                         66 PGND                          
 17 DirLed                           67 PGND                          
 18 DSel0                            68 PGND                          
 19 DSel1                            69 GND                           
 20 VCCIO-1.8                        70 PGND                          
 21 GND                              71 PGND                          
 22 Clk                              72 PGND                          
 23 PGND                             73 PGND                          
 24 DSel2                            74 PGND                          
 25 GND                              75 GND                           
 26 VCC                              76 PGND                          
 27 DSel3                            77 PGND                          
 28 PGND                             78 PGND                          
 29 PGND                             79 PGND                          
 30 PGND                             80 PGND                          
 31 GND                              81 PGND                          
 32 PGND                             82 PGND                          
 33 PGND                             83 TDO                           
 34 PGND                             84 GND                           
 35 PGND                             85 PGND                          
 36 PGND                             86 PGND                          
 37 PGND                             87 PGND                          
 38 VCCIO-1.8                        88 VCCIO-1.8                     
 39 PGND                             89 PGND                          
 40 PGND                             90 PGND                          
 41 PGND                             91 PGND                          
 42 PGND                             92 PGND                          
 43 PGND                             93 PGND                          
 44 PGND                             94 PGND                          
 45 TDI                              95 PGND                          
 46 PGND                             96 PGND                          
 47 TMS                              97 PGND                          
 48 TCK                              98 VCCIO-1.8                     
 49 SpeedKeyInp                      99 PGND                          
 50 PGND                            100 GND                           


Legend :  NC  = Not Connected, unbonded pin
        PGND  = Unused I/O configured as additional Ground pin
         KPR  = Unused I/O with weak keeper (leave unconnected)
         WPU  = Unused I/O with weak pull up (leave unconnected)
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
      VCCAUX  = Power supply for JTAG pins
   VCCIO-3.3  = I/O supply voltage for LVTTL, LVCMOS33, SSTL3_I
   VCCIO-2.5  = I/O supply voltage for LVCMOS25, SSTL2_I
   VCCIO-1.8  = I/O supply voltage for LVCMOS18
   VCCIO-1.5  = I/O supply voltage for LVCMOS15, HSTL_I
        VREF  = Reference voltage for indicated input standard
       *VREF  = Reference voltage pin selected by software
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc2c256-6-VQ100
Optimization Method                         : DENSITY
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Set Unused I/O Pin Termination              : GROUND
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
Enable Input Registers                      : ON
Function Block Fan-in Limit                 : 38
Use DATA_GATE Attribute                     : ON
Set Tristate Outputs to Termination Mode    : KEEPER
Default Voltage Standard for All Outputs    : LVCMOS18
Input Limit                                 : 32
Pterm Limit                                 : 28