********** Mapped Logic ********** |
DSel0 <= (NOT SelCnt(0) AND NOT SelCnt(1)); |
DSel1 <= (SelCnt(0) AND NOT SelCnt(1)); |
DSel2 <= (NOT SelCnt(0) AND SelCnt(1)); |
DSel3 <= (SelCnt(0) AND SelCnt(1)); |
FTCPE_FDiv0: FTCPE port map (FDiv(0),'0',NOT Clk,NOT Reset,'0','1'); |
FTCPE_FDiv1: FTCPE port map (FDiv(1),FDiv(0),NOT Clk,NOT Reset,'0','1'); |
FTCPE_FDiv2: FTCPE port map (FDiv(2),FDiv_T(2),NOT Clk,NOT Reset,'0','1');
FDiv_T(2) <= (FDiv(0) AND FDiv(1)); |
FTCPE_FDiv3: FTCPE port map (FDiv(3),FDiv_T(3),NOT Clk,NOT Reset,'0','1');
FDiv_T(3) <= (FDiv(0) AND FDiv(1) AND FDiv(2)); |
FTCPE_FDiv4: FTCPE port map (FDiv(4),FDiv_T(4),NOT Clk,NOT Reset,'0','1');
FDiv_T(4) <= (FDiv(0) AND FDiv(1) AND FDiv(2) AND FDiv(3)); |
FTCPE_FDiv5: FTCPE port map (FDiv(5),FDiv_T(5),NOT Clk,NOT Reset,'0','1');
FDiv_T(5) <= (FDiv(0) AND FDiv(1) AND FDiv(2) AND FDiv(3) AND FDiv(4)); |
FTCPE_FDiv6: FTCPE port map (FDiv(6),FDiv_T(6),NOT Clk,NOT Reset,'0','1');
FDiv_T(6) <= (FDiv(0) AND FDiv(1) AND FDiv(2) AND FDiv(3) AND FDiv(4) AND FDiv(5)); |
Seg_A <= '0'; |
Seg_B <= ((KeyIn2 AND DSel2)
OR (KeyIn1 AND DSel1) OR (KeyIn0 AND DSel0) OR (KeyIn3 AND DSel3)); |
Seg_C <= ((KeyIn2 AND DSel2)
OR (KeyIn1 AND DSel1) OR (KeyIn0 AND DSel0) OR (KeyIn3 AND DSel3)); |
Seg_D <= NOT (((KeyIn2 AND DSel2)
OR (KeyIn1 AND DSel1) OR (KeyIn0 AND DSel0) OR (KeyIn3 AND DSel3))); |
Seg_E <= NOT ('0'); |
Seg_F <= NOT ('0'); |
Seg_G <= ((KeyIn2 AND DSel2)
OR (KeyIn1 AND DSel1) OR (KeyIn0 AND DSel0) OR (KeyIn3 AND DSel3)); |
Seg_K <= '0'; |
FTCPE_SelCnt0: FTCPE port map (SelCnt(0),'0',FDiv(6),NOT Reset,'0','1'); |
FTCPE_SelCnt1: FTCPE port map (SelCnt(1),SelCnt(0),FDiv(6),NOT Reset,'0','1'); |
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE); FDDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); FTDCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); |