Signal Name | Total Pterms | Total Inputs | Function Block | Macrocell | Slew Rate | Bank | Pin Number | Pin Type | Pin Use | Reg Use | I/O Std | I/O Style | Reg Init State |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Seg_K | 0 | 0 | FB2 | MC1 | FAST | 2 | 1 | I/O/GTS2 | O | LVCMOS18 | |||
Seg_G | 3 | 4 | FB2 | MC3 | FAST | 2 | 2 | I/O/GTS3 | O | LVCMOS18 | |||
Seg_F | 3 | 4 | FB2 | MC5 | FAST | 2 | 3 | I/O/GTS0 | O | LVCMOS18 | |||
Seg_E | 3 | 4 | FB2 | MC12 | FAST | 2 | 4 | I/O/GTS1 | O | LVCMOS18 | |||
Seg_D | 4 | 4 | FB2 | MC14 | FAST | 2 | 6 | I/O | O | LVCMOS18 | |||
Seg_C | 3 | 4 | FB2 | MC15 | FAST | 2 | 7 | I/O | O | LVCMOS18 | |||
Seg_A | 3 | 4 | FB4 | MC1 | FAST | 2 | 8 | I/O | O | LVCMOS18 | |||
Seg_B | 3 | 4 | FB4 | MC2 | FAST | 2 | 9 | I/O | O | LVCMOS18 | |||
ModeLed | 1 | 1 | FB7 | MC12 | FAST | 1 | 16 | I/O | O | LVCMOS18 | |||
KeyLed | 2 | 4 | FB7 | MC11 | FAST | 1 | 17 | I/O | O | LATCH | LVCMOS18 | RESET | |
DSel0 | 1 | 2 | FB7 | MC6 | FAST | 1 | 18 | I/O | O | LVCMOS18 | |||
DSel1 | 1 | 2 | FB7 | MC5 | FAST | 1 | 19 | I/O | O | LVCMOS18 | |||
DSel2 | 1 | 2 | FB6 | MC2 | FAST | 1 | 24 | I/O/CDR | O | LVCMOS18 | |||
DSel3 | 1 | 2 | FB6 | MC4 | FAST | 1 | 27 | I/O/GCK2 | O | LVCMOS18 | |||
Key0Instance/ShRegister<0> | 2 | 2 | FB13 | MC6 | 1 | 55 | I/O | IR | DFF | KPR | |||
Cnt1<1> | 4 | 6 | FB1 | MC14 | 2 | 94 | I/O | (b) | TFF | RESET | |||
Cnt1<3> | 4 | 6 | FB1 | MC13 | 2 | 95 | I/O | (b) | TFF | RESET | |||
Cnt10<0> | 3 | 6 | FB1 | MC12 | 2 | 96 | I/O | (b) | TFF | RESET | |||
Cnt1<2> | 3 | 4 | FB1 | MC6 | 2 | 97 | I/O | (b) | TFF | RESET | |||
MuxDisplInstance/Tetr<0> | 4 | 8 | FB1 | MC3 | 2 | 99 | I/O/GSR | (b) | |||||
Cnt10<2> | 3 | 8 | FB1 | MC1 | (b) | (b) | RESET | ||||||
Cnt100<0> | 3 | 10 | FB1 | MC2 | (b) | (b) | RESET | ||||||
Cnt10<3> | 4 | 10 | FB1 | MC4 | (b) | (b) | RESET | ||||||
Cnt10<1> | 5 | 10 | FB1 | MC5 | (b) | (b) | RESET | ||||||
Cnt100<2> | 3 | 12 | FB1 | MC7 | (b) | (b) | RESET | ||||||
Cnt1000<0> | 3 | 14 | FB1 | MC8 | (b) | (b) | RESET | ||||||
Cnt100<3> | 4 | 14 | FB1 | MC9 | (b) | (b) | RESET | ||||||
Cnt100<1> | 5 | 14 | FB1 | MC10 | (b) | (b) | RESET | ||||||
Cnt1000<2> | 3 | 16 | FB1 | MC11 | (b) | (b) | RESET | ||||||
Cnt1000<3> | 4 | 18 | FB1 | MC15 | (b) | (b) | RESET | ||||||
Cnt1000<1> | 5 | 18 | FB1 | MC16 | (b) | (b) | RESET | ||||||
MuxDisplInstance/SelCnt<0> | 2 | 2 | FB2 | MC2 | (b) | (b) | RESET | ||||||
FDiv<4> | 3 | 6 | FB2 | MC4 | (b) | (b) | RESET | ||||||
FDiv<3> | 3 | 5 | FB2 | MC6 | (b) | (b) | RESET | ||||||
FDiv<2> | 3 | 4 | FB2 | MC7 | (b) | (b) | RESET | ||||||
FDiv<1> | 3 | 3 | FB2 | MC8 | (b) | (b) | RESET | ||||||
FDiv<0> | 2 | 2 | FB2 | MC9 | (b) | (b) | RESET | ||||||
Cnt1<0> | 2 | 2 | FB2 | MC10 | (b) | (b) | RESET | ||||||
FClk | 2 | 3 | FB2 | MC11 | (b) | (b) | RESET | ||||||
FDivInstance/FDivCnt<1> | 2 | 2 | FB2 | MC13 | (b) | (b) | RESET | ||||||
FDivInstance/FDivCnt<0> | 1 | 1 | FB2 | MC16 | (b) | (b) | RESET | ||||||
MuxDisplInstance/SelCnt<1> | 3 | 3 | FB3 | MC6 | (b) | (b) | RESET | ||||||
Key0Instance/ShRegister<3> | 3 | 3 | FB3 | MC7 | (b) | (b) | RESET | ||||||
Key0Instance/ShRegister<2> | 3 | 3 | FB3 | MC8 | (b) | (b) | RESET | ||||||
Key0Instance/ShRegister<1> | 3 | 3 | FB3 | MC9 | (b) | (b) | RESET | ||||||
N_PZ_198 | 2 | 3 | FB3 | MC10 | (b) | (b) | |||||||
MuxDisplInstance/Tetr<3> | 4 | 8 | FB3 | MC11 | (b) | (b) | |||||||
MuxDisplInstance/Tetr<2> | 4 | 8 | FB3 | MC13 | (b) | (b) | |||||||
MuxDisplInstance/Tetr<1> | 4 | 8 | FB3 | MC15 | (b) | (b) |