cpldfit:  version J.36                              Xilinx Inc.
                                  Fitter Report
Design Name: Clock                               Date:  5-16-2009,  9:42PM
Device Used: XC2C256-6-VQ100
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
91 /256 ( 36%) 216 /896  ( 24%) 160 /640  ( 25%) 58 /256 ( 23%) 16 /80  ( 20%)

** Function Block Resources **

Function Mcells   FB Inps  Pterms   IO       CTC      CTR      CTS      CTE     
Block    Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot
FB1       5/16     32/40    56/56*    0/ 5    0/1      0/1      0/1      0/1
FB2      16/16*    30/40    44/56     6/ 6*   1/1*     1/1*     0/1      0/1
FB3      16/16*    16/40    16/56     0/ 4    0/1      1/1*     0/1      0/1
FB4      16/16*    19/40    25/56     2/ 6    1/1*     1/1*     0/1      0/1
FB5      16/16*    29/40    38/56     0/ 2    1/1*     1/1*     0/1      0/1
FB6      16/16*    21/40    26/56     2/ 5    1/1*     1/1*     1/1*     0/1
FB7       4/16     11/40     9/56     2/ 6    0/1      0/1      0/1      0/1
FB8       0/16      0/40     0/56     0/ 6    0/1      0/1      0/1      0/1
FB9       0/16      0/40     0/56     0/ 5    0/1      0/1      0/1      0/1
FB10      0/16      0/40     0/56     0/ 7    0/1      0/1      0/1      0/1
FB11      0/16      0/40     0/56     0/ 4    0/1      0/1      0/1      0/1
FB12      0/16      0/40     0/56     0/ 4    0/1      0/1      0/1      0/1
FB13      2/16      2/40     2/56     0/ 4    1/1*     0/1      1/1*     0/1
FB14      0/16      0/40     0/56     0/ 5    0/1      0/1      0/1      0/1
FB15      0/16      0/40     0/56     0/ 6    0/1      0/1      0/1      0/1
FB16      0/16      0/40     0/56     0/ 5    0/1      0/1      0/1      0/1
         -----    -------  -------   -----    ---      ---      ---      ---
Total    91/256   160/640  216/896   12/80    5/16     5/16     2/16     0/16

CTC - Control Term Clock
CTR - Control Term Reset
CTS - Control Term Set
CTE - Control Term Output Enable

* - Resource is exhausted

** Global Control Resources **

GCK         GSR         GTS         
Used/Tot    Used/Tot    Used/Tot    
1/3         0/1         0/4

Signal 'Clk' mapped onto global clock net GCK0.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :    3           3    |  I/O              :     9     70
Output        :   12          12    |  GCK/IO           :     2      3
Bidirectional :    0           0    |  GTS/IO           :     4      4
GCK           :    1           1    |  GSR/IO           :     0      1
GTS           :    0           0    |  CDR/IO           :     1      1
GSR           :    0           0    |  DGE/IO           :     0      1
                 ----        ----
        Total     16          16

End of Mapped Resource Summary
*************************  Summary of Mapped Logic  ************************

** 12 Outputs **

Signal                                  Total Total Loc     Pin   Pin       Pin     I/O      I/O       Slew Reg     Reg Init
Name                                    Pts   Inps          No.   Type      Use     STD      Style     Rate Use     State
Seg_K                                   3     5     FB2_1   1     GTS/I/O   O       LVCMOS18           FAST         
Seg_G                                   3     4     FB2_3   2     GTS/I/O   O       LVCMOS18           FAST         
Seg_F                                   3     4     FB2_5   3     GTS/I/O   O       LVCMOS18           FAST         
Seg_E                                   3     4     FB2_12  4     GTS/I/O   O       LVCMOS18           FAST         
Seg_D                                   4     4     FB2_14  6     I/O       O       LVCMOS18           FAST         
Seg_C                                   3     4     FB2_15  7     I/O       O       LVCMOS18           FAST         
Seg_A                                   3     4     FB4_1   8     I/O       O       LVCMOS18           FAST         
Seg_B                                   3     4     FB4_2   9     I/O       O       LVCMOS18           FAST         
DSel2                                   1     2     FB6_2   24    CDR/I/O   O       LVCMOS18           FAST         
DSel3                                   1     2     FB6_4   27    GCK/I/O   O       LVCMOS18           FAST         
DSel1                                   1     2     FB7_5   19    I/O       O       LVCMOS18           FAST         
DSel0                                   1     2     FB7_6   18    I/O       O       LVCMOS18           FAST         

** 79 Buried Nodes **

Signal                                  Total Total Loc     Reg     Reg Init
Name                                    Pts   Inps          Use     State
N_PZ_452                                2     14    FB1_9           
N_PZ_494                                7     13    FB1_10          
MuxDisplInstance/Mmux_Tetr_I1_Result10  17    20    FB1_11          
MuxDisplInstance/Tetr<3>                13    21    FB1_15          
MuxDisplInstance/Tetr<1>                19    24    FB1_16          
N_PZ_524                                2     8     FB2_2           
MuxDisplInstance/Tetr<0>                10    20    FB2_4           
Sec<5>                                  4     10    FB2_6   TFF     RESET
Sec<4>                                  4     10    FB2_7   TFF     RESET
Sec<3>                                  4     10    FB2_8   TFF     RESET
Sec<2>                                  5     9     FB2_9   TFF     RESET
Sec<1>                                  3     5     FB2_10  TFF     RESET
Sec1<0>                                 3     4     FB2_11  TFF     RESET
N_PZ_400                                3     4     FB2_13          
N_PZ_403                                2     4     FB2_16          
F1HzDivInstance/FDivCnt<3>              2     4     FB3_1   TFF     RESET
F1HzDivInstance/FDivCnt<4>              2     5     FB3_2   TFF     RESET
F1HzDivInstance/FDivCnt<5>              2     6     FB3_3   TFF     RESET
F1HzDivInstance/FDivCnt<6>              2     7     FB3_4   TFF     RESET
FDivInstance/FDivCnt<0>                 1     1     FB3_5   TFF     RESET
F1HzDivInstance/FDivCnt<7>              2     8     FB3_6   TFF     RESET
F1HzDivInstance/FDivCnt<8>              2     9     FB3_7   TFF     RESET
F1HzDivInstance/FDivCnt<9>              2     10    FB3_8   TFF     RESET
F1HzDivInstance/FDivCnt<10>             2     11    FB3_9   TFF     RESET
F1HzDivInstance/FDivCnt<11>             2     12    FB3_10  TFF     RESET
F1HzDivInstance/FDivCnt<12>             2     13    FB3_11  TFF     RESET
F1HzDivInstance/FDivCnt<0>              1     1     FB3_12  TFF     RESET
F1HzDivInstance/FDivCnt<13>             2     14    FB3_13  TFF     RESET
F1HzDivInstance/FDivCnt<1>              2     2     FB3_14  TFF     RESET
F1Hz                                    2     15    FB3_15  TFF     RESET
F1HzDivInstance/FDivCnt<2>              2     3     FB3_16  TFF     RESET
MuxDisplInstance/SelCnt<0>              2     2     FB4_3   TFF     RESET
FDiv<1>                                 3     3     FB4_4   TFF     RESET
FDiv<4>                                 3     6     FB4_5   TFF     RESET
FDiv<3>                                 3     5     FB4_6   TFF     RESET
FDiv<0>                                 2     2     FB4_7   TFF     RESET
ClrPresc_or0000                         2     3     FB4_8           
MachineState_FFd2                       3     5     FB4_9   DFF     RESET
MachineState_FFd1                       3     5     FB4_10  DFF     RESET
Context_FFd2                            3     4     FB4_11  DEFF    RESET

Signal                                  Total Total Loc     Reg     Reg Init
Name                                    Pts   Inps          Use     State
DispMode                                3     6     FB4_12  TFF     RESET
FDiv<2>                                 3     4     FB4_13  TFF     RESET
Context_FFd1                            3     4     FB4_14  DEFF    RESET
FClk                                    2     3     FB4_15  TFF     RESET
FDivInstance/FDivCnt<1>                 2     2     FB4_16  TFF     RESET
Hrs<4>                                  4     9     FB5_1   TFF     RESET
MuxDisplInstance/Tetr<2>                7     13    FB5_2           
Min1<0>                                 3     3     FB5_3   TFF     RESET
Hrs<5>                                  3     8     FB5_4   TFF     RESET
Min<1>                                  3     4     FB5_5   TFF     RESET
Hrs<3>                                  5     9     FB5_6   TFF     RESET
Min<2>                                  4     8     FB5_7   TFF     RESET
Min<5>                                  4     9     FB5_8   TFF     RESET
Min<4>                                  4     9     FB5_9   TFF     RESET
Min<3>                                  4     9     FB5_10  TFF     RESET
N_PZ_435                                3     5     FB5_11          
MCnvInstance/B<2>                       2     5     FB5_12          
MCnvInstance/B<1>                       4     4     FB5_13          
N_PZ_453                                2     2     FB5_14          
N_PZ_528                                1     2     FB5_15          
N_PZ_484                                1     2     FB5_16          
SetupKeyInstance/ShRegister<2>          3     3     FB6_1   DFF     RESET
SetupKeyInstance/ShRegister<1>          3     3     FB6_3   DFF     RESET
ModeKeyStatus                           2     4     FB6_5   LATCH   RESET
ModeKeyInstance/ShRegister<3>           3     3     FB6_6   DFF     RESET
ModeKeyInstance/ShRegister<2>           3     3     FB6_7   DFF     RESET
ModeKeyInstance/ShRegister<1>           3     3     FB6_8   DFF     RESET
Hrs<2>                                  3     5     FB6_9   TFF     RESET
Hrs<1>                                  3     4     FB6_10  TFF     RESET
Hrs1<0>                                 3     3     FB6_11  TFF     RESET
N_PZ_455                                2     2     FB6_12          
MuxDisplInstance/SelCnt<1>              3     3     FB6_13  TFF     RESET
SetupKeyStatus                          2     4     FB6_14  LATCH   RESET
N_PZ_390                                1     3     FB6_15          
SetupKeyInstance/ShRegister<3>          3     3     FB6_16  DFF     RESET
N_PZ_382                                3     5     FB7_15          
N_PZ_399                                4     4     FB7_16          
ModeKeyInstance/ShRegister<0>           2     2     FB13_6  DFF     RESET
SetupKeyInstance/ShRegister<0>          2     2     FB13_13 DFF     RESET

** 4 Inputs **

Signal                                  Loc     Pin   Pin       Pin     I/O      I/O
Name                                            No.   Type      Use     STD      Style
Clk                                     FB5_6   22    GCK/I/O   GCK     LVCMOS18 KPR
Reset                                   FB12_15 65    I/O       I       LVCMOS18 KPR
ModeKeyInp                              FB13_6  55    I/O       I       LVCMOS18 KPR
SetupKeyInp                             FB13_13 56    I/O       I       LVCMOS18 KPR

Legend:
Pin No.   - ~     - User Assigned
I/O Style - OD    - OpenDrain
          - PU    - Pullup
          - KPR   - Keeper
          - S     - SchmittTrigger
          - DG    - DataGate
Reg Use   - LATCH - Transparent latch
          - DFF   - D-flip-flop
          - DEFF  - D-flip-flop with clock enable
          - TFF   - T-flip-flop
          - TDFF  - Dual-edge-triggered T-flip-flop
          - DDFF  - Dual-edge-triggered flip-flop
          - DDEFF - Dual-edge-triggered flip-flop with clock enable
          /S (after any above flop/latch type) indicates initial state is Set
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
              VRF - Vref
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               32/8
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   56/0
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB1_1        (b)           
(unused)                      0     FB1_2        (b)           
(unused)                      0     FB1_3   99   GSR/I/O       
(unused)                      0     FB1_4        (b)           
(unused)                      0     FB1_5        (b)           
(unused)                      0     FB1_6   97   I/O           
(unused)                      0     FB1_7        (b)           
(unused)                      0     FB1_8        (b)           
N_PZ_452                      2     FB1_9        (b)     (b)               
N_PZ_494                      7     FB1_10       (b)     (b)               
MuxDisplInstance/Mmux_Tetr_I1_Result10
                              17    FB1_11       (b)     (b)               
(unused)                      0     FB1_12  96   I/O           
(unused)                      0     FB1_13  95   I/O           
(unused)                      0     FB1_14  94   I/O           
MuxDisplInstance/Tetr<3>      13    FB1_15       (b)     (b)               
MuxDisplInstance/Tetr<1>      19    FB1_16       (b)     (b)               

Signals Used by Logic in Function Block
  1: Context_FFd1       12: Min<1>                      23: N_PZ_453 
  2: Context_FFd2       13: Min<2>                      24: N_PZ_455 
  3: DispMode           14: Min<3>                      25: N_PZ_484 
  4: Hrs<1>             15: Min<4>                      26: N_PZ_528 
  5: Hrs<2>             16: Min<5>                      27: Sec1<0> 
  6: Hrs<3>             17: MuxDisplInstance/SelCnt<0>  28: Sec<1> 
  7: Hrs<4>             18: MuxDisplInstance/SelCnt<1>  29: Sec<2> 
  8: Hrs<5>             19: N_PZ_382                    30: Sec<3> 
  9: MCnvInstance/B<1>  20: N_PZ_390                    31: Sec<4> 
 10: MCnvInstance/B<2>  21: N_PZ_399                    32: Sec<5> 
 11: Min1<0>            22: N_PZ_435                   

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
N_PZ_452          XX........XXXXXX..........XXXXXX........ 14      
N_PZ_494          ..XXXXXXXX.X....XXX...X................. 13      
MuxDisplInstance/Mmux_Tetr_I1_Result10 
                  ...XXXXXXX.X....XXXXX.XX...XXXXX........ 20      
MuxDisplInstance/Tetr<3> 
                  ..XXXXXXXX.X....XXXXX.XX...XXXXX........ 21      
MuxDisplInstance/Tetr<1> 
                  ..XXXXXXXX.X....XXXXXXXXXX.XXXXX........ 24      
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB2  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               30/10
Number of function block control terms used/remaining:        2/2
Number of PLA product terms used/remaining:                   44/12
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
Seg_K                         3     FB2_1   1    GTS/I/O O                 
N_PZ_524                      2     FB2_2        (b)     (b)               
Seg_G                         3     FB2_3   2    GTS/I/O O                 
MuxDisplInstance/Tetr<0>      10    FB2_4        (b)     (b)               
Seg_F                         3     FB2_5   3    GTS/I/O O                 
Sec<5>                        4     FB2_6        (b)     (b)    +   +      
Sec<4>                        4     FB2_7        (b)     (b)    +   +      
Sec<3>                        4     FB2_8        (b)     (b)    +   +      
Sec<2>                        5     FB2_9        (b)     (b)    +   +      
Sec<1>                        3     FB2_10       (b)     (b)    +   +      
Sec1<0>                       3     FB2_11       (b)     (b)    +   +      
Seg_E                         3     FB2_12  4    GTS/I/O O                 
N_PZ_400                      3     FB2_13       (b)     (b)               
Seg_D                         4     FB2_14  6    I/O     O                 
Seg_C                         3     FB2_15  7    I/O     O                 
N_PZ_403                      2     FB2_16       (b)     (b)               

Signals Used by Logic in Function Block
  1: ClrPresc_or0000    11: ModeKeyStatus               21: N_PZ_453 
  2: Context_FFd1       12: MuxDisplInstance/SelCnt<0>  22: N_PZ_484 
  3: Context_FFd2       13: MuxDisplInstance/SelCnt<1>  23: N_PZ_494 
  4: DispMode           14: MuxDisplInstance/Tetr<0>    24: N_PZ_528 
  5: F1Hz               15: MuxDisplInstance/Tetr<1>    25: Sec1<0> 
  6: Hrs1<0>            16: MuxDisplInstance/Tetr<2>    26: Sec<1> 
  7: MCnvInstance/B<1>  17: MuxDisplInstance/Tetr<3>    27: Sec<2> 
  8: MCnvInstance/B<2>  18: N_PZ_390                    28: Sec<3> 
  9: Min1<0>            19: N_PZ_399                    29: Sec<4> 
 10: Min<1>             20: N_PZ_403                    30: Sec<5> 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
Seg_K             .XX.X......XX........................... 5       
N_PZ_524          .XX.....................XXXXXX.......... 8       
Seg_G             .............XXXX....................... 4       
MuxDisplInstance/Tetr<0> 
                  ...X.XXXXX.XX....XX.XXXXXXXXXX.......... 20      
Seg_F             .............XXXX....................... 4       
Sec<5>            XXX.X...................XXXXXX.......... 10      
Sec<4>            XXX.X...................XXXXXX.......... 10      
Sec<3>            XXX.X...................XXXXXX.......... 10      
Sec<2>            XXX.X.............X.....XX.X.X.......... 9       
Sec<1>            XXX.X...................X............... 5       
Sec1<0>           XXX.X................................... 4       
Seg_E             .............XXXX....................... 4       
N_PZ_400          .XX.......X........X.................... 4       
Seg_D             .............XXXX....................... 4       
Seg_C             .............XXXX....................... 4       
N_PZ_403          .XX.X.....X............................. 4       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB3  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               16/24
Number of function block control terms used/remaining:        1/3
Number of PLA product terms used/remaining:                   16/40
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
F1HzDivInstance/FDivCnt<3>    2     FB3_1        (b)     (b)        +      
F1HzDivInstance/FDivCnt<4>    2     FB3_2        (b)     (b)        +      
F1HzDivInstance/FDivCnt<5>    2     FB3_3        (b)     (b)        +      
F1HzDivInstance/FDivCnt<6>    2     FB3_4        (b)     (b)        +      
FDivInstance/FDivCnt<0>       1     FB3_5   93   I/O     (b)               
F1HzDivInstance/FDivCnt<7>    2     FB3_6        (b)     (b)        +      
F1HzDivInstance/FDivCnt<8>    2     FB3_7        (b)     (b)        +      
F1HzDivInstance/FDivCnt<9>    2     FB3_8        (b)     (b)        +      
F1HzDivInstance/FDivCnt<10>   2     FB3_9        (b)     (b)        +      
F1HzDivInstance/FDivCnt<11>   2     FB3_10       (b)     (b)        +      
F1HzDivInstance/FDivCnt<12>   2     FB3_11       (b)     (b)        +      
F1HzDivInstance/FDivCnt<0>    1     FB3_12  92   I/O     (b)        +      
F1HzDivInstance/FDivCnt<13>   2     FB3_13       (b)     (b)        +      
F1HzDivInstance/FDivCnt<1>    2     FB3_14  91   I/O     (b)        +      
F1Hz                          2     FB3_15       (b)     (b)        +      
F1HzDivInstance/FDivCnt<2>    2     FB3_16  90   I/O     (b)        +      

Signals Used by Logic in Function Block
  1: ClrPresc_or0000               7: F1HzDivInstance/FDivCnt<1>  12: F1HzDivInstance/FDivCnt<6> 
  2: F1HzDivInstance/FDivCnt<0>    8: F1HzDivInstance/FDivCnt<2>  13: F1HzDivInstance/FDivCnt<7> 
  3: F1HzDivInstance/FDivCnt<10>   9: F1HzDivInstance/FDivCnt<3>  14: F1HzDivInstance/FDivCnt<8> 
  4: F1HzDivInstance/FDivCnt<11>  10: F1HzDivInstance/FDivCnt<4>  15: F1HzDivInstance/FDivCnt<9> 
  5: F1HzDivInstance/FDivCnt<12>  11: F1HzDivInstance/FDivCnt<5>  16: Reset 
  6: F1HzDivInstance/FDivCnt<13> 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
F1HzDivInstance/FDivCnt<3> 
                  XX....XX................................ 4       
F1HzDivInstance/FDivCnt<4> 
                  XX....XXX............................... 5       
F1HzDivInstance/FDivCnt<5> 
                  XX....XXXX.............................. 6       
F1HzDivInstance/FDivCnt<6> 
                  XX....XXXXX............................. 7       
FDivInstance/FDivCnt<0> 
                  ...............X........................ 1       
F1HzDivInstance/FDivCnt<7> 
                  XX....XXXXXX............................ 8       
F1HzDivInstance/FDivCnt<8> 
                  XX....XXXXXXX........................... 9       
F1HzDivInstance/FDivCnt<9> 
                  XX....XXXXXXXX.......................... 10      
F1HzDivInstance/FDivCnt<10> 
                  XX....XXXXXXXXX......................... 11      
F1HzDivInstance/FDivCnt<11> 
                  XXX...XXXXXXXXX......................... 12      
F1HzDivInstance/FDivCnt<12> 
                  XXXX..XXXXXXXXX......................... 13      
F1HzDivInstance/FDivCnt<0> 
                  X....................................... 1       
F1HzDivInstance/FDivCnt<13> 
                  XXXXX.XXXXXXXXX......................... 14      
F1HzDivInstance/FDivCnt<1> 
                  XX...................................... 2       
F1Hz              XXXXXXXXXXXXXXX......................... 15      
F1HzDivInstance/FDivCnt<2> 
                  XX....X................................. 3       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB4  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               19/21
Number of function block control terms used/remaining:        2/2
Number of PLA product terms used/remaining:                   25/31
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
Seg_A                         3     FB4_1   8    I/O     O                 
Seg_B                         3     FB4_2   9    I/O     O                 
MuxDisplInstance/SelCnt<0>    2     FB4_3   10   I/O     (b)        +      
FDiv<1>                       3     FB4_4        (b)     (b)    +   +      
FDiv<4>                       3     FB4_5   11   I/O     (b)    +   +      
FDiv<3>                       3     FB4_6   12   I/O     (b)    +   +      
FDiv<0>                       2     FB4_7        (b)     (b)    +   +      
ClrPresc_or0000               2     FB4_8        (b)     (b)               
MachineState_FFd2             3     FB4_9        (b)     (b)        +      
MachineState_FFd1             3     FB4_10       (b)     (b)        +      
Context_FFd2                  3     FB4_11       (b)     (b)        +      
DispMode                      3     FB4_12       (b)     (b)        +      
FDiv<2>                       3     FB4_13  13   I/O     (b)    +   +      
Context_FFd1                  3     FB4_14       (b)     (b)        +      
FClk                          2     FB4_15       (b)     (b)        +      
FDivInstance/FDivCnt<1>       2     FB4_16       (b)     (b)        +      

Signals Used by Logic in Function Block
  1: Context_FFd1       8: FDiv<3>                  14: MuxDisplInstance/Tetr<0> 
  2: Context_FFd2       9: FDivInstance/FDivCnt<0>  15: MuxDisplInstance/Tetr<1> 
  3: DispMode          10: FDivInstance/FDivCnt<1>  16: MuxDisplInstance/Tetr<2> 
  4: FClk              11: MachineState_FFd1        17: MuxDisplInstance/Tetr<3> 
  5: FDiv<0>           12: MachineState_FFd2        18: Reset 
  6: FDiv<1>           13: ModeKeyStatus            19: SetupKeyStatus 
  7: FDiv<2>          

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
Seg_A             .............XXXX....................... 4       
Seg_B             .............XXXX....................... 4       
MuxDisplInstance/SelCnt<0> 
                  .......X.........X...................... 2       
FDiv<1>           ...XX............X...................... 3       
FDiv<4>           ...XXXXX.........X...................... 6       
FDiv<3>           ...XXXX..........X...................... 5       
FDiv<0>           ...X.............X...................... 2       
ClrPresc_or0000   XX...............X...................... 3       
MachineState_FFd2 
                  ..........XXX....XX..................... 5       
MachineState_FFd1 
                  ..........XXX....XX..................... 5       
Context_FFd2      X.........XX.....X...................... 4       
DispMode          XXX.......XX.....X...................... 6       
FDiv<2>           ...XXX...........X...................... 4       
Context_FFd1      .X........XX.....X...................... 4       
FClk              ........XX.......X...................... 3       
FDivInstance/FDivCnt<1> 
                  ........X........X...................... 2       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB5  ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               29/11
Number of function block control terms used/remaining:        2/2
Number of PLA product terms used/remaining:                   38/18
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
Hrs<4>                        4     FB5_1        (b)     (b)        +      
MuxDisplInstance/Tetr<2>      7     FB5_2        (b)     (b)               
Min1<0>                       3     FB5_3        (b)     (b)    +   +      
Hrs<5>                        3     FB5_4   23   GCK/I/O (b)        +      
Min<1>                        3     FB5_5        (b)     (b)    +   +      
Hrs<3>                        5     FB5_6   22   GCK/I/O GCK        +      
Min<2>                        4     FB5_7        (b)     (b)    +   +      
Min<5>                        4     FB5_8        (b)     (b)    +   +      
Min<4>                        4     FB5_9        (b)     (b)    +   +      
Min<3>                        4     FB5_10       (b)     (b)    +   +      
N_PZ_435                      3     FB5_11       (b)     (b)               
MCnvInstance/B<2>             2     FB5_12       (b)     (b)               
MCnvInstance/B<1>             4     FB5_13       (b)     (b)               
N_PZ_453                      2     FB5_14       (b)     (b)               
N_PZ_528                      1     FB5_15       (b)     (b)               
N_PZ_484                      1     FB5_16       (b)     (b)               

Signals Used by Logic in Function Block
  1: DispMode           11: Min<1>                                  21: N_PZ_435 
  2: Hrs1<0>            12: Min<2>                                  22: N_PZ_452 
  3: Hrs<1>             13: Min<3>                                  23: N_PZ_484 
  4: Hrs<2>             14: Min<4>                                  24: N_PZ_524 
  5: Hrs<3>             15: Min<5>                                  25: N_PZ_528 
  6: Hrs<4>             16: MuxDisplInstance/Mmux_Tetr_I1_Result10  26: Reset 
  7: Hrs<5>             17: MuxDisplInstance/SelCnt<0>              27: Sec<3> 
  8: MCnvInstance/B<1>  18: MuxDisplInstance/SelCnt<1>              28: Sec<4> 
  9: MCnvInstance/B<2>  19: N_PZ_400                                29: Sec<5> 
 10: Min1<0>            20: N_PZ_403                               

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
Hrs<4>            .XXXXXX...........X..X...X.............. 9       
MuxDisplInstance/Tetr<2> 
                  ....XXX.....XXXXX.....X.X.XXX........... 13      
Min1<0>           ...................X...X.X.............. 3       
Hrs<5>            .XXXXX............X..X...X.............. 8       
Min<1>            .........X.........X...X.X.............. 4       
Hrs<3>            .XXXXXX...........X..X...X.............. 9       
Min<2>            ........XXX..XX....X...X.X.............. 8       
Min<5>            .........XXXXXX....X...X.X.............. 9       
Min<4>            .........XXXXXX....X...X.X.............. 9       
Min<3>            .........XXXXXX....X...X.X.............. 9       
N_PZ_435          .......X...XXXX......................... 5       
MCnvInstance/B<2> 
                  .......X....XXX.....X................... 5       
MCnvInstance/B<1> 
                  ...........XXXX......................... 4       
N_PZ_453          ...........X........X................... 2       
N_PZ_528          X................X...................... 2       
N_PZ_484          X................X...................... 2       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB6  ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               21/19
Number of function block control terms used/remaining:        3/1
Number of PLA product terms used/remaining:                   26/30
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
SetupKeyInstance/ShRegister<2>
                              3     FB6_1        (b)     (b)    +       +  
DSel2                         1     FB6_2   24   CDR/I/O O                 
SetupKeyInstance/ShRegister<1>
                              3     FB6_3        (b)     (b)    +       +  
DSel3                         1     FB6_4   27   GCK/I/O O                 
ModeKeyStatus                 2     FB6_5        (b)     (b)               
ModeKeyInstance/ShRegister<3> 3     FB6_6        (b)     (b)    +       +  
ModeKeyInstance/ShRegister<2> 3     FB6_7        (b)     (b)    +       +  
ModeKeyInstance/ShRegister<1> 3     FB6_8        (b)     (b)    +       +  
Hrs<2>                        3     FB6_9        (b)     (b)        +      
Hrs<1>                        3     FB6_10       (b)     (b)        +      
Hrs1<0>                       3     FB6_11       (b)     (b)        +      
N_PZ_455                      2     FB6_12  28   DGE/I/O (b)               
MuxDisplInstance/SelCnt<1>    3     FB6_13       (b)     (b)        +      
SetupKeyStatus                2     FB6_14  29   I/O     (b)               
N_PZ_390                      1     FB6_15       (b)     (b)               
SetupKeyInstance/ShRegister<3>
                              3     FB6_16  30   I/O     (b)    +       +  

Signals Used by Logic in Function Block
  1: FDiv<3>                         8: ModeKeyInstance/ShRegister<1>  15: N_PZ_484 
  2: FDiv<4>                         9: ModeKeyInstance/ShRegister<2>  16: N_PZ_528 
  3: Hrs1<0>                        10: ModeKeyInstance/ShRegister<3>  17: Reset 
  4: Hrs<1>                         11: MuxDisplInstance/SelCnt<0>     18: SetupKeyInstance/ShRegister<0> 
  5: Hrs<3>                         12: MuxDisplInstance/SelCnt<1>     19: SetupKeyInstance/ShRegister<1> 
  6: Hrs<5>                         13: N_PZ_400                       20: SetupKeyInstance/ShRegister<2> 
  7: ModeKeyInstance/ShRegister<0>  14: N_PZ_452                       21: SetupKeyInstance/ShRegister<3> 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
SetupKeyInstance/ShRegister<2> 
                  .X..............X.X..................... 3       
DSel2             ..........XX............................ 2       
SetupKeyInstance/ShRegister<1> 
                  .X..............XX...................... 3       
DSel3             ..........XX............................ 2       
ModeKeyStatus     ......XXXX.............................. 4       
ModeKeyInstance/ShRegister<3> 
                  .X......X.......X....................... 3       
ModeKeyInstance/ShRegister<2> 
                  .X.....X........X....................... 3       
ModeKeyInstance/ShRegister<1> 
                  .X....X.........X....................... 3       
Hrs<2>            ..XX........XX..X....................... 5       
Hrs<1>            ..X.........XX..X....................... 4       
Hrs1<0>           ............XX..X....................... 3       
N_PZ_455          ....XX.................................. 2       
MuxDisplInstance/SelCnt<1> 
                  X.........X.....X....................... 3       
SetupKeyStatus    .................XXXX................... 4       
N_PZ_390          ..........X...XX........................ 3       
SetupKeyInstance/ShRegister<3> 
                  .X..............X..X.................... 3       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB7  ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               11/29
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   9/47
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB7_1        (b)           
(unused)                      0     FB7_2        (b)           
(unused)                      0     FB7_3        (b)           
(unused)                      0     FB7_4        (b)           
DSel1                         1     FB7_5   19   I/O     O                 
DSel0                         1     FB7_6   18   I/O     O                 
(unused)                      0     FB7_7        (b)           
(unused)                      0     FB7_8        (b)           
(unused)                      0     FB7_9        (b)           
(unused)                      0     FB7_10       (b)           
(unused)                      0     FB7_11  17   I/O           
(unused)                      0     FB7_12  16   I/O           
(unused)                      0     FB7_13  15   I/O           
(unused)                      0     FB7_14  14   I/O           
N_PZ_382                      3     FB7_15       (b)     (b)               
N_PZ_399                      4     FB7_16       (b)     (b)               

Signals Used by Logic in Function Block
  1: Hrs<2>             5: MuxDisplInstance/SelCnt<0>   9: Sec<3> 
  2: Hrs<3>             6: MuxDisplInstance/SelCnt<1>  10: Sec<4> 
  3: Hrs<4>             7: N_PZ_455                    11: Sec<5> 
  4: Hrs<5>             8: Sec<2>                     

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
DSel1             ....XX.................................. 2       
DSel0             ....XX.................................. 2       
N_PZ_382          XXXX..X................................. 5       
N_PZ_399          .......XXXX............................. 4       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB8  ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB8_1        (b)           
(unused)                      0     FB8_2        (b)           
(unused)                      0     FB8_3        (b)           
(unused)                      0     FB8_4        (b)           
(unused)                      0     FB8_5        (b)           
(unused)                      0     FB8_6   32   I/O           
(unused)                      0     FB8_7        (b)           
(unused)                      0     FB8_8        (b)           
(unused)                      0     FB8_9        (b)           
(unused)                      0     FB8_10       (b)           
(unused)                      0     FB8_11  33   I/O           
(unused)                      0     FB8_12  34   I/O           
(unused)                      0     FB8_13  35   I/O           
(unused)                      0     FB8_14  36   I/O           
(unused)                      0     FB8_15  37   I/O           
(unused)                      0     FB8_16       (b)           
*********************************** FB9  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB9_1   78   I/O           
(unused)                      0     FB9_2   79   I/O           
(unused)                      0     FB9_3        (b)           
(unused)                      0     FB9_4   80   I/O           
(unused)                      0     FB9_5        (b)           
(unused)                      0     FB9_6   81   I/O           
(unused)                      0     FB9_7        (b)           
(unused)                      0     FB9_8        (b)           
(unused)                      0     FB9_9        (b)           
(unused)                      0     FB9_10       (b)           
(unused)                      0     FB9_11       (b)           
(unused)                      0     FB9_12  82   I/O           
(unused)                      0     FB9_13       (b)           
(unused)                      0     FB9_14       (b)           
(unused)                      0     FB9_15       (b)           
(unused)                      0     FB9_16       (b)           
*********************************** FB10 ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB10_1  77   I/O           
(unused)                      0     FB10_2  76   I/O           
(unused)                      0     FB10_3  74   I/O           
(unused)                      0     FB10_4  73   I/O           
(unused)                      0     FB10_5  72   I/O           
(unused)                      0     FB10_6  71   I/O           
(unused)                      0     FB10_7       (b)           
(unused)                      0     FB10_8       (b)           
(unused)                      0     FB10_9       (b)           
(unused)                      0     FB10_10      (b)           
(unused)                      0     FB10_11      (b)           
(unused)                      0     FB10_12 70   I/O           
(unused)                      0     FB10_13      (b)           
(unused)                      0     FB10_14      (b)           
(unused)                      0     FB10_15      (b)           
(unused)                      0     FB10_16      (b)           
*********************************** FB11 ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB11_1       (b)           
(unused)                      0     FB11_2       (b)           
(unused)                      0     FB11_3       (b)           
(unused)                      0     FB11_4       (b)           
(unused)                      0     FB11_5       (b)           
(unused)                      0     FB11_6       (b)           
(unused)                      0     FB11_7       (b)           
(unused)                      0     FB11_8       (b)           
(unused)                      0     FB11_9       (b)           
(unused)                      0     FB11_10      (b)           
(unused)                      0     FB11_11 85   I/O           
(unused)                      0     FB11_12 86   I/O           
(unused)                      0     FB11_13 87   I/O           
(unused)                      0     FB11_14 89   I/O           
(unused)                      0     FB11_15      (b)           
(unused)                      0     FB11_16      (b)           
*********************************** FB12 ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB12_1       (b)           
(unused)                      0     FB12_2       (b)           
(unused)                      0     FB12_3       (b)           
(unused)                      0     FB12_4       (b)           
(unused)                      0     FB12_5       (b)           
(unused)                      0     FB12_6       (b)           
(unused)                      0     FB12_7       (b)           
(unused)                      0     FB12_8       (b)           
(unused)                      0     FB12_9       (b)           
(unused)                      0     FB12_10      (b)           
(unused)                      0     FB12_11 68   I/O           
(unused)                      0     FB12_12      (b)           
(unused)                      0     FB12_13 67   I/O           
(unused)                      0     FB12_14 66   I/O           
(unused)                      0     FB12_15 65   I/O     I     
(unused)                      0     FB12_16      (b)           
*********************************** FB13 ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               2/38
Number of function block control terms used/remaining:        2/2
Number of PLA product terms used/remaining:                   2/54
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB13_1       (b)           
(unused)                      0     FB13_2  53   I/O           
(unused)                      0     FB13_3       (b)           
(unused)                      0     FB13_4  54   I/O           
(unused)                      0     FB13_5       (b)           
ModeKeyInstance/ShRegister<0> 2     FB13_6  55   I/O     I      +       +  
(unused)                      0     FB13_7       (b)           
(unused)                      0     FB13_8       (b)           
(unused)                      0     FB13_9       (b)           
(unused)                      0     FB13_10      (b)           
(unused)                      0     FB13_11      (b)           
(unused)                      0     FB13_12      (b)           
SetupKeyInstance/ShRegister<0>
                              2     FB13_13 56   I/O     I      +       +  
(unused)                      0     FB13_14      (b)           
(unused)                      0     FB13_15      (b)           
(unused)                      0     FB13_16      (b)           

Signals Used by Logic in Function Block
  1: FDiv<4>            2: Reset            

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB14 ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB14_1  52   I/O           
(unused)                      0     FB14_2       (b)           
(unused)                      0     FB14_3  50   I/O           
(unused)                      0     FB14_4       (b)           
(unused)                      0     FB14_5  49   I/O           
(unused)                      0     FB14_6       (b)           
(unused)                      0     FB14_7       (b)           
(unused)                      0     FB14_8       (b)           
(unused)                      0     FB14_9       (b)           
(unused)                      0     FB14_10      (b)           
(unused)                      0     FB14_11      (b)           
(unused)                      0     FB14_12      (b)           
(unused)                      0     FB14_13      (b)           
(unused)                      0     FB14_14 46   I/O           
(unused)                      0     FB14_15 44   I/O           
(unused)                      0     FB14_16      (b)           
*********************************** FB15 ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB15_1       (b)           
(unused)                      0     FB15_2       (b)           
(unused)                      0     FB15_3       (b)           
(unused)                      0     FB15_4       (b)           
(unused)                      0     FB15_5       (b)           
(unused)                      0     FB15_6       (b)           
(unused)                      0     FB15_7       (b)           
(unused)                      0     FB15_8       (b)           
(unused)                      0     FB15_9       (b)           
(unused)                      0     FB15_10      (b)           
(unused)                      0     FB15_11 58   I/O           
(unused)                      0     FB15_12 59   I/O           
(unused)                      0     FB15_13 60   I/O           
(unused)                      0     FB15_14 61   I/O           
(unused)                      0     FB15_15 63   I/O           
(unused)                      0     FB15_16 64   I/O           
*********************************** FB16 ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB16_1       (b)           
(unused)                      0     FB16_2       (b)           
(unused)                      0     FB16_3       (b)           
(unused)                      0     FB16_4       (b)           
(unused)                      0     FB16_5  43   I/O           
(unused)                      0     FB16_6  42   I/O           
(unused)                      0     FB16_7       (b)           
(unused)                      0     FB16_8       (b)           
(unused)                      0     FB16_9       (b)           
(unused)                      0     FB16_10      (b)           
(unused)                      0     FB16_11 41   I/O           
(unused)                      0     FB16_12 40   I/O           
(unused)                      0     FB16_13 39   I/O           
(unused)                      0     FB16_14      (b)           
(unused)                      0     FB16_15      (b)           
(unused)                      0     FB16_16      (b)           
*******************************  Equations  ********************************

********** Mapped Logic **********


ClrPresc_or0000 <= ((Reset AND Context_FFd2)
	OR (Reset AND NOT Context_FFd1));

FDCPE_Context_FFd1: FDCPE port map (Context_FFd1,Context_FFd2,NOT Clk,NOT Reset,'0',Context_FFd1_CE);
Context_FFd1_CE <= (MachineState_FFd2 AND MachineState_FFd1);

FDCPE_Context_FFd2: FDCPE port map (Context_FFd2,NOT Context_FFd1,NOT Clk,NOT Reset,'0',Context_FFd2_CE);
Context_FFd2_CE <= (MachineState_FFd2 AND MachineState_FFd1);


DSel0 <= (NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1));


DSel1 <= (MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1));


DSel2 <= (NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1));


DSel3 <= (MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1));

FTCPE_DispMode: FTCPE port map (DispMode,DispMode_T,NOT Clk,NOT Reset,'0','1');
DispMode_T <= ((NOT Context_FFd2 AND NOT Context_FFd1 AND MachineState_FFd2 AND 
	NOT MachineState_FFd1)
	OR (NOT Context_FFd2 AND NOT Context_FFd1 AND MachineState_FFd2 AND 
	NOT DispMode));

FTCPE_F1HzDivInstance/FDivCnt0: FTCPE port map (F1HzDivInstance/FDivCnt(0),'0',NOT Clk,NOT ClrPresc_or0000,'0','1');

FTCPE_F1HzDivInstance/FDivCnt1: FTCPE port map (F1HzDivInstance/FDivCnt(1),F1HzDivInstance/FDivCnt(0),NOT Clk,NOT ClrPresc_or0000,'0','1');

FTCPE_F1HzDivInstance/FDivCnt2: FTCPE port map (F1HzDivInstance/FDivCnt(2),F1HzDivInstance/FDivCnt_T(2),NOT Clk,NOT ClrPresc_or0000,'0','1');
F1HzDivInstance/FDivCnt_T(2) <= (F1HzDivInstance/FDivCnt(0) AND 
	F1HzDivInstance/FDivCnt(1));

FTCPE_F1HzDivInstance/FDivCnt3: FTCPE port map (F1HzDivInstance/FDivCnt(3),F1HzDivInstance/FDivCnt_T(3),NOT Clk,NOT ClrPresc_or0000,'0','1');
F1HzDivInstance/FDivCnt_T(3) <= (F1HzDivInstance/FDivCnt(0) AND 
	F1HzDivInstance/FDivCnt(1) AND F1HzDivInstance/FDivCnt(2));

FTCPE_F1HzDivInstance/FDivCnt4: FTCPE port map (F1HzDivInstance/FDivCnt(4),F1HzDivInstance/FDivCnt_T(4),NOT Clk,NOT ClrPresc_or0000,'0','1');
F1HzDivInstance/FDivCnt_T(4) <= (F1HzDivInstance/FDivCnt(0) AND 
	F1HzDivInstance/FDivCnt(1) AND F1HzDivInstance/FDivCnt(2) AND 
	F1HzDivInstance/FDivCnt(3));

FTCPE_F1HzDivInstance/FDivCnt5: FTCPE port map (F1HzDivInstance/FDivCnt(5),F1HzDivInstance/FDivCnt_T(5),NOT Clk,NOT ClrPresc_or0000,'0','1');
F1HzDivInstance/FDivCnt_T(5) <= (F1HzDivInstance/FDivCnt(0) AND 
	F1HzDivInstance/FDivCnt(1) AND F1HzDivInstance/FDivCnt(2) AND 
	F1HzDivInstance/FDivCnt(3) AND F1HzDivInstance/FDivCnt(4));

FTCPE_F1HzDivInstance/FDivCnt6: FTCPE port map (F1HzDivInstance/FDivCnt(6),F1HzDivInstance/FDivCnt_T(6),NOT Clk,NOT ClrPresc_or0000,'0','1');
F1HzDivInstance/FDivCnt_T(6) <= (F1HzDivInstance/FDivCnt(0) AND 
	F1HzDivInstance/FDivCnt(1) AND F1HzDivInstance/FDivCnt(2) AND 
	F1HzDivInstance/FDivCnt(3) AND F1HzDivInstance/FDivCnt(4) AND 
	F1HzDivInstance/FDivCnt(5));

FTCPE_F1HzDivInstance/FDivCnt7: FTCPE port map (F1HzDivInstance/FDivCnt(7),F1HzDivInstance/FDivCnt_T(7),NOT Clk,NOT ClrPresc_or0000,'0','1');
F1HzDivInstance/FDivCnt_T(7) <= (F1HzDivInstance/FDivCnt(0) AND 
	F1HzDivInstance/FDivCnt(1) AND F1HzDivInstance/FDivCnt(2) AND 
	F1HzDivInstance/FDivCnt(3) AND F1HzDivInstance/FDivCnt(4) AND 
	F1HzDivInstance/FDivCnt(5) AND F1HzDivInstance/FDivCnt(6));

FTCPE_F1HzDivInstance/FDivCnt8: FTCPE port map (F1HzDivInstance/FDivCnt(8),F1HzDivInstance/FDivCnt_T(8),NOT Clk,NOT ClrPresc_or0000,'0','1');
F1HzDivInstance/FDivCnt_T(8) <= (F1HzDivInstance/FDivCnt(0) AND 
	F1HzDivInstance/FDivCnt(1) AND F1HzDivInstance/FDivCnt(2) AND 
	F1HzDivInstance/FDivCnt(3) AND F1HzDivInstance/FDivCnt(4) AND 
	F1HzDivInstance/FDivCnt(5) AND F1HzDivInstance/FDivCnt(6) AND 
	F1HzDivInstance/FDivCnt(7));

FTCPE_F1HzDivInstance/FDivCnt9: FTCPE port map (F1HzDivInstance/FDivCnt(9),F1HzDivInstance/FDivCnt_T(9),NOT Clk,NOT ClrPresc_or0000,'0','1');
F1HzDivInstance/FDivCnt_T(9) <= (F1HzDivInstance/FDivCnt(0) AND 
	F1HzDivInstance/FDivCnt(1) AND F1HzDivInstance/FDivCnt(2) AND 
	F1HzDivInstance/FDivCnt(3) AND F1HzDivInstance/FDivCnt(4) AND 
	F1HzDivInstance/FDivCnt(5) AND F1HzDivInstance/FDivCnt(6) AND 
	F1HzDivInstance/FDivCnt(7) AND F1HzDivInstance/FDivCnt(8));

FTCPE_F1HzDivInstance/FDivCnt10: FTCPE port map (F1HzDivInstance/FDivCnt(10),F1HzDivInstance/FDivCnt_T(10),NOT Clk,NOT ClrPresc_or0000,'0','1');
F1HzDivInstance/FDivCnt_T(10) <= (F1HzDivInstance/FDivCnt(0) AND 
	F1HzDivInstance/FDivCnt(1) AND F1HzDivInstance/FDivCnt(2) AND 
	F1HzDivInstance/FDivCnt(3) AND F1HzDivInstance/FDivCnt(4) AND 
	F1HzDivInstance/FDivCnt(5) AND F1HzDivInstance/FDivCnt(6) AND 
	F1HzDivInstance/FDivCnt(7) AND F1HzDivInstance/FDivCnt(8) AND 
	F1HzDivInstance/FDivCnt(9));

FTCPE_F1HzDivInstance/FDivCnt11: FTCPE port map (F1HzDivInstance/FDivCnt(11),F1HzDivInstance/FDivCnt_T(11),NOT Clk,NOT ClrPresc_or0000,'0','1');
F1HzDivInstance/FDivCnt_T(11) <= (F1HzDivInstance/FDivCnt(0) AND 
	F1HzDivInstance/FDivCnt(10) AND F1HzDivInstance/FDivCnt(1) AND 
	F1HzDivInstance/FDivCnt(2) AND F1HzDivInstance/FDivCnt(3) AND 
	F1HzDivInstance/FDivCnt(4) AND F1HzDivInstance/FDivCnt(5) AND 
	F1HzDivInstance/FDivCnt(6) AND F1HzDivInstance/FDivCnt(7) AND 
	F1HzDivInstance/FDivCnt(8) AND F1HzDivInstance/FDivCnt(9));

FTCPE_F1HzDivInstance/FDivCnt12: FTCPE port map (F1HzDivInstance/FDivCnt(12),F1HzDivInstance/FDivCnt_T(12),NOT Clk,NOT ClrPresc_or0000,'0','1');
F1HzDivInstance/FDivCnt_T(12) <= (F1HzDivInstance/FDivCnt(0) AND 
	F1HzDivInstance/FDivCnt(10) AND F1HzDivInstance/FDivCnt(1) AND 
	F1HzDivInstance/FDivCnt(2) AND F1HzDivInstance/FDivCnt(3) AND 
	F1HzDivInstance/FDivCnt(4) AND F1HzDivInstance/FDivCnt(5) AND 
	F1HzDivInstance/FDivCnt(6) AND F1HzDivInstance/FDivCnt(7) AND 
	F1HzDivInstance/FDivCnt(8) AND F1HzDivInstance/FDivCnt(9) AND 
	F1HzDivInstance/FDivCnt(11));

FTCPE_F1HzDivInstance/FDivCnt13: FTCPE port map (F1HzDivInstance/FDivCnt(13),F1HzDivInstance/FDivCnt_T(13),NOT Clk,NOT ClrPresc_or0000,'0','1');
F1HzDivInstance/FDivCnt_T(13) <= (F1HzDivInstance/FDivCnt(0) AND 
	F1HzDivInstance/FDivCnt(10) AND F1HzDivInstance/FDivCnt(1) AND 
	F1HzDivInstance/FDivCnt(2) AND F1HzDivInstance/FDivCnt(3) AND 
	F1HzDivInstance/FDivCnt(4) AND F1HzDivInstance/FDivCnt(5) AND 
	F1HzDivInstance/FDivCnt(6) AND F1HzDivInstance/FDivCnt(7) AND 
	F1HzDivInstance/FDivCnt(8) AND F1HzDivInstance/FDivCnt(9) AND 
	F1HzDivInstance/FDivCnt(11) AND F1HzDivInstance/FDivCnt(12));

FTCPE_F1Hz: FTCPE port map (F1Hz,F1Hz_T,NOT Clk,NOT ClrPresc_or0000,'0','1');
F1Hz_T <= (F1HzDivInstance/FDivCnt(0) AND 
	F1HzDivInstance/FDivCnt(10) AND F1HzDivInstance/FDivCnt(1) AND 
	F1HzDivInstance/FDivCnt(2) AND F1HzDivInstance/FDivCnt(3) AND 
	F1HzDivInstance/FDivCnt(4) AND F1HzDivInstance/FDivCnt(5) AND 
	F1HzDivInstance/FDivCnt(6) AND F1HzDivInstance/FDivCnt(7) AND 
	F1HzDivInstance/FDivCnt(8) AND F1HzDivInstance/FDivCnt(9) AND 
	F1HzDivInstance/FDivCnt(11) AND F1HzDivInstance/FDivCnt(12) AND 
	F1HzDivInstance/FDivCnt(13));

FTCPE_FClk: FTCPE port map (FClk,FClk_T,NOT Clk,NOT Reset,'0','1');
FClk_T <= (FDivInstance/FDivCnt(0) AND FDivInstance/FDivCnt(1));

FTCPE_FDiv0: FTCPE port map (FDiv(0),'0',FClk,NOT Reset,'0','1');

FTCPE_FDiv1: FTCPE port map (FDiv(1),FDiv(0),FClk,NOT Reset,'0','1');

FTCPE_FDiv2: FTCPE port map (FDiv(2),FDiv_T(2),FClk,NOT Reset,'0','1');
FDiv_T(2) <= (FDiv(0) AND FDiv(1));

FTCPE_FDiv3: FTCPE port map (FDiv(3),FDiv_T(3),FClk,NOT Reset,'0','1');
FDiv_T(3) <= (FDiv(0) AND FDiv(1) AND FDiv(2));

FTCPE_FDiv4: FTCPE port map (FDiv(4),FDiv_T(4),FClk,NOT Reset,'0','1');
FDiv_T(4) <= (FDiv(3) AND FDiv(0) AND FDiv(1) AND FDiv(2));

FTCPE_FDivInstance/FDivCnt0: FTCPE port map (FDivInstance/FDivCnt(0),'0',NOT Clk,NOT Reset,'0','1');

FTCPE_FDivInstance/FDivCnt1: FTCPE port map (FDivInstance/FDivCnt(1),FDivInstance/FDivCnt(0),NOT Clk,NOT Reset,'0','1');

FTCPE_Hrs10: FTCPE port map (Hrs1(0),N_PZ_452,N_PZ_400,NOT Reset,'0','1');

FTCPE_Hrs1: FTCPE port map (Hrs(1),Hrs_T(1),N_PZ_400,NOT Reset,'0','1');
Hrs_T(1) <= (Hrs1(0) AND N_PZ_452);

FTCPE_Hrs2: FTCPE port map (Hrs(2),Hrs_T(2),N_PZ_400,NOT Reset,'0','1');
Hrs_T(2) <= (Hrs(1) AND Hrs1(0) AND N_PZ_452);

FTCPE_Hrs3: FTCPE port map (Hrs(3),Hrs_T(3),N_PZ_400,NOT Reset,'0','1');
Hrs_T(3) <= ((Hrs(1) AND Hrs1(0) AND N_PZ_452 AND Hrs(2) AND Hrs(3))
	OR (Hrs(1) AND Hrs1(0) AND N_PZ_452 AND Hrs(2) AND NOT Hrs(4))
	OR (Hrs(1) AND Hrs1(0) AND N_PZ_452 AND Hrs(2) AND Hrs(5)));

FTCPE_Hrs4: FTCPE port map (Hrs(4),Hrs_T(4),N_PZ_400,NOT Reset,'0','1');
Hrs_T(4) <= ((Hrs(1) AND Hrs1(0) AND N_PZ_452 AND Hrs(2) AND Hrs(3))
	OR (Hrs(1) AND Hrs1(0) AND N_PZ_452 AND Hrs(2) AND Hrs(4) AND 
	NOT Hrs(5)));

FTCPE_Hrs5: FTCPE port map (Hrs(5),Hrs_T(5),N_PZ_400,NOT Reset,'0','1');
Hrs_T(5) <= (Hrs(1) AND Hrs1(0) AND N_PZ_452 AND Hrs(2) AND Hrs(3) AND 
	Hrs(4));


MCnvInstance/B(1) <= ((Min(3) AND Min(5))
	OR (NOT Min(3) AND NOT Min(5))
	OR (Min(2) AND NOT Min(4) AND Min(5))
	OR (NOT Min(2) AND Min(4) AND NOT Min(5)));


MCnvInstance/B(2) <= ((NOT Min(3) AND Min(5) AND MCnvInstance/B(1))
	OR (Min(4) AND MCnvInstance/B(1) AND NOT N_PZ_435));

FDCPE_MachineState_FFd1: FDCPE port map (MachineState_FFd1,MachineState_FFd1_D,NOT Clk,NOT Reset,'0','1');
MachineState_FFd1_D <= NOT (((NOT MachineState_FFd2 AND NOT MachineState_FFd1 AND 
	ModeKeyStatus)
	OR (NOT MachineState_FFd2 AND NOT ModeKeyStatus AND 
	NOT SetupKeyStatus)));

FDCPE_MachineState_FFd2: FDCPE port map (MachineState_FFd2,MachineState_FFd2_D,NOT Clk,NOT Reset,'0','1');
MachineState_FFd2_D <= ((NOT MachineState_FFd2 AND NOT MachineState_FFd1 AND 
	ModeKeyStatus)
	OR (NOT MachineState_FFd2 AND NOT MachineState_FFd1 AND 
	SetupKeyStatus));

FTCPE_Min10: FTCPE port map (Min1(0),N_PZ_524,N_PZ_403,NOT Reset,'0','1');

FTCPE_Min1: FTCPE port map (Min(1),Min_T(1),N_PZ_403,NOT Reset,'0','1');
Min_T(1) <= (Min1(0) AND N_PZ_524);

FTCPE_Min2: FTCPE port map (Min(2),Min_T(2),N_PZ_403,NOT Reset,'0','1');
Min_T(2) <= (Min(1) AND Min1(0) AND N_PZ_524)
	XOR (Min(1) AND Min1(0) AND N_PZ_524 AND MCnvInstance/B(2) AND 
	Min(4) AND Min(5));

FTCPE_Min3: FTCPE port map (Min(3),Min_T(3),N_PZ_403,NOT Reset,'0','1');
Min_T(3) <= ((Min(1) AND Min1(0) AND N_PZ_524 AND Min(2))
	OR (Min(1) AND Min1(0) AND N_PZ_524 AND Min(3) AND Min(4) AND 
	Min(5)));

FTCPE_Min4: FTCPE port map (Min(4),Min_T(4),N_PZ_403,NOT Reset,'0','1');
Min_T(4) <= ((Min(1) AND Min1(0) AND N_PZ_524 AND Min(3) AND Min(2))
	OR (Min(1) AND Min1(0) AND N_PZ_524 AND Min(3) AND Min(4) AND 
	Min(5)));

FTCPE_Min5: FTCPE port map (Min(5),Min_T(5),N_PZ_403,NOT Reset,'0','1');
Min_T(5) <= ((Min(1) AND Min1(0) AND N_PZ_524 AND Min(3) AND Min(2) AND 
	Min(4))
	OR (Min(1) AND Min1(0) AND N_PZ_524 AND Min(3) AND Min(4) AND 
	Min(5)));

FDCPE_ModeKeyInstance/ShRegister0: FDCPE port map (ModeKeyInstance/ShRegister(0),ModeKeyInp,FDiv(4),'0',NOT Reset,'1');

FDCPE_ModeKeyInstance/ShRegister1: FDCPE port map (ModeKeyInstance/ShRegister(1),ModeKeyInstance/ShRegister(0),FDiv(4),'0',NOT Reset,'1');

FDCPE_ModeKeyInstance/ShRegister2: FDCPE port map (ModeKeyInstance/ShRegister(2),ModeKeyInstance/ShRegister(1),FDiv(4),'0',NOT Reset,'1');

FDCPE_ModeKeyInstance/ShRegister3: FDCPE port map (ModeKeyInstance/ShRegister(3),ModeKeyInstance/ShRegister(2),FDiv(4),'0',NOT Reset,'1');

LDCP_ModeKeyStatus: LDCP port map (ModeKeyStatus,NOT '0',,ModeKeyStatus_CLR,'0');
ModeKeyStatus_G <= (NOT ModeKeyInstance/ShRegister(0) AND 
	NOT ModeKeyInstance/ShRegister(1) AND NOT ModeKeyInstance/ShRegister(2) AND 
	NOT ModeKeyInstance/ShRegister(3));
ModeKeyStatus_CLR <= (ModeKeyInstance/ShRegister(0) AND 
	ModeKeyInstance/ShRegister(1) AND ModeKeyInstance/ShRegister(2) AND 
	ModeKeyInstance/ShRegister(3));


MuxDisplInstance/Mmux_Tetr_I1_Result10 <= ((Min(1) AND N_PZ_390 AND NOT N_PZ_453)
	OR (NOT Min(1) AND MCnvInstance/B(2) AND N_PZ_390)
	OR (MCnvInstance/B(1) AND N_PZ_390 AND NOT N_PZ_453)
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND NOT N_PZ_390 AND NOT Hrs(1) AND NOT N_PZ_382 AND N_PZ_455)
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND NOT N_PZ_390 AND N_PZ_382 AND Hrs(2) AND NOT Hrs(4))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND NOT N_PZ_390 AND N_PZ_382 AND Hrs(3) AND NOT Hrs(5))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND Sec(2) AND NOT Sec(4) AND NOT N_PZ_399 AND NOT N_PZ_390)
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND NOT N_PZ_390 AND Hrs(1) AND Hrs(2) AND Hrs(3) AND NOT Hrs(4))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND NOT N_PZ_390 AND NOT Hrs(1) AND Hrs(2) AND NOT Hrs(4) AND Hrs(5))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND Sec(1) AND NOT Sec(2) AND NOT Sec(4) AND N_PZ_399 AND NOT N_PZ_390)
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND Sec(1) AND NOT Sec(4) AND NOT Sec(5) AND N_PZ_399 AND NOT N_PZ_390)
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND NOT Sec(1) AND Sec(2) AND NOT Sec(4) AND Sec(5) AND NOT N_PZ_390)
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND NOT Sec(1) AND NOT Sec(2) AND Sec(4) AND N_PZ_399 AND NOT N_PZ_390)
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND NOT Sec(2) AND Sec(4) AND NOT Sec(5) AND NOT N_PZ_399 AND NOT N_PZ_390)
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND NOT N_PZ_390 AND Hrs(1) AND NOT N_PZ_382 AND Hrs(2) AND Hrs(4) AND 
	Hrs(5))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND NOT N_PZ_390 AND Hrs(1) AND NOT N_PZ_382 AND NOT Hrs(2) AND NOT Hrs(4) AND 
	Hrs(5))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND Sec(1) AND NOT Sec(3) AND Sec(4) AND Sec(5) AND N_PZ_399 AND 
	NOT N_PZ_390));

FTCPE_MuxDisplInstance/SelCnt0: FTCPE port map (MuxDisplInstance/SelCnt(0),'0',FDiv(3),NOT Reset,'0','1');

FTCPE_MuxDisplInstance/SelCnt1: FTCPE port map (MuxDisplInstance/SelCnt(1),MuxDisplInstance/SelCnt(0),FDiv(3),NOT Reset,'0','1');


MuxDisplInstance/Tetr(0) <= ((MuxDisplInstance/SelCnt(1) AND N_PZ_494)
	OR (NOT Min1(0) AND N_PZ_390)
	OR (NOT MuxDisplInstance/SelCnt(0) AND NOT Sec1(0) AND N_PZ_528)
	OR (NOT MuxDisplInstance/SelCnt(0) AND N_PZ_484 AND NOT Hrs1(0))
	OR (NOT Sec(1) AND NOT N_PZ_399 AND NOT DispMode AND N_PZ_494)
	OR (DispMode AND NOT MCnvInstance/B(2) AND MCnvInstance/B(1) AND 
	N_PZ_494)
	OR (Sec(3) AND Sec(5) AND NOT N_PZ_399 AND NOT DispMode AND 
	N_PZ_494)
	OR (NOT Sec(3) AND NOT Sec(5) AND NOT N_PZ_399 AND NOT DispMode AND 
	N_PZ_494)
	OR (DispMode AND NOT Min(1) AND NOT MCnvInstance/B(2) AND 
	N_PZ_453 AND N_PZ_494)
	OR (NOT Sec(2) AND Sec(3) AND Sec(4) AND NOT N_PZ_399 AND NOT DispMode AND 
	N_PZ_494));


MuxDisplInstance/Tetr(1) <= ((NOT Min(1) AND MCnvInstance/B(2) AND N_PZ_390)
	OR (MuxDisplInstance/SelCnt(0) AND N_PZ_484 AND N_PZ_382 AND 
	Hrs(4))
	OR (Min(1) AND NOT MCnvInstance/B(2) AND MCnvInstance/B(1) AND 
	N_PZ_390)
	OR (NOT Min(1) AND NOT MCnvInstance/B(1) AND N_PZ_390 AND 
	NOT N_PZ_453)
	OR (N_PZ_435 AND NOT N_PZ_390 AND NOT N_PZ_484 AND NOT N_PZ_528)
	OR (MuxDisplInstance/SelCnt(0) AND NOT Sec(4) AND Sec(5) AND 
	N_PZ_399 AND N_PZ_528)
	OR (MuxDisplInstance/SelCnt(0) AND N_PZ_484 AND NOT N_PZ_382 AND 
	NOT Hrs(4) AND Hrs(5))
	OR (MuxDisplInstance/SelCnt(0) AND N_PZ_484 AND Hrs(3) AND 
	Hrs(4) AND NOT Hrs(5))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND NOT N_PZ_390 AND Hrs(1) AND N_PZ_382)
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND NOT Sec(1) AND N_PZ_399 AND NOT N_PZ_390)
	OR (N_PZ_484 AND NOT Hrs(1) AND NOT N_PZ_382 AND NOT Hrs(4) AND Hrs(5))
	OR (MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND Sec(3) AND Sec(4) AND NOT N_PZ_399 AND NOT DispMode)
	OR (MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND Sec(4) AND NOT Sec(5) AND NOT N_PZ_399 AND NOT DispMode)
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND NOT N_PZ_390 AND NOT Hrs(1) AND NOT N_PZ_382 AND N_PZ_455)
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND NOT N_PZ_390 AND NOT Hrs(1) AND NOT N_PZ_382 AND Hrs(2) AND NOT Hrs(4))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND NOT N_PZ_390 AND NOT Hrs(1) AND NOT N_PZ_382 AND Hrs(2) AND Hrs(5))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND Sec(1) AND Sec(3) AND Sec(5) AND NOT N_PZ_399 AND NOT N_PZ_390)
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1) AND Sec(1) AND NOT Sec(3) AND NOT Sec(5) AND NOT N_PZ_399 AND NOT N_PZ_390)
	OR (NOT MuxDisplInstance/SelCnt(1) AND Sec(1) AND NOT Sec(2) AND 
	Sec(4) AND NOT Sec(5) AND NOT N_PZ_399 AND NOT DispMode));


MuxDisplInstance/Tetr(2) <= ((NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/Mmux_Tetr_I1_Result10)
	OR (NOT Sec(5) AND N_PZ_528 AND 
	NOT MuxDisplInstance/Mmux_Tetr_I1_Result10)
	OR (N_PZ_484 AND NOT Hrs(5) AND 
	NOT MuxDisplInstance/Mmux_Tetr_I1_Result10)
	OR (NOT Sec(3) AND NOT Sec(4) AND N_PZ_528 AND 
	NOT MuxDisplInstance/Mmux_Tetr_I1_Result10)
	OR (NOT Min(5) AND NOT N_PZ_484 AND NOT N_PZ_528 AND 
	NOT MuxDisplInstance/Mmux_Tetr_I1_Result10)
	OR (N_PZ_484 AND NOT Hrs(3) AND NOT Hrs(4) AND 
	NOT MuxDisplInstance/Mmux_Tetr_I1_Result10)
	OR (NOT Min(3) AND NOT Min(4) AND NOT N_PZ_484 AND NOT N_PZ_528 AND 
	NOT MuxDisplInstance/Mmux_Tetr_I1_Result10));


MuxDisplInstance/Tetr(3) <= ((Min(1) AND MCnvInstance/B(2) AND MCnvInstance/B(1) AND 
	N_PZ_390)
	OR (NOT Min(1) AND NOT MCnvInstance/B(1) AND N_PZ_390 AND 
	N_PZ_453)
	OR (MCnvInstance/B(2) AND MCnvInstance/B(1) AND N_PZ_390 AND 
	NOT N_PZ_453)
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND NOT N_PZ_390 AND Hrs(1) AND NOT N_PZ_382 AND N_PZ_455)
	OR (NOT MuxDisplInstance/SelCnt(0) AND Sec(1) AND NOT Sec(2) AND 
	Sec(4) AND N_PZ_399 AND NOT DispMode AND NOT N_PZ_390)
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND NOT N_PZ_390 AND Hrs(1) AND NOT N_PZ_382 AND Hrs(2) AND NOT Hrs(4) AND 
	Hrs(5))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND NOT N_PZ_390 AND NOT Hrs(1) AND NOT N_PZ_382 AND NOT Hrs(2) AND NOT Hrs(4) AND 
	NOT Hrs(5))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND NOT N_PZ_390 AND NOT Hrs(1) AND NOT N_PZ_382 AND Hrs(3) AND Hrs(4) AND 
	NOT Hrs(5))
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND NOT N_PZ_390 AND NOT Hrs(1) AND NOT Hrs(2) AND NOT Hrs(3) AND Hrs(4) AND 
	Hrs(5))
	OR (NOT MuxDisplInstance/SelCnt(0) AND Sec(1) AND Sec(2) AND 
	NOT Sec(4) AND Sec(5) AND N_PZ_399 AND NOT DispMode AND NOT N_PZ_390)
	OR (NOT MuxDisplInstance/SelCnt(0) AND NOT Sec(1) AND Sec(2) AND 
	Sec(3) AND NOT Sec(5) AND NOT N_PZ_399 AND NOT DispMode AND NOT N_PZ_390)
	OR (NOT MuxDisplInstance/SelCnt(0) AND NOT Sec(1) AND NOT Sec(2) AND 
	Sec(4) AND Sec(5) AND NOT N_PZ_399 AND NOT DispMode AND NOT N_PZ_390)
	OR (NOT MuxDisplInstance/SelCnt(0) AND NOT Sec(1) AND Sec(3) AND 
	NOT Sec(4) AND NOT Sec(5) AND NOT N_PZ_399 AND NOT DispMode AND NOT N_PZ_390));


N_PZ_382 <= ((Hrs(2) AND N_PZ_455)
	OR (NOT Hrs(4) AND N_PZ_455)
	OR (NOT Hrs(2) AND Hrs(3) AND Hrs(4) AND NOT Hrs(5)));


N_PZ_390 <= (NOT MuxDisplInstance/SelCnt(0) AND NOT N_PZ_484 AND NOT N_PZ_528);


N_PZ_399 <= (NOT Sec(2) AND Sec(4))
	XOR ((NOT Sec(3) AND Sec(5))
	OR (Sec(2) AND Sec(3) AND NOT Sec(4) AND NOT Sec(5))
	OR (NOT Sec(2) AND Sec(3) AND Sec(4) AND NOT Sec(5)));


N_PZ_400 <= ((Context_FFd2 AND NOT Context_FFd1)
	OR (NOT Context_FFd2 AND NOT N_PZ_403)
	OR (NOT ModeKeyStatus AND NOT N_PZ_403));


N_PZ_403 <= ((Context_FFd2 AND NOT Context_FFd1 AND ModeKeyStatus)
	OR (NOT Context_FFd2 AND NOT Context_FFd1 AND F1Hz));


N_PZ_435 <= ((Min(3) AND Min(4) AND NOT Min(5))
	OR (NOT Min(3) AND NOT Min(4) AND Min(5))
	OR (Min(2) AND Min(4) AND MCnvInstance/B(1)));


N_PZ_452 <= ((Context_FFd2 AND Context_FFd1)
	OR (Sec(1) AND NOT Context_FFd2 AND NOT Context_FFd1 AND Sec1(0) AND 
	NOT Sec(2) AND Sec(3) AND Sec(4) AND Sec(5) AND Min(1) AND Min1(0) AND 
	Min(3) AND NOT Min(2) AND Min(4) AND Min(5)));


N_PZ_453 <= ((Min(2) AND N_PZ_435)
	OR (NOT Min(2) AND NOT N_PZ_435));


N_PZ_455 <= ((Hrs(3) AND Hrs(5))
	OR (NOT Hrs(3) AND NOT Hrs(5)));


N_PZ_484 <= (MuxDisplInstance/SelCnt(1) AND DispMode);


N_PZ_494 <= ((MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1))
	OR (MuxDisplInstance/SelCnt(0) AND DispMode AND N_PZ_382)
	OR (MuxDisplInstance/SelCnt(0) AND NOT DispMode AND 
	NOT MCnvInstance/B(2) AND MCnvInstance/B(1))
	OR (MuxDisplInstance/SelCnt(0) AND NOT DispMode AND NOT Min(1) AND 
	NOT MCnvInstance/B(2) AND N_PZ_453)
	OR (MuxDisplInstance/SelCnt(0) AND DispMode AND NOT Hrs(1) AND 
	Hrs(2) AND Hrs(3) AND Hrs(4))
	OR (MuxDisplInstance/SelCnt(0) AND DispMode AND NOT Hrs(1) AND 
	NOT Hrs(2) AND Hrs(3) AND NOT Hrs(4))
	OR (MuxDisplInstance/SelCnt(0) AND DispMode AND NOT Hrs(1) AND 
	NOT Hrs(2) AND NOT Hrs(3) AND Hrs(4) AND Hrs(5)));


N_PZ_524 <= ((Context_FFd2 AND NOT Context_FFd1)
	OR (Sec(1) AND NOT Context_FFd1 AND Sec1(0) AND NOT Sec(2) AND 
	Sec(3) AND Sec(4) AND Sec(5)));


N_PZ_528 <= (NOT MuxDisplInstance/SelCnt(1) AND NOT DispMode);

FTCPE_Sec10: FTCPE port map (Sec1(0),Sec1_T(0),F1Hz,NOT ClrPresc_or0000,'0','1');
Sec1_T(0) <= (NOT Context_FFd2 AND NOT Context_FFd1);

FTCPE_Sec1: FTCPE port map (Sec(1),Sec_T(1),F1Hz,NOT ClrPresc_or0000,'0','1');
Sec_T(1) <= (NOT Context_FFd2 AND NOT Context_FFd1 AND Sec1(0));

FTCPE_Sec2: FTCPE port map (Sec(2),Sec_T(2),F1Hz,NOT ClrPresc_or0000,'0','1');
Sec_T(2) <= ((Sec(1) AND NOT Context_FFd2 AND NOT Context_FFd1 AND Sec1(0) AND 
	NOT Sec(3))
	OR (Sec(1) AND NOT Context_FFd2 AND NOT Context_FFd1 AND Sec1(0) AND 
	NOT Sec(5))
	OR (Sec(1) AND NOT Context_FFd2 AND NOT Context_FFd1 AND Sec1(0) AND 
	NOT N_PZ_399));

FTCPE_Sec3: FTCPE port map (Sec(3),Sec_T(3),F1Hz,NOT ClrPresc_or0000,'0','1');
Sec_T(3) <= ((Sec(1) AND NOT Context_FFd2 AND NOT Context_FFd1 AND Sec1(0) AND 
	Sec(2))
	OR (Sec(1) AND NOT Context_FFd2 AND NOT Context_FFd1 AND Sec1(0) AND 
	Sec(3) AND Sec(4) AND Sec(5)));

FTCPE_Sec4: FTCPE port map (Sec(4),Sec_T(4),F1Hz,NOT ClrPresc_or0000,'0','1');
Sec_T(4) <= ((Sec(1) AND NOT Context_FFd2 AND NOT Context_FFd1 AND Sec1(0) AND 
	Sec(2) AND Sec(3))
	OR (Sec(1) AND NOT Context_FFd2 AND NOT Context_FFd1 AND Sec1(0) AND 
	Sec(3) AND Sec(4) AND Sec(5)));

FTCPE_Sec5: FTCPE port map (Sec(5),Sec_T(5),F1Hz,NOT ClrPresc_or0000,'0','1');
Sec_T(5) <= ((Sec(1) AND NOT Context_FFd2 AND NOT Context_FFd1 AND Sec1(0) AND 
	Sec(2) AND Sec(3) AND Sec(4))
	OR (Sec(1) AND NOT Context_FFd2 AND NOT Context_FFd1 AND Sec1(0) AND 
	Sec(3) AND Sec(4) AND Sec(5)));


Seg_A <= NOT ((NOT MuxDisplInstance/Tetr(1) AND 
	NOT MuxDisplInstance/Tetr(0))
	XOR ((NOT MuxDisplInstance/Tetr(1) AND 
	NOT MuxDisplInstance/Tetr(3) AND NOT MuxDisplInstance/Tetr(2))
	OR (NOT MuxDisplInstance/Tetr(0) AND 
	MuxDisplInstance/Tetr(3) AND MuxDisplInstance/Tetr(2))));


Seg_B <= NOT ((MuxDisplInstance/Tetr(0) AND 
	NOT MuxDisplInstance/Tetr(2))
	XOR ((MuxDisplInstance/Tetr(1) AND 
	NOT MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(3))
	OR (NOT MuxDisplInstance/Tetr(1) AND 
	NOT MuxDisplInstance/Tetr(3) AND NOT MuxDisplInstance/Tetr(2))));


Seg_C <= NOT (((MuxDisplInstance/Tetr(1) AND 
	MuxDisplInstance/Tetr(3) AND NOT MuxDisplInstance/Tetr(2))
	OR (MuxDisplInstance/Tetr(0) AND 
	MuxDisplInstance/Tetr(3) AND NOT MuxDisplInstance/Tetr(2))
	OR (MuxDisplInstance/Tetr(1) AND 
	MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(3) AND 
	MuxDisplInstance/Tetr(2))));


Seg_D <= NOT (((MuxDisplInstance/Tetr(1) AND 
	NOT MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(2))
	OR (MuxDisplInstance/Tetr(1) AND 
	MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(3) AND 
	MuxDisplInstance/Tetr(2))
	OR (NOT MuxDisplInstance/Tetr(1) AND 
	MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(3) AND 
	NOT MuxDisplInstance/Tetr(2))
	OR (NOT MuxDisplInstance/Tetr(1) AND 
	NOT MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(3) AND 
	MuxDisplInstance/Tetr(2))));


Seg_E <= NOT (((NOT MuxDisplInstance/Tetr(0) AND 
	NOT MuxDisplInstance/Tetr(3))
	OR (NOT MuxDisplInstance/Tetr(1) AND 
	NOT MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(2))
	OR (NOT MuxDisplInstance/Tetr(1) AND 
	NOT MuxDisplInstance/Tetr(3) AND NOT MuxDisplInstance/Tetr(2))));


Seg_F <= NOT ((NOT MuxDisplInstance/Tetr(0) AND 
	NOT MuxDisplInstance/Tetr(3))
	XOR ((NOT MuxDisplInstance/Tetr(1) AND 
	NOT MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(2))
	OR (MuxDisplInstance/Tetr(1) AND 
	MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(3) AND 
	MuxDisplInstance/Tetr(2))));


Seg_G <= NOT (((NOT MuxDisplInstance/Tetr(1) AND 
	NOT MuxDisplInstance/Tetr(3) AND MuxDisplInstance/Tetr(2))
	OR (MuxDisplInstance/Tetr(1) AND 
	NOT MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(3) AND 
	NOT MuxDisplInstance/Tetr(2))
	OR (NOT MuxDisplInstance/Tetr(1) AND 
	MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(3) AND 
	NOT MuxDisplInstance/Tetr(2))));


Seg_K <= ((MuxDisplInstance/SelCnt(1) AND Context_FFd2 AND 
	Context_FFd1)
	OR (NOT MuxDisplInstance/SelCnt(1) AND Context_FFd2 AND 
	NOT Context_FFd1)
	OR (NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1) AND NOT Context_FFd2 AND NOT Context_FFd1 AND NOT F1Hz));

FDCPE_SetupKeyInstance/ShRegister0: FDCPE port map (SetupKeyInstance/ShRegister(0),SetupKeyInp,FDiv(4),'0',NOT Reset,'1');

FDCPE_SetupKeyInstance/ShRegister1: FDCPE port map (SetupKeyInstance/ShRegister(1),SetupKeyInstance/ShRegister(0),FDiv(4),'0',NOT Reset,'1');

FDCPE_SetupKeyInstance/ShRegister2: FDCPE port map (SetupKeyInstance/ShRegister(2),SetupKeyInstance/ShRegister(1),FDiv(4),'0',NOT Reset,'1');

FDCPE_SetupKeyInstance/ShRegister3: FDCPE port map (SetupKeyInstance/ShRegister(3),SetupKeyInstance/ShRegister(2),FDiv(4),'0',NOT Reset,'1');

LDCP_SetupKeyStatus: LDCP port map (SetupKeyStatus,NOT '0',,SetupKeyStatus_CLR,'0');
SetupKeyStatus_G <= (NOT SetupKeyInstance/ShRegister(0) AND 
	NOT SetupKeyInstance/ShRegister(1) AND NOT SetupKeyInstance/ShRegister(2) AND 
	NOT SetupKeyInstance/ShRegister(3));
SetupKeyStatus_CLR <= (SetupKeyInstance/ShRegister(0) AND 
	SetupKeyInstance/ShRegister(1) AND SetupKeyInstance/ShRegister(2) AND 
	SetupKeyInstance/ShRegister(3));


Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE); 
 FDDCPE (Q,D,C,CLR,PRE,CE); 
 FTCPE (Q,D,C,CLR,PRE,CE); 
 FTDCPE (Q,D,C,CLR,PRE,CE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC2C256-6-VQ100


   --------------------------------------------------  
  /100 98  96  94  92  90  88  86  84  82  80  78  76  \
 |   99  97  95  93  91  89  87  85  83  81  79  77    |
 | 1                                               75  | 
 | 2                                               74  | 
 | 3                                               73  | 
 | 4                                               72  | 
 | 5                                               71  | 
 | 6                                               70  | 
 | 7                                               69  | 
 | 8                                               68  | 
 | 9                                               67  | 
 | 10                                              66  | 
 | 11                                              65  | 
 | 12                                              64  | 
 | 13                XC2C256-6-VQ100               63  | 
 | 14                                              62  | 
 | 15                                              61  | 
 | 16                                              60  | 
 | 17                                              59  | 
 | 18                                              58  | 
 | 19                                              57  | 
 | 20                                              56  | 
 | 21                                              55  | 
 | 22                                              54  | 
 | 23                                              53  | 
 | 24                                              52  | 
 | 25                                              51  | 
 |   27  29  31  33  35  37  39  41  43  45  47  49    |
  \26  28  30  32  34  36  38  40  42  44  46  48  50  /
   --------------------------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 Seg_K                            51 VCCIO-1.8                     
  2 Seg_G                            52 KPR                           
  3 Seg_F                            53 KPR                           
  4 Seg_E                            54 KPR                           
  5 VCCAUX                           55 ModeKeyInp                    
  6 Seg_D                            56 SetupKeyInp                   
  7 Seg_C                            57 VCC                           
  8 Seg_A                            58 KPR                           
  9 Seg_B                            59 KPR                           
 10 KPR                              60 KPR                           
 11 KPR                              61 KPR                           
 12 KPR                              62 GND                           
 13 KPR                              63 KPR                           
 14 KPR                              64 KPR                           
 15 KPR                              65 Reset                         
 16 KPR                              66 KPR                           
 17 KPR                              67 KPR                           
 18 DSel0                            68 KPR                           
 19 DSel1                            69 GND                           
 20 VCCIO-1.8                        70 KPR                           
 21 GND                              71 KPR                           
 22 Clk                              72 KPR                           
 23 KPR                              73 KPR                           
 24 DSel2                            74 KPR                           
 25 GND                              75 GND                           
 26 VCC                              76 KPR                           
 27 DSel3                            77 KPR                           
 28 KPR                              78 KPR                           
 29 KPR                              79 KPR                           
 30 KPR                              80 KPR                           
 31 GND                              81 KPR                           
 32 KPR                              82 KPR                           
 33 KPR                              83 TDO                           
 34 KPR                              84 GND                           
 35 KPR                              85 KPR                           
 36 KPR                              86 KPR                           
 37 KPR                              87 KPR                           
 38 VCCIO-1.8                        88 VCCIO-1.8                     
 39 KPR                              89 KPR                           
 40 KPR                              90 KPR                           
 41 KPR                              91 KPR                           
 42 KPR                              92 KPR                           
 43 KPR                              93 KPR                           
 44 KPR                              94 KPR                           
 45 TDI                              95 KPR                           
 46 KPR                              96 KPR                           
 47 TMS                              97 KPR                           
 48 TCK                              98 VCCIO-1.8                     
 49 KPR                              99 KPR                           
 50 KPR                             100 GND                           


Legend :  NC  = Not Connected, unbonded pin
        PGND  = Unused I/O configured as additional Ground pin
         KPR  = Unused I/O with weak keeper (leave unconnected)
         WPU  = Unused I/O with weak pull up (leave unconnected)
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
      VCCAUX  = Power supply for JTAG pins
   VCCIO-3.3  = I/O supply voltage for LVTTL, LVCMOS33, SSTL3_I
   VCCIO-2.5  = I/O supply voltage for LVCMOS25, SSTL2_I
   VCCIO-1.8  = I/O supply voltage for LVCMOS18
   VCCIO-1.5  = I/O supply voltage for LVCMOS15, HSTL_I
        VREF  = Reference voltage for indicated input standard
       *VREF  = Reference voltage pin selected by software
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc2c256-6-VQ100
Optimization Method                         : DENSITY
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Set Unused I/O Pin Termination              : KEEPER
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
Enable Input Registers                      : ON
Function Block Fan-in Limit                 : 38
Use DATA_GATE Attribute                     : ON
Set Tristate Outputs to Termination Mode    : KEEPER
Default Voltage Standard for All Outputs    : LVCMOS18
Input Limit                                 : 32
Pterm Limit                                 : 28