Equations

********** Mapped Logic **********
FTCPE_Cnt0: FTCPE port map (Cnt(0),'0',FDiv(19),NOT Reset,'0','1');
FTCPE_Cnt1: FTCPE port map (Cnt(1),Cnt(0),FDiv(19),NOT Reset,'0','1');
FTCPE_Cnt2: FTCPE port map (Cnt(2),Cnt_T(2),FDiv(19),NOT Reset,'0','1');
     Cnt_T(2) <= (Cnt(0) AND Cnt(1));
FTCPE_Cnt3: FTCPE port map (Cnt(3),Cnt_T(3),FDiv(19),NOT Reset,'0','1');
     Cnt_T(3) <= (Cnt(0) AND Cnt(1) AND Cnt(2));
FTCPE_Cnt4: FTCPE port map (Cnt(4),Cnt_T(4),FDiv(19),NOT Reset,'0','1');
     Cnt_T(4) <= (Cnt(0) AND Cnt(1) AND Cnt(2) AND Cnt(3));
FTCPE_Cnt5: FTCPE port map (Cnt(5),Cnt_T(5),FDiv(19),NOT Reset,'0','1');
     Cnt_T(5) <= (Cnt(0) AND Cnt(1) AND Cnt(2) AND Cnt(3) AND Cnt(4));
FTCPE_Cnt6: FTCPE port map (Cnt(6),Cnt_T(6),FDiv(19),NOT Reset,'0','1');
     Cnt_T(6) <= (Cnt(0) AND Cnt(1) AND Cnt(2) AND Cnt(3) AND Cnt(4) AND
      Cnt(5));
FTCPE_Cnt7: FTCPE port map (Cnt(7),Cnt_T(7),FDiv(19),NOT Reset,'0','1');
     Cnt_T(7) <= (Cnt(0) AND Cnt(1) AND Cnt(2) AND Cnt(3) AND Cnt(4) AND
      Cnt(5) AND Cnt(6));
FTCPE_Cnt8: FTCPE port map (Cnt(8),Cnt_T(8),FDiv(19),NOT Reset,'0','1');
     Cnt_T(8) <= (Cnt(0) AND Cnt(1) AND Cnt(2) AND Cnt(3) AND Cnt(4) AND
      Cnt(5) AND Cnt(6) AND Cnt(7));
FTCPE_Cnt9: FTCPE port map (Cnt(9),Cnt_T(9),FDiv(19),NOT Reset,'0','1');
     Cnt_T(9) <= (Cnt(0) AND Cnt(1) AND Cnt(2) AND Cnt(3) AND Cnt(4) AND
      Cnt(5) AND Cnt(6) AND Cnt(7) AND Cnt(8));
FTCPE_Cnt10: FTCPE port map (Cnt(10),Cnt_T(10),FDiv(19),NOT Reset,'0','1');
     Cnt_T(10) <= (Cnt(9) AND Cnt(0) AND Cnt(1) AND Cnt(2) AND Cnt(3) AND
      Cnt(4) AND Cnt(5) AND Cnt(6) AND Cnt(7) AND Cnt(8));
FTCPE_Cnt11: FTCPE port map (Cnt(11),Cnt_T(11),FDiv(19),NOT Reset,'0','1');
     Cnt_T(11) <= (Cnt(9) AND Cnt(0) AND Cnt(1) AND Cnt(2) AND Cnt(3) AND
      Cnt(4) AND Cnt(5) AND Cnt(6) AND Cnt(7) AND Cnt(8) AND Cnt(10));
FTCPE_Cnt12: FTCPE port map (Cnt(12),Cnt_T(12),FDiv(19),NOT Reset,'0','1');
     Cnt_T(12) <= (Cnt(9) AND Cnt(0) AND Cnt(1) AND Cnt(2) AND Cnt(3) AND
      Cnt(4) AND Cnt(5) AND Cnt(6) AND Cnt(7) AND Cnt(8) AND Cnt(10) AND
      Cnt(11));
FTCPE_Cnt13: FTCPE port map (Cnt(13),Cnt_T(13),FDiv(19),NOT Reset,'0','1');
     Cnt_T(13) <= (Cnt(9) AND Cnt(0) AND Cnt(1) AND Cnt(2) AND Cnt(3) AND
      Cnt(4) AND Cnt(5) AND Cnt(6) AND Cnt(7) AND Cnt(8) AND Cnt(10) AND
      Cnt(11) AND Cnt(12));
FTCPE_Cnt14: FTCPE port map (Cnt(14),Cnt_T(14),FDiv(19),NOT Reset,'0','1');
     Cnt_T(14) <= (Cnt(9) AND Cnt(0) AND Cnt(1) AND Cnt(2) AND Cnt(3) AND
      Cnt(4) AND Cnt(5) AND Cnt(6) AND Cnt(7) AND Cnt(8) AND Cnt(13) AND
      Cnt(10) AND Cnt(11) AND Cnt(12));
FTCPE_Cnt15: FTCPE port map (Cnt(15),Cnt_T(15),FDiv(19),NOT Reset,'0','1');
     Cnt_T(15) <= (Cnt(9) AND Cnt(0) AND Cnt(1) AND Cnt(2) AND Cnt(3) AND
      Cnt(4) AND Cnt(5) AND Cnt(6) AND Cnt(7) AND Cnt(8) AND Cnt(13) AND
      Cnt(10) AND Cnt(11) AND Cnt(12) AND Cnt(14));
DSel0 <= NOT ((NOT MuxDisplInstance/SelCnt(0) AND
      NOT MuxDisplInstance/SelCnt(1)));
DSel1 <= NOT ((MuxDisplInstance/SelCnt(0) AND
      NOT MuxDisplInstance/SelCnt(1)));
DSel2 <= NOT ((NOT MuxDisplInstance/SelCnt(0) AND
      MuxDisplInstance/SelCnt(1)));
DSel3 <= NOT ((MuxDisplInstance/SelCnt(0) AND
      MuxDisplInstance/SelCnt(1)));
FTCPE_FDiv0: FTCPE port map (FDiv(0),'0',NOT Clk,NOT Reset,'0','1');
FTCPE_FDiv1: FTCPE port map (FDiv(1),FDiv(0),NOT Clk,NOT Reset,'0','1');
FTCPE_FDiv2: FTCPE port map (FDiv(2),FDiv_T(2),NOT Clk,NOT Reset,'0','1');
     FDiv_T(2) <= (FDiv(0) AND FDiv(1));
FTCPE_FDiv3: FTCPE port map (FDiv(3),FDiv_T(3),NOT Clk,NOT Reset,'0','1');
     FDiv_T(3) <= (FDiv(0) AND FDiv(1) AND FDiv(2));
FTCPE_FDiv4: FTCPE port map (FDiv(4),FDiv_T(4),NOT Clk,NOT Reset,'0','1');
     FDiv_T(4) <= (FDiv(0) AND FDiv(1) AND FDiv(2) AND FDiv(3));
FTCPE_FDiv5: FTCPE port map (FDiv(5),FDiv_T(5),NOT Clk,NOT Reset,'0','1');
     FDiv_T(5) <= (FDiv(0) AND FDiv(1) AND FDiv(2) AND FDiv(3) AND
      FDiv(4));
FTCPE_FDiv6: FTCPE port map (FDiv(6),FDiv_T(6),NOT Clk,NOT Reset,'0','1');
     FDiv_T(6) <= (FDiv(0) AND FDiv(1) AND FDiv(2) AND FDiv(3) AND
      FDiv(4) AND FDiv(5));
FTCPE_FDiv7: FTCPE port map (FDiv(7),FDiv_T(7),NOT Clk,NOT Reset,'0','1');
     FDiv_T(7) <= (FDiv(0) AND FDiv(1) AND FDiv(2) AND FDiv(3) AND
      FDiv(4) AND FDiv(5) AND FDiv(6));
FTCPE_FDiv8: FTCPE port map (FDiv(8),FDiv_T(8),NOT Clk,NOT Reset,'0','1');
     FDiv_T(8) <= (FDiv(0) AND FDiv(1) AND FDiv(2) AND FDiv(3) AND
      FDiv(4) AND FDiv(5) AND FDiv(6) AND FDiv(7));
FTCPE_FDiv9: FTCPE port map (FDiv(9),FDiv_T(9),NOT Clk,NOT Reset,'0','1');
     FDiv_T(9) <= (FDiv(0) AND FDiv(1) AND FDiv(2) AND FDiv(3) AND
      FDiv(4) AND FDiv(5) AND FDiv(6) AND FDiv(7) AND FDiv(8));
FTCPE_FDiv10: FTCPE port map (FDiv(10),FDiv_T(10),NOT Clk,NOT Reset,'0','1');
     FDiv_T(10) <= (FDiv(0) AND FDiv(1) AND FDiv(2) AND FDiv(3) AND
      FDiv(4) AND FDiv(5) AND FDiv(6) AND FDiv(7) AND FDiv(8) AND
      FDiv(9));
FTCPE_FDiv11: FTCPE port map (FDiv(11),FDiv_T(11),NOT Clk,NOT Reset,'0','1');
     FDiv_T(11) <= (FDiv(0) AND FDiv(10) AND FDiv(1) AND FDiv(2) AND
      FDiv(3) AND FDiv(4) AND FDiv(5) AND FDiv(6) AND FDiv(7) AND
      FDiv(8) AND FDiv(9));
FTCPE_FDiv12: FTCPE port map (FDiv(12),FDiv_T(12),NOT Clk,NOT Reset,'0','1');
     FDiv_T(12) <= (FDiv(11) AND FDiv(0) AND FDiv(10) AND FDiv(1) AND
      FDiv(2) AND FDiv(3) AND FDiv(4) AND FDiv(5) AND FDiv(6) AND
      FDiv(7) AND FDiv(8) AND FDiv(9));
FTCPE_FDiv13: FTCPE port map (FDiv(13),FDiv_T(13),NOT Clk,NOT Reset,'0','1');
     FDiv_T(13) <= (FDiv(11) AND FDiv(0) AND FDiv(10) AND FDiv(1) AND
      FDiv(2) AND FDiv(3) AND FDiv(4) AND FDiv(5) AND FDiv(6) AND
      FDiv(7) AND FDiv(8) AND FDiv(9) AND FDiv(12));
FTCPE_FDiv14: FTCPE port map (FDiv(14),FDiv_T(14),NOT Clk,NOT Reset,'0','1');
     FDiv_T(14) <= (FDiv(11) AND FDiv(0) AND FDiv(10) AND FDiv(1) AND
      FDiv(2) AND FDiv(3) AND FDiv(4) AND FDiv(5) AND FDiv(6) AND
      FDiv(7) AND FDiv(8) AND FDiv(9) AND FDiv(12) AND FDiv(13));
FTCPE_FDiv15: FTCPE port map (FDiv(15),FDiv_T(15),NOT Clk,NOT Reset,'0','1');
     FDiv_T(15) <= (FDiv(11) AND FDiv(0) AND FDiv(10) AND FDiv(1) AND
      FDiv(2) AND FDiv(3) AND FDiv(4) AND FDiv(5) AND FDiv(6) AND
      FDiv(7) AND FDiv(8) AND FDiv(9) AND FDiv(12) AND FDiv(13) AND
      FDiv(14));
FTCPE_FDiv16: FTCPE port map (FDiv(16),FDiv_T(16),NOT Clk,NOT Reset,'0','1');
     FDiv_T(16) <= (FDiv(11) AND FDiv(0) AND FDiv(10) AND FDiv(1) AND
      FDiv(2) AND FDiv(3) AND FDiv(4) AND FDiv(5) AND FDiv(6) AND
      FDiv(7) AND FDiv(8) AND FDiv(9) AND FDiv(12) AND FDiv(13) AND
      FDiv(14) AND FDiv(15));
FTCPE_FDiv17: FTCPE port map (FDiv(17),FDiv_T(17),NOT Clk,NOT Reset,'0','1');
     FDiv_T(17) <= (FDiv(11) AND FDiv(0) AND FDiv(10) AND FDiv(1) AND
      FDiv(2) AND FDiv(3) AND FDiv(4) AND FDiv(5) AND FDiv(6) AND
      FDiv(7) AND FDiv(8) AND FDiv(9) AND FDiv(12) AND FDiv(13) AND
      FDiv(14) AND FDiv(15) AND FDiv(16));
FTCPE_FDiv18: FTCPE port map (FDiv(18),FDiv_T(18),NOT Clk,NOT Reset,'0','1');
     FDiv_T(18) <= (FDiv(11) AND FDiv(0) AND FDiv(10) AND FDiv(1) AND
      FDiv(2) AND FDiv(3) AND FDiv(4) AND FDiv(5) AND FDiv(6) AND
      FDiv(7) AND FDiv(8) AND FDiv(9) AND FDiv(12) AND FDiv(13) AND
      FDiv(14) AND FDiv(15) AND FDiv(16) AND FDiv(17));
FTCPE_FDiv19: FTCPE port map (FDiv(19),FDiv_T(19),NOT Clk,NOT Reset,'0','1');
     FDiv_T(19) <= (FDiv(11) AND FDiv(0) AND FDiv(10) AND FDiv(1) AND
      FDiv(2) AND FDiv(3) AND FDiv(4) AND FDiv(5) AND FDiv(6) AND
      FDiv(7) AND FDiv(8) AND FDiv(9) AND FDiv(12) AND FDiv(13) AND
      FDiv(14) AND FDiv(15) AND FDiv(16) AND FDiv(17) AND FDiv(18));
FTCPE_MuxDisplInstance/SelCnt0: FTCPE port map (MuxDisplInstance/SelCnt(0),'0',FDiv(11),NOT Reset,'0','1');
FTCPE_MuxDisplInstance/SelCnt1: FTCPE port map (MuxDisplInstance/SelCnt(1),MuxDisplInstance/SelCnt(0),FDiv(11),NOT Reset,'0','1');
MuxDisplInstance/Tetr(0) <= ((Cnt(0) AND NOT DSel0)
      OR (Cnt(4) AND NOT Seg_K)
      OR (Cnt(8) AND NOT DSel2)
      OR (Cnt(12) AND NOT DSel3));
MuxDisplInstance/Tetr(1) <= ((Cnt(9) AND NOT DSel2)
      OR (Cnt(1) AND NOT DSel0)
      OR (Cnt(5) AND NOT Seg_K)
      OR (Cnt(13) AND NOT DSel3));
MuxDisplInstance/Tetr(2) <= ((Cnt(2) AND NOT DSel0)
      OR (Cnt(6) AND NOT Seg_K)
      OR (NOT DSel2 AND Cnt(10))
      OR (NOT DSel3 AND Cnt(14)));
MuxDisplInstance/Tetr(3) <= ((Cnt(3) AND NOT DSel0)
      OR (Cnt(7) AND NOT Seg_K)
      OR (NOT DSel2 AND Cnt(11))
      OR (NOT DSel3 AND Cnt(15)));
Seg_A <= (NOT MuxDisplInstance/Tetr(1) AND
      MuxDisplInstance/Tetr(0))
      XOR ((NOT MuxDisplInstance/Tetr(1) AND
      NOT MuxDisplInstance/Tetr(3) AND MuxDisplInstance/Tetr(2))
      OR (MuxDisplInstance/Tetr(0) AND
      MuxDisplInstance/Tetr(3) AND NOT MuxDisplInstance/Tetr(2)));
Seg_B <= (NOT MuxDisplInstance/Tetr(0) AND
      MuxDisplInstance/Tetr(2))
      XOR ((MuxDisplInstance/Tetr(1) AND
      MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(3))
      OR (NOT MuxDisplInstance/Tetr(1) AND
      NOT MuxDisplInstance/Tetr(3) AND MuxDisplInstance/Tetr(2)));
Seg_C <= ((MuxDisplInstance/Tetr(1) AND
      MuxDisplInstance/Tetr(3) AND MuxDisplInstance/Tetr(2))
      OR (NOT MuxDisplInstance/Tetr(0) AND
      MuxDisplInstance/Tetr(3) AND MuxDisplInstance/Tetr(2))
      OR (MuxDisplInstance/Tetr(1) AND
      NOT MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(3) AND
      NOT MuxDisplInstance/Tetr(2)));
Seg_D <= ((MuxDisplInstance/Tetr(1) AND
      MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(2))
      OR (MuxDisplInstance/Tetr(1) AND
      NOT MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(3) AND
      NOT MuxDisplInstance/Tetr(2))
      OR (NOT MuxDisplInstance/Tetr(1) AND
      MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(3) AND
      NOT MuxDisplInstance/Tetr(2))
      OR (NOT MuxDisplInstance/Tetr(1) AND
      NOT MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(3) AND
      MuxDisplInstance/Tetr(2)));
Seg_E <= ((MuxDisplInstance/Tetr(0) AND
      NOT MuxDisplInstance/Tetr(3))
      OR (NOT MuxDisplInstance/Tetr(1) AND
      MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(2))
      OR (NOT MuxDisplInstance/Tetr(1) AND
      NOT MuxDisplInstance/Tetr(3) AND MuxDisplInstance/Tetr(2)));
Seg_F <= (MuxDisplInstance/Tetr(0) AND
      NOT MuxDisplInstance/Tetr(3))
      XOR ((NOT MuxDisplInstance/Tetr(1) AND
      MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(2))
      OR (MuxDisplInstance/Tetr(1) AND
      NOT MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(3) AND
      NOT MuxDisplInstance/Tetr(2)));
Seg_G <= ((NOT MuxDisplInstance/Tetr(1) AND
      NOT MuxDisplInstance/Tetr(3) AND NOT MuxDisplInstance/Tetr(2))
      OR (MuxDisplInstance/Tetr(1) AND
      MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(3) AND
      MuxDisplInstance/Tetr(2))
      OR (NOT MuxDisplInstance/Tetr(1) AND
      NOT MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(3) AND
      MuxDisplInstance/Tetr(2)));
Seg_K <= NOT ((MuxDisplInstance/SelCnt(0) AND
      NOT MuxDisplInstance/SelCnt(1)));
Register Legend:
      FDCPE (Q,D,C,CLR,PRE,CE);
      FDDCPE (Q,D,C,CLR,PRE,CE);
      FTCPE (Q,D,C,CLR,PRE,CE);
      FTDCPE (Q,D,C,CLR,PRE,CE);
      LDCP (Q,D,G,CLR,PRE);