cpldfit: version J.36 Xilinx Inc. Fitter Report Design Name: Clock Date: 4-23-2009, 2:32PM Device Used: XC2C256-6-TQ144 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 98 /256 ( 38%) 244 /896 ( 27%) 167 /640 ( 26%) 68 /256 ( 27%) 16 /118 ( 14%) ** Function Block Resources ** Function Mcells FB Inps Pterms IO CTC CTR CTS CTE Block Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot FB1 16/16* 18/40 20/56 0/ 6 1/1* 1/1* 1/1* 0/1 FB2 5/16 33/40 56/56* 0/ 8 0/1 0/1 0/1 0/1 FB3 16/16* 33/40 40/56 0/ 6 1/1* 1/1* 0/1 0/1 FB4 16/16* 21/40 32/56 0/ 8 0/1 1/1* 0/1 0/1 FB5 16/16* 18/40 36/56 0/ 5 1/1* 1/1* 0/1 0/1 FB6 16/16* 25/40 32/56 0/ 8 1/1* 1/1* 0/1 0/1 FB7 0/16 0/40 0/56 0/ 8 0/1 0/1 0/1 0/1 FB8 0/16 0/40 0/56 0/ 8 0/1 0/1 0/1 0/1 FB9 0/16 0/40 0/56 0/ 8 0/1 0/1 0/1 0/1 FB10 0/16 0/40 0/56 0/ 9 0/1 0/1 0/1 0/1 FB11 4/16 2/40 4/56 4/ 8 0/1 0/1 0/1 0/1 FB12 1/16 2/40 2/56 0/ 6 1/1* 0/1 1/1* 0/1 FB13 0/16 0/40 0/56 0/ 8 0/1 0/1 0/1 0/1 FB14 1/16 4/40 3/56 1/ 8 0/1 0/1 0/1 0/1 FB15 0/16 0/40 0/56 0/ 7 0/1 0/1 0/1 0/1 FB16 7/16 11/40 19/56 7/ 7* 0/1 0/1 0/1 0/1 ----- ------- ------- ----- --- --- --- --- Total 98/256 167/640 244/896 12/118 5/16 5/16 2/16 0/16 CTC - Control Term Clock CTR - Control Term Reset CTS - Control Term Set CTE - Control Term Output Enable * - Resource is exhausted ** Global Control Resources ** GCK GSR GTS Used/Tot Used/Tot Used/Tot 1/3 0/1 0/4 Signal 'Clk' mapped onto global clock net GCK2. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 3 3 | I/O : 13 108 Output : 12 12 | GCK/IO : 1 3 Bidirectional : 0 0 | GTS/IO : 0 4 GCK : 1 1 | GSR/IO : 1 1 GTS : 0 0 | CDR/IO : 0 1 GSR : 0 0 | DGE/IO : 1 1 ---- ---- Total 16 16 End of Mapped Resource Summary ************************* Summary of Mapped Logic ************************ ** 12 Outputs ** Signal Total Total Loc Pin Pin Pin I/O I/O Slew Reg Reg Init Name Pts Inps No. Type Use STD Style Rate Use State DSel0 1 2 FB11_13 126 I/O O LVCMOS18 FAST DSel1 1 2 FB11_14 128 I/O O LVCMOS18 FAST DSel2 1 2 FB11_15 129 I/O O LVCMOS18 FAST DSel3 1 2 FB11_16 130 I/O O LVCMOS18 FAST Seg_G 3 4 FB14_16 61 I/O O LVCMOS18 FAST Seg_C 3 4 FB16_5 60 I/O O LVCMOS18 FAST Seg_K 4 7 FB16_6 59 I/O O LVCMOS18 FAST Seg_D 4 4 FB16_11 58 I/O O LVCMOS18 FAST Seg_E 3 4 FB16_12 57 I/O O LVCMOS18 FAST Seg_A 3 4 FB16_13 56 I/O O LVCMOS18 FAST Seg_F 3 4 FB16_15 54 I/O O LVCMOS18 FAST Seg_B 3 4 FB16_16 53 I/O O LVCMOS18 FAST ** 86 Buried Nodes ** Signal Total Total Loc Reg Reg Init Name Pts Inps Use State ModeKeyInstance/ShRegister<2> 3 3 FB1_1 DFF RESET ModeKeyInstance/ShRegister<1> 3 3 FB1_2 DFF RESET ModeKeyInstance/ShRegister<0> 4 4 FB1_3 DFF RESET SetupKeyInstance/ShRegister<3> 3 3 FB1_4 DFF RESET FClk 2 8 FB1_5 TFF RESET SetupKeyInstance/ShRegister<2> 3 3 FB1_6 DFF RESET FDivInstance/FDivCnt<6> 2 7 FB1_7 TFF RESET FDivInstance/FDivCnt<5> 2 6 FB1_8 TFF RESET FDivInstance/FDivCnt<4> 2 5 FB1_9 TFF RESET FDivInstance/FDivCnt<3> 2 4 FB1_10 TFF RESET FDivInstance/FDivCnt<2> 2 3 FB1_11 TFF RESET SetupKeyInstance/ShRegister<1> 3 3 FB1_12 DFF RESET ModeKeyStatus 2 4 FB1_13 LATCH RESET ModeKeyInstance/ShRegister<3> 3 3 FB1_14 DFF RESET FDivInstance/FDivCnt<1> 2 2 FB1_15 TFF RESET FDivInstance/FDivCnt<0> 1 1 FB1_16 TFF RESET N_PZ_570 2 8 FB2_8 N_PZ_496 2 12 FB2_9 MuxDisplInstance/Tetr<3> 10 24 FB2_10 MuxDisplInstance/Tetr<1> 15 26 FB2_11 MuxDisplInstance/Tetr<2> 27 27 FB2_16 Hrs<3> 5 9 FB3_1 TFF RESET Hrs<4> 4 9 FB3_2 TFF RESET Hrs<5> 3 8 FB3_3 TFF RESET N_PZ_498 2 3 FB3_4 Hrs<2> 3 5 FB3_5 TFF RESET N_PZ_497 2 3 FB3_6 N_PZ_519 1 3 FB3_7 Min<1> 3 4 FB3_8 TFF RESET N_PZ_407 3 6 FB3_9 Min<2> 4 7 FB3_10 TFF RESET Min<5> 4 9 FB3_11 TFF RESET Min<4> 4 9 FB3_12 TFF RESET Min<3> 4 9 FB3_13 TFF RESET Min1<0> 3 3 FB3_14 TFF RESET MuxDisplInstance/Tetr<0> 10 21 FB3_15 N_PZ_576 2 3 FB3_16 F2HzDiv<4> 3 7 FB4_1 TFF RESET F2HzDiv<5> 3 8 FB4_2 TFF RESET F2HzDiv<6> 3 9 FB4_3 TFF RESET Signal Total Total Loc Reg Reg Init Name Pts Inps Use State F2HzDiv<7> 3 10 FB4_4 TFF RESET F2HzDiv<8> 3 11 FB4_5 TFF RESET F2HzDiv<9> 3 12 FB4_6 TFF RESET F2HzDiv<12> 3 15 FB4_7 TFF RESET F2HzDiv<13> 3 16 FB4_8 TFF RESET F2HzDiv<14> 3 17 FB4_9 TFF RESET F2HzDiv<15> 3 18 FB4_10 TFF RESET F2HzDiv_cmp_eq0000 1 19 FB4_11 F2HzDiv<10> 3 13 FB4_12 TFF RESET F2HzDiv<16> 3 19 FB4_13 TFF RESET F2HzDiv<11> 3 14 FB4_14 TFF RESET F2HzDiv<17> 3 20 FB4_15 TFF RESET F2HzDiv<18> 3 21 FB4_16 TFF RESET DispMode 3 6 FB5_1 TFF RESET F2HzDiv<0> 1 1 FB5_2 TFF RESET N_PZ_452 3 4 FB5_3 MachineState_FFd2 3 5 FB5_4 DFF RESET MachineState_FFd1 3 5 FB5_5 DFF RESET Context_FFd2 3 4 FB5_6 DEFF RESET N_PZ_449 2 4 FB5_7 Sec1<0> 3 4 FB5_8 TFF RESET N_PZ_514 3 4 FB5_9 N_PZ_445 4 4 FB5_10 Sec<1> 3 5 FB5_11 TFF RESET Sec<2> 5 9 FB5_12 TFF RESET Sec<5> 4 10 FB5_13 TFF RESET Context_FFd1 3 4 FB5_14 DEFF RESET Sec<4> 4 10 FB5_15 TFF RESET Sec<3> 4 10 FB5_16 TFF RESET SetupKeyStatus 2 4 FB6_1 LATCH RESET N_PZ_515 3 4 FB6_2 FDiv<3> 3 5 FB6_3 TFF RESET N_PZ_446 4 4 FB6_4 FDiv<2> 3 4 FB6_5 TFF RESET FDiv<1> 3 3 FB6_6 TFF RESET FDiv<0> 2 2 FB6_7 TFF RESET F1HzFF 2 2 FB6_8 TFF RESET F2HzDiv<3> 3 6 FB6_9 TFF RESET F2HzDiv<2> 3 5 FB6_10 TFF RESET F2HzDiv<1> 3 4 FB6_11 DFF RESET Signal Total Total Loc Reg Reg Init Name Pts Inps Use State Hrs<1> 3 4 FB6_12 TFF RESET Hrs1<0> 3 3 FB6_13 TFF RESET MuxDisplInstance/SelCnt<1> 3 3 FB6_14 TFF RESET MuxDisplInstance/SelCnt<0> 2 2 FB6_15 TFF RESET FDiv<4> 3 6 FB6_16 TFF RESET SetupKeyInstance/ShRegister<0> 2 2 FB12_15 DFF RESET ** 4 Inputs ** Signal Loc Pin Pin Pin I/O I/O Name No. Type Use STD Style ModeKeyInp FB1_3 143 GSR/I/O I LVCMOS18 KPR Clk FB6_4 38 GCK/I/O GCK LVCMOS18 KPR Reset FB6_12 39 DGE/I/O I LVCMOS18 KPR SetupKeyInp FB12_15 94 I/O I LVCMOS18 KPR Legend: Pin No. - ~ - User Assigned I/O Style - OD - OpenDrain - PU - Pullup - KPR - Keeper - S - SchmittTrigger - DG - DataGate Reg Use - LATCH - Transparent latch - DFF - D-flip-flop - DEFF - D-flip-flop with clock enable - TFF - T-flip-flop - TDFF - Dual-edge-triggered T-flip-flop - DDFF - Dual-edge-triggered flip-flop - DDEFF - Dual-edge-triggered flip-flop with clock enable /S (after any above flop/latch type) indicates initial state is Set ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset VRF - Vref Pin No. - ~ - User Assigned *********************************** FB1 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 18/22 Number of function block control terms used/remaining: 3/1 Number of PLA product terms used/remaining: 20/36 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use ModeKeyInstance/ShRegister<2> 3 FB1_1 (b) (b) + + ModeKeyInstance/ShRegister<1> 3 FB1_2 (b) (b) + + ModeKeyInstance/ShRegister<0> 4 FB1_3 143 GSR/I/O I + + SetupKeyInstance/ShRegister<3> 3 FB1_4 142 I/O (b) + + FClk 2 FB1_5 (b) (b) + SetupKeyInstance/ShRegister<2> 3 FB1_6 140 I/O (b) + + FDivInstance/FDivCnt<6> 2 FB1_7 (b) (b) + FDivInstance/FDivCnt<5> 2 FB1_8 (b) (b) + FDivInstance/FDivCnt<4> 2 FB1_9 (b) (b) + FDivInstance/FDivCnt<3> 2 FB1_10 (b) (b) + FDivInstance/FDivCnt<2> 2 FB1_11 (b) (b) + SetupKeyInstance/ShRegister<1> 3 FB1_12 139 I/O (b) + + ModeKeyStatus 2 FB1_13 138 I/O (b) ModeKeyInstance/ShRegister<3> 3 FB1_14 137 I/O (b) + + FDivInstance/FDivCnt<1> 2 FB1_15 (b) (b) + FDivInstance/FDivCnt<0> 1 FB1_16 (b) (b) + Signals Used by Logic in Function Block 1: Context_FFd1 7: FDivInstance/FDivCnt<3> 13: ModeKeyInstance/ShRegister<2> 2: Context_FFd2 8: FDivInstance/FDivCnt<4> 14: ModeKeyInstance/ShRegister<3> 3: FDiv<4> 9: FDivInstance/FDivCnt<5> 15: Reset 4: FDivInstance/FDivCnt<0> 10: FDivInstance/FDivCnt<6> 16: SetupKeyInstance/ShRegister<0> 5: FDivInstance/FDivCnt<1> 11: ModeKeyInstance/ShRegister<0> 17: SetupKeyInstance/ShRegister<1> 6: FDivInstance/FDivCnt<2> 12: ModeKeyInstance/ShRegister<1> 18: SetupKeyInstance/ShRegister<2> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs ModeKeyInstance/ShRegister<2> ..X........X..X......................... 3 ModeKeyInstance/ShRegister<1> ..X.......X...X......................... 3 ModeKeyInstance/ShRegister<0> XXX...........X......................... 4 SetupKeyInstance/ShRegister<3> ..X...........X..X...................... 3 FClk ...XXXXXXX....X......................... 8 SetupKeyInstance/ShRegister<2> ..X...........X.X....................... 3 FDivInstance/FDivCnt<6> ...XXXXXX.....X......................... 7 FDivInstance/FDivCnt<5> ...XXXXX......X......................... 6 FDivInstance/FDivCnt<4> ...XXXX.......X......................... 5 FDivInstance/FDivCnt<3> ...XXX........X......................... 4 FDivInstance/FDivCnt<2> ...XX.........X......................... 3 SetupKeyInstance/ShRegister<1> ..X...........XX........................ 3 ModeKeyStatus ..........XXXX.......................... 4 ModeKeyInstance/ShRegister<3> ..X.........X.X......................... 3 FDivInstance/FDivCnt<1> ...X..........X......................... 2 FDivInstance/FDivCnt<0> ..............X......................... 1 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB2 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 33/7 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 56/0 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB2_1 2 GTS/I/O (unused) 0 FB2_2 (b) (unused) 0 FB2_3 3 GTS/I/O (unused) 0 FB2_4 4 I/O (unused) 0 FB2_5 5 GTS/I/O (unused) 0 FB2_6 (b) (unused) 0 FB2_7 (b) N_PZ_570 2 FB2_8 (b) (b) N_PZ_496 2 FB2_9 (b) (b) MuxDisplInstance/Tetr<3> 10 FB2_10 (b) (b) MuxDisplInstance/Tetr<1> 15 FB2_11 (b) (b) (unused) 0 FB2_12 6 GTS/I/O (unused) 0 FB2_13 7 I/O (unused) 0 FB2_14 9 I/O (unused) 0 FB2_15 10 I/O MuxDisplInstance/Tetr<2> 27 FB2_16 (b) (b) Signals Used by Logic in Function Block 1: Context_FFd1 12: Hrs<5> 23: N_PZ_498 2: Context_FFd2 13: Min1<0> 24: N_PZ_514 3: DSel0 14: Min<1> 25: N_PZ_515 4: DSel1 15: Min<2> 26: N_PZ_519 5: DSel2 16: Min<3> 27: N_PZ_576 6: DSel3 17: Min<4> 28: Sec1<0> 7: DispMode 18: Min<5> 29: Sec<1> 8: Hrs<1> 19: N_PZ_407 30: Sec<2> 9: Hrs<2> 20: N_PZ_445 31: Sec<3> 10: Hrs<3> 21: N_PZ_446 32: Sec<4> 11: Hrs<4> 22: N_PZ_497 33: Sec<5> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs N_PZ_570 XX.........................XXXXXX....... 8 N_PZ_496 XX..........XX.X.........X.XXXXXX....... 12 MuxDisplInstance/Tetr<3> ..X.X.XXX.XX.XXXXXXXXX.XXXX.XX.XX....... 24 MuxDisplInstance/Tetr<1> ..XXXXXX.XXX.X.XXXXXXXXXXXX.X.XXX....... 26 MuxDisplInstance/Tetr<2> ..XXXXXXXXXX.XXXXXXXXXX..XX.XXXXX....... 27 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB3 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 33/7 Number of function block control terms used/remaining: 2/2 Number of PLA product terms used/remaining: 40/16 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use Hrs<3> 5 FB3_1 136 I/O (b) + Hrs<4> 4 FB3_2 135 I/O (b) + Hrs<5> 3 FB3_3 134 I/O (b) + N_PZ_498 2 FB3_4 (b) (b) Hrs<2> 3 FB3_5 133 I/O (b) + N_PZ_497 2 FB3_6 (b) (b) N_PZ_519 1 FB3_7 (b) (b) Min<1> 3 FB3_8 (b) (b) + + N_PZ_407 3 FB3_9 (b) (b) Min<2> 4 FB3_10 (b) (b) + + Min<5> 4 FB3_11 (b) (b) + + Min<4> 4 FB3_12 (b) (b) + + Min<3> 4 FB3_13 (b) (b) + + Min1<0> 3 FB3_14 132 I/O (b) + + MuxDisplInstance/Tetr<0> 10 FB3_15 (b) (b) N_PZ_576 2 FB3_16 131 I/O (b) Signals Used by Logic in Function Block 1: DSel0 12: Min1<0> 23: N_PZ_496 2: DSel1 13: Min<1> 24: N_PZ_497 3: DSel2 14: Min<2> 25: N_PZ_498 4: DSel3 15: Min<3> 26: N_PZ_514 5: DispMode 16: Min<4> 27: N_PZ_515 6: Hrs1<0> 17: Min<5> 28: N_PZ_519 7: Hrs<1> 18: N_PZ_407 29: N_PZ_570 8: Hrs<2> 19: N_PZ_445 30: N_PZ_576 9: Hrs<3> 20: N_PZ_446 31: Reset 10: Hrs<4> 21: N_PZ_449 32: Sec1<0> 11: Hrs<5> 22: N_PZ_452 33: Sec<1> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs Hrs<3> .....XXXXXX..........XX.......X......... 9 Hrs<4> .....XXXXXX..........XX.......X......... 9 Hrs<5> .....XXXXX...........XX.......X......... 8 N_PZ_498 .X.XX................................... 3 Hrs<2> .....XX..............XX.......X......... 5 N_PZ_497 X.X.X................................... 3 N_PZ_519 .............X.XX....................... 3 Min<1> ...........X........X.......X.X......... 4 N_PZ_407 .............XXXX..........X.X.......... 6 Min<2> ...........XX.X.....X......XX.X......... 7 Min<5> ...........XXXXXX...X.......X.X......... 9 Min<4> ...........XXXXXX...X.......X.X......... 9 Min<3> ...........XXXXXX...X.......X.X......... 9 Min1<0> ....................X.......X.X......... 3 MuxDisplInstance/Tetr<0> XXXXXXX....XX.X.XXXX...XXXX..X.XX....... 21 N_PZ_576 .............X.XX....................... 3 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB4 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 21/19 Number of function block control terms used/remaining: 1/3 Number of PLA product terms used/remaining: 32/24 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use F2HzDiv<4> 3 FB4_1 11 I/O (b) + F2HzDiv<5> 3 FB4_2 12 I/O (b) + F2HzDiv<6> 3 FB4_3 13 I/O (b) + F2HzDiv<7> 3 FB4_4 14 I/O (b) + F2HzDiv<8> 3 FB4_5 15 I/O (b) + F2HzDiv<9> 3 FB4_6 16 I/O (b) + F2HzDiv<12> 3 FB4_7 (b) (b) + F2HzDiv<13> 3 FB4_8 (b) (b) + F2HzDiv<14> 3 FB4_9 (b) (b) + F2HzDiv<15> 3 FB4_10 (b) (b) + F2HzDiv_cmp_eq0000 1 FB4_11 (b) (b) F2HzDiv<10> 3 FB4_12 17 I/O (b) + F2HzDiv<16> 3 FB4_13 (b) (b) + F2HzDiv<11> 3 FB4_14 18 I/O (b) + F2HzDiv<17> 3 FB4_15 (b) (b) + F2HzDiv<18> 3 FB4_16 (b) (b) + Signals Used by Logic in Function Block 1: F2HzDiv<0> 8: F2HzDiv<16> 15: F2HzDiv<5> 2: F2HzDiv<10> 9: F2HzDiv<17> 16: F2HzDiv<6> 3: F2HzDiv<11> 10: F2HzDiv<18> 17: F2HzDiv<7> 4: F2HzDiv<12> 11: F2HzDiv<1> 18: F2HzDiv<8> 5: F2HzDiv<13> 12: F2HzDiv<2> 19: F2HzDiv<9> 6: F2HzDiv<14> 13: F2HzDiv<3> 20: F2HzDiv_cmp_eq0000 7: F2HzDiv<15> 14: F2HzDiv<4> 21: ModeKeyInstance/ShRegister<0>.COMB Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs F2HzDiv<4> X.........XXXX.....XX................... 7 F2HzDiv<5> X.........XXXXX....XX................... 8 F2HzDiv<6> X.........XXXXXX...XX................... 9 F2HzDiv<7> X.........XXXXXXX..XX................... 10 F2HzDiv<8> X.........XXXXXXXX.XX................... 11 F2HzDiv<9> X.........XXXXXXXXXXX................... 12 F2HzDiv<12> XXXX......XXXXXXXXXXX................... 15 F2HzDiv<13> XXXXX.....XXXXXXXXXXX................... 16 F2HzDiv<14> XXXXXX....XXXXXXXXXXX................... 17 F2HzDiv<15> XXXXXXX...XXXXXXXXXXX................... 18 F2HzDiv_cmp_eq0000 XXXXXXXXXXXXXXXXXXX..................... 19 F2HzDiv<10> XX........XXXXXXXXXXX................... 13 F2HzDiv<16> XXXXXXXX..XXXXXXXXXXX................... 19 F2HzDiv<11> XXX.......XXXXXXXXXXX................... 14 F2HzDiv<17> XXXXXXXXX.XXXXXXXXXXX................... 20 F2HzDiv<18> XXXXXXXXXXXXXXXXXXXXX................... 21 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB5 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 18/22 Number of function block control terms used/remaining: 2/2 Number of PLA product terms used/remaining: 36/20 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use DispMode 3 FB5_1 (b) (b) F2HzDiv<0> 1 FB5_2 33 I/O (b) + N_PZ_452 3 FB5_3 (b) (b) MachineState_FFd2 3 FB5_4 32 GCK/I/O (b) MachineState_FFd1 3 FB5_5 31 I/O (b) Context_FFd2 3 FB5_6 30 GCK/I/O (b) N_PZ_449 2 FB5_7 (b) (b) Sec1<0> 3 FB5_8 (b) (b) + + N_PZ_514 3 FB5_9 (b) (b) N_PZ_445 4 FB5_10 (b) (b) Sec<1> 3 FB5_11 (b) (b) + + Sec<2> 5 FB5_12 (b) (b) + + Sec<5> 4 FB5_13 (b) (b) + + Context_FFd1 3 FB5_14 28 I/O (b) Sec<4> 4 FB5_15 (b) (b) + + Sec<3> 4 FB5_16 (b) (b) + + Signals Used by Logic in Function Block 1: Context_FFd1 7: ModeKeyInstance/ShRegister<0>.COMB 13: Sec<1> 2: Context_FFd2 8: ModeKeyStatus 14: Sec<2> 3: DispMode 9: N_PZ_445 15: Sec<3> 4: F1HzFF 10: N_PZ_449 16: Sec<4> 5: MachineState_FFd1 11: Reset 17: Sec<5> 6: MachineState_FFd2 12: Sec1<0> 18: SetupKeyStatus Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs DispMode XXX.XX....X............................. 6 F2HzDiv<0> ......X................................. 1 N_PZ_452 XX.....X.X.............................. 4 MachineState_FFd2 ....XX.X..X......X...................... 5 MachineState_FFd1 ....XX.X..X......X...................... 5 Context_FFd2 X...XX....X............................. 4 N_PZ_449 XX.X...X................................ 4 Sec1<0> XX.X..X................................. 4 N_PZ_514 .............XXXX....................... 4 N_PZ_445 .............XXXX....................... 4 Sec<1> XX.X..X....X............................ 5 Sec<2> XX.X..X.X..XX.X.X....................... 9 Sec<5> XX.X..X....XXXXXX....................... 10 Context_FFd1 .X..XX....X............................. 4 Sec<4> XX.X..X....XXXXXX....................... 10 Sec<3> XX.X..X....XXXXXX....................... 10 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB6 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 25/15 Number of function block control terms used/remaining: 2/2 Number of PLA product terms used/remaining: 32/24 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use SetupKeyStatus 2 FB6_1 34 I/O (b) N_PZ_515 3 FB6_2 35 CDR/I/O (b) FDiv<3> 3 FB6_3 (b) (b) + + N_PZ_446 4 FB6_4 38 GCK/I/O GCK FDiv<2> 3 FB6_5 (b) (b) + + FDiv<1> 3 FB6_6 (b) (b) + + FDiv<0> 2 FB6_7 (b) (b) + + F1HzFF 2 FB6_8 (b) (b) F2HzDiv<3> 3 FB6_9 (b) (b) F2HzDiv<2> 3 FB6_10 (b) (b) F2HzDiv<1> 3 FB6_11 (b) (b) Hrs<1> 3 FB6_12 39 DGE/I/O I + Hrs1<0> 3 FB6_13 40 I/O (b) + MuxDisplInstance/SelCnt<1> 3 FB6_14 41 I/O (b) + MuxDisplInstance/SelCnt<0> 2 FB6_15 42 I/O (b) + FDiv<4> 3 FB6_16 43 I/O (b) + + Signals Used by Logic in Function Block 1: F2HzDiv<0> 10: FDiv<2> 18: MuxDisplInstance/SelCnt<0> 2: F2HzDiv<18> 11: FDiv<3> 19: N_PZ_452 3: F2HzDiv<1> 12: Hrs1<0> 20: N_PZ_496 4: F2HzDiv<2> 13: Hrs<2> 21: Reset 5: F2HzDiv<3> 14: Hrs<3> 22: SetupKeyInstance/ShRegister<0> 6: F2HzDiv_cmp_eq0000 15: Hrs<4> 23: SetupKeyInstance/ShRegister<1> 7: FClk 16: Hrs<5> 24: SetupKeyInstance/ShRegister<2> 8: FDiv<0> 17: ModeKeyInstance/ShRegister<0>.COMB 25: SetupKeyInstance/ShRegister<3> 9: FDiv<1> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs SetupKeyStatus .....................XXXX............... 4 N_PZ_515 ............XXXX........................ 4 FDiv<3> ......XXXX..........X................... 5 N_PZ_446 ............XXXX........................ 4 FDiv<2> ......XXX...........X................... 4 FDiv<1> ......XX............X................... 3 FDiv<0> ......X.............X................... 2 F1HzFF .X..............X....................... 2 F2HzDiv<3> X.XXXX..........X....................... 6 F2HzDiv<2> X.XX.X..........X....................... 5 F2HzDiv<1> X.X..X..........X....................... 4 Hrs<1> ...........X......XXX................... 4 Hrs1<0> ..................XXX................... 3 MuxDisplInstance/SelCnt<1> ..........X......X..X................... 3 MuxDisplInstance/SelCnt<0> ..........X.........X................... 2 FDiv<4> ......XXXXX.........X................... 6 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB7 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB7_1 (b) (unused) 0 FB7_2 (b) (unused) 0 FB7_3 (b) (unused) 0 FB7_4 (b) (unused) 0 FB7_5 26 I/O (unused) 0 FB7_6 25 I/O (unused) 0 FB7_7 (b) (unused) 0 FB7_8 (b) (unused) 0 FB7_9 (b) (unused) 0 FB7_10 (b) (unused) 0 FB7_11 24 I/O (unused) 0 FB7_12 23 I/O (unused) 0 FB7_13 22 I/O (unused) 0 FB7_14 21 I/O (unused) 0 FB7_15 20 I/O (unused) 0 FB7_16 19 I/O *********************************** FB8 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB8_1 44 I/O (unused) 0 FB8_2 45 I/O (unused) 0 FB8_3 46 I/O (unused) 0 FB8_4 (b) (unused) 0 FB8_5 48 I/O (unused) 0 FB8_6 49 I/O (unused) 0 FB8_7 (b) (unused) 0 FB8_8 (b) (unused) 0 FB8_9 (b) (unused) 0 FB8_10 (b) (unused) 0 FB8_11 50 I/O (unused) 0 FB8_12 51 I/O (unused) 0 FB8_13 52 I/O (unused) 0 FB8_14 (b) (unused) 0 FB8_15 (b) (unused) 0 FB8_16 (b) *********************************** FB9 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB9_1 112 I/O (unused) 0 FB9_2 113 I/O (unused) 0 FB9_3 (b) (unused) 0 FB9_4 114 I/O (unused) 0 FB9_5 (b) (unused) 0 FB9_6 115 I/O (unused) 0 FB9_7 (b) (unused) 0 FB9_8 (b) (unused) 0 FB9_9 (b) (unused) 0 FB9_10 (b) (unused) 0 FB9_11 (b) (unused) 0 FB9_12 116 I/O (unused) 0 FB9_13 117 I/O (unused) 0 FB9_14 118 I/O (unused) 0 FB9_15 119 I/O (unused) 0 FB9_16 (b) *********************************** FB10 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB10_1 111 I/O (unused) 0 FB10_2 110 I/O (unused) 0 FB10_3 107 I/O (unused) 0 FB10_4 106 I/O (unused) 0 FB10_5 105 I/O (unused) 0 FB10_6 104 I/O (unused) 0 FB10_7 (b) (unused) 0 FB10_8 (b) (unused) 0 FB10_9 (b) (unused) 0 FB10_10 (b) (unused) 0 FB10_11 (b) (unused) 0 FB10_12 103 I/O (unused) 0 FB10_13 (b) (unused) 0 FB10_14 102 I/O (unused) 0 FB10_15 (b) (unused) 0 FB10_16 101 I/O *********************************** FB11 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 2/38 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 4/52 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB11_1 (b) (unused) 0 FB11_2 (b) (unused) 0 FB11_3 (b) (unused) 0 FB11_4 (b) (unused) 0 FB11_5 120 I/O (unused) 0 FB11_6 121 I/O (unused) 0 FB11_7 (b) (unused) 0 FB11_8 (b) (unused) 0 FB11_9 (b) (unused) 0 FB11_10 (b) (unused) 0 FB11_11 124 I/O (unused) 0 FB11_12 125 I/O DSel0 1 FB11_13 126 I/O O DSel1 1 FB11_14 128 I/O O DSel2 1 FB11_15 129 I/O O DSel3 1 FB11_16 130 I/O O Signals Used by Logic in Function Block 1: MuxDisplInstance/SelCnt<0> 2: MuxDisplInstance/SelCnt<1> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs DSel0 XX...................................... 2 DSel1 XX...................................... 2 DSel2 XX...................................... 2 DSel3 XX...................................... 2 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB12 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 2/38 Number of function block control terms used/remaining: 2/2 Number of PLA product terms used/remaining: 2/54 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB12_1 (b) (unused) 0 FB12_2 100 I/O (unused) 0 FB12_3 (b) (unused) 0 FB12_4 (b) (unused) 0 FB12_5 (b) (unused) 0 FB12_6 (b) (unused) 0 FB12_7 (b) (unused) 0 FB12_8 (b) (unused) 0 FB12_9 (b) (unused) 0 FB12_10 (b) (unused) 0 FB12_11 98 I/O (unused) 0 FB12_12 97 I/O (unused) 0 FB12_13 96 I/O (unused) 0 FB12_14 95 I/O SetupKeyInstance/ShRegister<0> 2 FB12_15 94 I/O I + + (unused) 0 FB12_16 (b) Signals Used by Logic in Function Block 1: FDiv<4> 2: Reset Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB13 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB13_1 75 I/O (unused) 0 FB13_2 76 I/O (unused) 0 FB13_3 77 I/O (unused) 0 FB13_4 (b) (unused) 0 FB13_5 78 I/O (unused) 0 FB13_6 79 I/O (unused) 0 FB13_7 (b) (unused) 0 FB13_8 (b) (unused) 0 FB13_9 (b) (unused) 0 FB13_10 (b) (unused) 0 FB13_11 (b) (unused) 0 FB13_12 80 I/O (unused) 0 FB13_13 81 I/O (unused) 0 FB13_14 82 I/O (unused) 0 FB13_15 (b) (unused) 0 FB13_16 (b) *********************************** FB14 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 4/36 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 3/53 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB14_1 74 I/O (unused) 0 FB14_2 71 I/O (unused) 0 FB14_3 70 I/O (unused) 0 FB14_4 69 I/O (unused) 0 FB14_5 (b) (unused) 0 FB14_6 68 I/O (unused) 0 FB14_7 (b) (unused) 0 FB14_8 (b) (unused) 0 FB14_9 (b) (unused) 0 FB14_10 (b) (unused) 0 FB14_11 (b) (unused) 0 FB14_12 (b) (unused) 0 FB14_13 66 I/O (unused) 0 FB14_14 64 I/O (unused) 0 FB14_15 (b) Seg_G 3 FB14_16 61 I/O O Signals Used by Logic in Function Block 1: MuxDisplInstance/Tetr<0> 3: MuxDisplInstance/Tetr<2> 4: MuxDisplInstance/Tetr<3> 2: MuxDisplInstance/Tetr<1> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs Seg_G XXXX.................................... 4 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB15 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB15_1 (b) (unused) 0 FB15_2 83 I/O (unused) 0 FB15_3 (b) (unused) 0 FB15_4 (b) (unused) 0 FB15_5 (b) (unused) 0 FB15_6 (b) (unused) 0 FB15_7 (b) (unused) 0 FB15_8 (b) (unused) 0 FB15_9 (b) (unused) 0 FB15_10 (b) (unused) 0 FB15_11 85 I/O (unused) 0 FB15_12 86 I/O (unused) 0 FB15_13 87 I/O (unused) 0 FB15_14 88 I/O (unused) 0 FB15_15 91 I/O (unused) 0 FB15_16 92 I/O *********************************** FB16 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 11/29 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 19/37 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB16_1 (b) (unused) 0 FB16_2 (b) (unused) 0 FB16_3 (b) (unused) 0 FB16_4 (b) Seg_C 3 FB16_5 60 I/O O Seg_K 4 FB16_6 59 I/O O (unused) 0 FB16_7 (b) (unused) 0 FB16_8 (b) (unused) 0 FB16_9 (b) (unused) 0 FB16_10 (b) Seg_D 4 FB16_11 58 I/O O Seg_E 3 FB16_12 57 I/O O Seg_A 3 FB16_13 56 I/O O (unused) 0 FB16_14 (b) Seg_F 3 FB16_15 54 I/O O Seg_B 3 FB16_16 53 I/O O Signals Used by Logic in Function Block 1: Context_FFd1 5: DSel2 9: MuxDisplInstance/Tetr<1> 2: Context_FFd2 6: DSel3 10: MuxDisplInstance/Tetr<2> 3: DSel0 7: F1HzFF 11: MuxDisplInstance/Tetr<3> 4: DSel1 8: MuxDisplInstance/Tetr<0> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs Seg_C .......XXXX............................. 4 Seg_K XXXXXXX................................. 7 Seg_D .......XXXX............................. 4 Seg_E .......XXXX............................. 4 Seg_A .......XXXX............................. 4 Seg_F .......XXXX............................. 4 Seg_B .......XXXX............................. 4 0----+----1----+----2----+----3----+----4 0 0 0 0 ******************************* Equations ******************************** ********** Mapped Logic ********** FDCPE_Context_FFd1: FDCPE port map (Context_FFd1,Context_FFd2,NOT Clk,NOT Reset,'0',Context_FFd1_CE); Context_FFd1_CE <= (MachineState_FFd2 AND MachineState_FFd1); FDCPE_Context_FFd2: FDCPE port map (Context_FFd2,NOT Context_FFd1,NOT Clk,NOT Reset,'0',Context_FFd2_CE); Context_FFd2_CE <= (MachineState_FFd2 AND MachineState_FFd1); DSel0 <= NOT ((NOT MuxDisplInstance/SelCnt(0) AND NOT MuxDisplInstance/SelCnt(1))); DSel1 <= NOT ((MuxDisplInstance/SelCnt(0) AND NOT MuxDisplInstance/SelCnt(1))); DSel2 <= NOT ((NOT MuxDisplInstance/SelCnt(0) AND MuxDisplInstance/SelCnt(1))); DSel3 <= NOT ((MuxDisplInstance/SelCnt(0) AND MuxDisplInstance/SelCnt(1))); FTCPE_DispMode: FTCPE port map (DispMode,DispMode_T,NOT Clk,NOT Reset,'0','1'); DispMode_T <= ((NOT Context_FFd2 AND NOT Context_FFd1 AND MachineState_FFd2 AND NOT MachineState_FFd1) OR (NOT Context_FFd2 AND NOT Context_FFd1 AND MachineState_FFd2 AND NOT DispMode)); FTCPE_F1HzFF: FTCPE port map (F1HzFF,'0',F2HzDiv(18),NOT ModeKeyInstance/ShRegister(0).COMB,'0','1'); FTCPE_F2HzDiv0: FTCPE port map (F2HzDiv(0),'0',NOT Clk,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1'); FDCPE_F2HzDiv1: FDCPE port map (F2HzDiv(1),F2HzDiv_D(1),NOT Clk,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1'); F2HzDiv_D(1) <= ((NOT F2HzDiv_cmp_eq0000 AND F2HzDiv(0) AND NOT F2HzDiv(1)) OR (NOT F2HzDiv_cmp_eq0000 AND NOT F2HzDiv(0) AND F2HzDiv(1))); FTCPE_F2HzDiv2: FTCPE port map (F2HzDiv(2),F2HzDiv_T(2),NOT Clk,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1'); F2HzDiv_T(2) <= ((F2HzDiv_cmp_eq0000 AND F2HzDiv(2)) OR (NOT F2HzDiv_cmp_eq0000 AND F2HzDiv(0) AND F2HzDiv(1))); FTCPE_F2HzDiv3: FTCPE port map (F2HzDiv(3),F2HzDiv_T(3),NOT Clk,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1'); F2HzDiv_T(3) <= ((F2HzDiv_cmp_eq0000 AND F2HzDiv(3)) OR (NOT F2HzDiv_cmp_eq0000 AND F2HzDiv(0) AND F2HzDiv(1) AND F2HzDiv(2))); FTCPE_F2HzDiv4: FTCPE port map (F2HzDiv(4),F2HzDiv_T(4),NOT Clk,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1'); F2HzDiv_T(4) <= ((F2HzDiv_cmp_eq0000 AND F2HzDiv(4)) OR (NOT F2HzDiv_cmp_eq0000 AND F2HzDiv(0) AND F2HzDiv(1) AND F2HzDiv(2) AND F2HzDiv(3))); FTCPE_F2HzDiv5: FTCPE port map (F2HzDiv(5),F2HzDiv_T(5),NOT Clk,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1'); F2HzDiv_T(5) <= ((F2HzDiv_cmp_eq0000 AND F2HzDiv(5)) OR (NOT F2HzDiv_cmp_eq0000 AND F2HzDiv(0) AND F2HzDiv(1) AND F2HzDiv(2) AND F2HzDiv(3) AND F2HzDiv(4))); FTCPE_F2HzDiv6: FTCPE port map (F2HzDiv(6),F2HzDiv_T(6),NOT Clk,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1'); F2HzDiv_T(6) <= ((F2HzDiv_cmp_eq0000 AND F2HzDiv(6)) OR (NOT F2HzDiv_cmp_eq0000 AND F2HzDiv(0) AND F2HzDiv(1) AND F2HzDiv(2) AND F2HzDiv(3) AND F2HzDiv(4) AND F2HzDiv(5))); FTCPE_F2HzDiv7: FTCPE port map (F2HzDiv(7),F2HzDiv_T(7),NOT Clk,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1'); F2HzDiv_T(7) <= ((F2HzDiv_cmp_eq0000 AND F2HzDiv(7)) OR (NOT F2HzDiv_cmp_eq0000 AND F2HzDiv(0) AND F2HzDiv(1) AND F2HzDiv(2) AND F2HzDiv(3) AND F2HzDiv(4) AND F2HzDiv(5) AND F2HzDiv(6))); FTCPE_F2HzDiv8: FTCPE port map (F2HzDiv(8),F2HzDiv_T(8),NOT Clk,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1'); F2HzDiv_T(8) <= ((F2HzDiv_cmp_eq0000 AND F2HzDiv(8)) OR (NOT F2HzDiv_cmp_eq0000 AND F2HzDiv(0) AND F2HzDiv(1) AND F2HzDiv(2) AND F2HzDiv(3) AND F2HzDiv(4) AND F2HzDiv(5) AND F2HzDiv(6) AND F2HzDiv(7))); FTCPE_F2HzDiv9: FTCPE port map (F2HzDiv(9),F2HzDiv_T(9),NOT Clk,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1'); F2HzDiv_T(9) <= ((F2HzDiv_cmp_eq0000 AND F2HzDiv(9)) OR (NOT F2HzDiv_cmp_eq0000 AND F2HzDiv(0) AND F2HzDiv(1) AND F2HzDiv(2) AND F2HzDiv(3) AND F2HzDiv(4) AND F2HzDiv(5) AND F2HzDiv(6) AND F2HzDiv(7) AND F2HzDiv(8))); FTCPE_F2HzDiv10: FTCPE port map (F2HzDiv(10),F2HzDiv_T(10),NOT Clk,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1'); F2HzDiv_T(10) <= ((F2HzDiv_cmp_eq0000 AND F2HzDiv(10)) OR (NOT F2HzDiv_cmp_eq0000 AND F2HzDiv(0) AND F2HzDiv(1) AND F2HzDiv(2) AND F2HzDiv(3) AND F2HzDiv(4) AND F2HzDiv(5) AND F2HzDiv(6) AND F2HzDiv(7) AND F2HzDiv(8) AND F2HzDiv(9))); FTCPE_F2HzDiv11: FTCPE port map (F2HzDiv(11),F2HzDiv_T(11),NOT Clk,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1'); F2HzDiv_T(11) <= ((F2HzDiv_cmp_eq0000 AND F2HzDiv(11)) OR (NOT F2HzDiv_cmp_eq0000 AND F2HzDiv(0) AND F2HzDiv(10) AND F2HzDiv(1) AND F2HzDiv(2) AND F2HzDiv(3) AND F2HzDiv(4) AND F2HzDiv(5) AND F2HzDiv(6) AND F2HzDiv(7) AND F2HzDiv(8) AND F2HzDiv(9))); FTCPE_F2HzDiv12: FTCPE port map (F2HzDiv(12),F2HzDiv_T(12),NOT Clk,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1'); F2HzDiv_T(12) <= ((F2HzDiv_cmp_eq0000 AND F2HzDiv(12)) OR (NOT F2HzDiv_cmp_eq0000 AND F2HzDiv(0) AND F2HzDiv(10) AND F2HzDiv(1) AND F2HzDiv(2) AND F2HzDiv(3) AND F2HzDiv(4) AND F2HzDiv(5) AND F2HzDiv(6) AND F2HzDiv(7) AND F2HzDiv(8) AND F2HzDiv(9) AND F2HzDiv(11))); FTCPE_F2HzDiv13: FTCPE port map (F2HzDiv(13),F2HzDiv_T(13),NOT Clk,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1'); F2HzDiv_T(13) <= ((F2HzDiv_cmp_eq0000 AND F2HzDiv(13)) OR (NOT F2HzDiv_cmp_eq0000 AND F2HzDiv(0) AND F2HzDiv(10) AND F2HzDiv(1) AND F2HzDiv(2) AND F2HzDiv(3) AND F2HzDiv(4) AND F2HzDiv(5) AND F2HzDiv(6) AND F2HzDiv(7) AND F2HzDiv(8) AND F2HzDiv(9) AND F2HzDiv(11) AND F2HzDiv(12))); FTCPE_F2HzDiv14: FTCPE port map (F2HzDiv(14),F2HzDiv_T(14),NOT Clk,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1'); F2HzDiv_T(14) <= ((F2HzDiv_cmp_eq0000 AND F2HzDiv(14)) OR (NOT F2HzDiv_cmp_eq0000 AND F2HzDiv(0) AND F2HzDiv(10) AND F2HzDiv(1) AND F2HzDiv(2) AND F2HzDiv(3) AND F2HzDiv(4) AND F2HzDiv(5) AND F2HzDiv(6) AND F2HzDiv(7) AND F2HzDiv(8) AND F2HzDiv(9) AND F2HzDiv(11) AND F2HzDiv(12) AND F2HzDiv(13))); FTCPE_F2HzDiv15: FTCPE port map (F2HzDiv(15),F2HzDiv_T(15),NOT Clk,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1'); F2HzDiv_T(15) <= ((F2HzDiv_cmp_eq0000 AND F2HzDiv(15)) OR (NOT F2HzDiv_cmp_eq0000 AND F2HzDiv(0) AND F2HzDiv(10) AND F2HzDiv(1) AND F2HzDiv(2) AND F2HzDiv(3) AND F2HzDiv(4) AND F2HzDiv(5) AND F2HzDiv(6) AND F2HzDiv(7) AND F2HzDiv(8) AND F2HzDiv(9) AND F2HzDiv(11) AND F2HzDiv(12) AND F2HzDiv(13) AND F2HzDiv(14))); FTCPE_F2HzDiv16: FTCPE port map (F2HzDiv(16),F2HzDiv_T(16),NOT Clk,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1'); F2HzDiv_T(16) <= ((F2HzDiv_cmp_eq0000 AND F2HzDiv(16)) OR (NOT F2HzDiv_cmp_eq0000 AND F2HzDiv(0) AND F2HzDiv(10) AND F2HzDiv(1) AND F2HzDiv(2) AND F2HzDiv(3) AND F2HzDiv(4) AND F2HzDiv(5) AND F2HzDiv(6) AND F2HzDiv(7) AND F2HzDiv(8) AND F2HzDiv(9) AND F2HzDiv(11) AND F2HzDiv(12) AND F2HzDiv(13) AND F2HzDiv(14) AND F2HzDiv(15))); FTCPE_F2HzDiv17: FTCPE port map (F2HzDiv(17),F2HzDiv_T(17),NOT Clk,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1'); F2HzDiv_T(17) <= ((F2HzDiv_cmp_eq0000 AND F2HzDiv(17)) OR (NOT F2HzDiv_cmp_eq0000 AND F2HzDiv(0) AND F2HzDiv(10) AND F2HzDiv(1) AND F2HzDiv(2) AND F2HzDiv(3) AND F2HzDiv(4) AND F2HzDiv(5) AND F2HzDiv(6) AND F2HzDiv(7) AND F2HzDiv(8) AND F2HzDiv(9) AND F2HzDiv(11) AND F2HzDiv(12) AND F2HzDiv(13) AND F2HzDiv(14) AND F2HzDiv(15) AND F2HzDiv(16))); FTCPE_F2HzDiv18: FTCPE port map (F2HzDiv(18),F2HzDiv_T(18),NOT Clk,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1'); F2HzDiv_T(18) <= ((F2HzDiv(18) AND F2HzDiv_cmp_eq0000) OR (NOT F2HzDiv_cmp_eq0000 AND F2HzDiv(0) AND F2HzDiv(10) AND F2HzDiv(1) AND F2HzDiv(2) AND F2HzDiv(3) AND F2HzDiv(4) AND F2HzDiv(5) AND F2HzDiv(6) AND F2HzDiv(7) AND F2HzDiv(8) AND F2HzDiv(9) AND F2HzDiv(11) AND F2HzDiv(12) AND F2HzDiv(13) AND F2HzDiv(14) AND F2HzDiv(15) AND F2HzDiv(16) AND F2HzDiv(17))); F2HzDiv_cmp_eq0000 <= (F2HzDiv(18) AND F2HzDiv(0) AND NOT F2HzDiv(10) AND F2HzDiv(1) AND F2HzDiv(2) AND F2HzDiv(3) AND F2HzDiv(4) AND NOT F2HzDiv(5) AND NOT F2HzDiv(6) AND NOT F2HzDiv(7) AND F2HzDiv(8) AND NOT F2HzDiv(9) AND NOT F2HzDiv(11) AND NOT F2HzDiv(12) AND F2HzDiv(13) AND NOT F2HzDiv(14) AND F2HzDiv(15) AND F2HzDiv(16) AND F2HzDiv(17)); FTCPE_FClk: FTCPE port map (FClk,FClk_T,NOT Clk,NOT Reset,'0','1'); FClk_T <= (FDivInstance/FDivCnt(0) AND FDivInstance/FDivCnt(1) AND FDivInstance/FDivCnt(2) AND FDivInstance/FDivCnt(3) AND FDivInstance/FDivCnt(4) AND FDivInstance/FDivCnt(5) AND FDivInstance/FDivCnt(6)); FTCPE_FDiv0: FTCPE port map (FDiv(0),'0',FClk,NOT Reset,'0','1'); FTCPE_FDiv1: FTCPE port map (FDiv(1),FDiv(0),FClk,NOT Reset,'0','1'); FTCPE_FDiv2: FTCPE port map (FDiv(2),FDiv_T(2),FClk,NOT Reset,'0','1'); FDiv_T(2) <= (FDiv(0) AND FDiv(1)); FTCPE_FDiv3: FTCPE port map (FDiv(3),FDiv_T(3),FClk,NOT Reset,'0','1'); FDiv_T(3) <= (FDiv(0) AND FDiv(1) AND FDiv(2)); FTCPE_FDiv4: FTCPE port map (FDiv(4),FDiv_T(4),FClk,NOT Reset,'0','1'); FDiv_T(4) <= (FDiv(3) AND FDiv(0) AND FDiv(1) AND FDiv(2)); FTCPE_FDivInstance/FDivCnt0: FTCPE port map (FDivInstance/FDivCnt(0),'0',NOT Clk,NOT Reset,'0','1'); FTCPE_FDivInstance/FDivCnt1: FTCPE port map (FDivInstance/FDivCnt(1),FDivInstance/FDivCnt(0),NOT Clk,NOT Reset,'0','1'); FTCPE_FDivInstance/FDivCnt2: FTCPE port map (FDivInstance/FDivCnt(2),FDivInstance/FDivCnt_T(2),NOT Clk,NOT Reset,'0','1'); FDivInstance/FDivCnt_T(2) <= (FDivInstance/FDivCnt(0) AND FDivInstance/FDivCnt(1)); FTCPE_FDivInstance/FDivCnt3: FTCPE port map (FDivInstance/FDivCnt(3),FDivInstance/FDivCnt_T(3),NOT Clk,NOT Reset,'0','1'); FDivInstance/FDivCnt_T(3) <= (FDivInstance/FDivCnt(0) AND FDivInstance/FDivCnt(1) AND FDivInstance/FDivCnt(2)); FTCPE_FDivInstance/FDivCnt4: FTCPE port map (FDivInstance/FDivCnt(4),FDivInstance/FDivCnt_T(4),NOT Clk,NOT Reset,'0','1'); FDivInstance/FDivCnt_T(4) <= (FDivInstance/FDivCnt(0) AND FDivInstance/FDivCnt(1) AND FDivInstance/FDivCnt(2) AND FDivInstance/FDivCnt(3)); FTCPE_FDivInstance/FDivCnt5: FTCPE port map (FDivInstance/FDivCnt(5),FDivInstance/FDivCnt_T(5),NOT Clk,NOT Reset,'0','1'); FDivInstance/FDivCnt_T(5) <= (FDivInstance/FDivCnt(0) AND FDivInstance/FDivCnt(1) AND FDivInstance/FDivCnt(2) AND FDivInstance/FDivCnt(3) AND FDivInstance/FDivCnt(4)); FTCPE_FDivInstance/FDivCnt6: FTCPE port map (FDivInstance/FDivCnt(6),FDivInstance/FDivCnt_T(6),NOT Clk,NOT Reset,'0','1'); FDivInstance/FDivCnt_T(6) <= (FDivInstance/FDivCnt(0) AND FDivInstance/FDivCnt(1) AND FDivInstance/FDivCnt(2) AND FDivInstance/FDivCnt(3) AND FDivInstance/FDivCnt(4) AND FDivInstance/FDivCnt(5)); FTCPE_Hrs10: FTCPE port map (Hrs1(0),N_PZ_496,N_PZ_452,NOT Reset,'0','1'); FTCPE_Hrs1: FTCPE port map (Hrs(1),Hrs_T(1),N_PZ_452,NOT Reset,'0','1'); Hrs_T(1) <= (Hrs1(0) AND N_PZ_496); FTCPE_Hrs2: FTCPE port map (Hrs(2),Hrs_T(2),N_PZ_452,NOT Reset,'0','1'); Hrs_T(2) <= (Hrs(1) AND Hrs1(0) AND N_PZ_496); FTCPE_Hrs3: FTCPE port map (Hrs(3),Hrs_T(3),N_PZ_452,NOT Reset,'0','1'); Hrs_T(3) <= ((Hrs(1) AND Hrs1(0) AND N_PZ_496 AND Hrs(2) AND NOT Hrs(4)) OR (Hrs(1) AND Hrs1(0) AND N_PZ_496 AND Hrs(2) AND Hrs(3)) OR (Hrs(1) AND Hrs1(0) AND N_PZ_496 AND Hrs(2) AND Hrs(5))); FTCPE_Hrs4: FTCPE port map (Hrs(4),Hrs_T(4),N_PZ_452,NOT Reset,'0','1'); Hrs_T(4) <= ((Hrs(1) AND Hrs1(0) AND N_PZ_496 AND Hrs(2) AND Hrs(3)) OR (Hrs(1) AND Hrs1(0) AND N_PZ_496 AND Hrs(2) AND Hrs(4) AND NOT Hrs(5))); FTCPE_Hrs5: FTCPE port map (Hrs(5),Hrs_T(5),N_PZ_452,NOT Reset,'0','1'); Hrs_T(5) <= (Hrs(1) AND Hrs1(0) AND N_PZ_496 AND Hrs(2) AND Hrs(4) AND Hrs(3)); FDCPE_MachineState_FFd1: FDCPE port map (MachineState_FFd1,MachineState_FFd1_D,NOT Clk,NOT Reset,'0','1'); MachineState_FFd1_D <= NOT (((NOT MachineState_FFd2 AND NOT MachineState_FFd1 AND ModeKeyStatus) OR (NOT MachineState_FFd2 AND NOT ModeKeyStatus AND NOT SetupKeyStatus))); FDCPE_MachineState_FFd2: FDCPE port map (MachineState_FFd2,MachineState_FFd2_D,NOT Clk,NOT Reset,'0','1'); MachineState_FFd2_D <= ((NOT MachineState_FFd2 AND NOT MachineState_FFd1 AND ModeKeyStatus) OR (NOT MachineState_FFd2 AND NOT MachineState_FFd1 AND SetupKeyStatus)); FTCPE_Min10: FTCPE port map (Min1(0),N_PZ_570,N_PZ_449,NOT Reset,'0','1'); FTCPE_Min1: FTCPE port map (Min(1),Min_T(1),N_PZ_449,NOT Reset,'0','1'); Min_T(1) <= (Min1(0) AND N_PZ_570); FTCPE_Min2: FTCPE port map (Min(2),Min_T(2),N_PZ_449,NOT Reset,'0','1'); Min_T(2) <= ((Min(1) AND Min1(0) AND N_PZ_570 AND NOT Min(3)) OR (Min(1) AND Min1(0) AND N_PZ_570 AND NOT N_PZ_519)); FTCPE_Min3: FTCPE port map (Min(3),Min_T(3),N_PZ_449,NOT Reset,'0','1'); Min_T(3) <= ((Min(1) AND Min1(0) AND N_PZ_570 AND Min(2)) OR (Min(1) AND Min1(0) AND N_PZ_570 AND Min(3) AND Min(4) AND Min(5))); FTCPE_Min4: FTCPE port map (Min(4),Min_T(4),N_PZ_449,NOT Reset,'0','1'); Min_T(4) <= ((Min(1) AND Min1(0) AND N_PZ_570 AND Min(3) AND Min(2)) OR (Min(1) AND Min1(0) AND N_PZ_570 AND Min(3) AND Min(4) AND Min(5))); FTCPE_Min5: FTCPE port map (Min(5),Min_T(5),N_PZ_449,NOT Reset,'0','1'); Min_T(5) <= ((Min(1) AND Min1(0) AND N_PZ_570 AND Min(3) AND Min(2) AND Min(4)) OR (Min(1) AND Min1(0) AND N_PZ_570 AND Min(3) AND Min(4) AND Min(5))); ModeKeyInstance/ShRegister(0).COMB <= ((Reset AND Context_FFd2) OR (Reset AND NOT Context_FFd1));FDCPE_ModeKeyInstance/ShRegister0: FDCPE port map (ModeKeyInstance/ShRegister(0),ModeKeyInp,FDiv(4),'0',NOT Reset,'1'); FDCPE_ModeKeyInstance/ShRegister1: FDCPE port map (ModeKeyInstance/ShRegister(1),ModeKeyInstance/ShRegister(0),FDiv(4),'0',NOT Reset,'1'); FDCPE_ModeKeyInstance/ShRegister2: FDCPE port map (ModeKeyInstance/ShRegister(2),ModeKeyInstance/ShRegister(1),FDiv(4),'0',NOT Reset,'1'); FDCPE_ModeKeyInstance/ShRegister3: FDCPE port map (ModeKeyInstance/ShRegister(3),ModeKeyInstance/ShRegister(2),FDiv(4),'0',NOT Reset,'1'); LDCP_ModeKeyStatus: LDCP port map (ModeKeyStatus,NOT '0',,ModeKeyStatus_CLR,'0'); ModeKeyStatus_G <= (NOT ModeKeyInstance/ShRegister(0) AND NOT ModeKeyInstance/ShRegister(1) AND NOT ModeKeyInstance/ShRegister(2) AND NOT ModeKeyInstance/ShRegister(3)); ModeKeyStatus_CLR <= (ModeKeyInstance/ShRegister(0) AND ModeKeyInstance/ShRegister(1) AND ModeKeyInstance/ShRegister(2) AND ModeKeyInstance/ShRegister(3)); FTCPE_MuxDisplInstance/SelCnt0: FTCPE port map (MuxDisplInstance/SelCnt(0),'0',FDiv(3),NOT Reset,'0','1'); FTCPE_MuxDisplInstance/SelCnt1: FTCPE port map (MuxDisplInstance/SelCnt(1),MuxDisplInstance/SelCnt(0),FDiv(3),NOT Reset,'0','1'); MuxDisplInstance/Tetr(0) <= ((Min1(0) AND N_PZ_497) OR (N_PZ_407 AND N_PZ_498) OR (Hrs1(0) AND DispMode AND NOT DSel2) OR (Sec1(0) AND NOT DispMode AND NOT DSel0) OR (N_PZ_445 AND NOT DispMode AND NOT DSel1) OR (DispMode AND N_PZ_446 AND NOT DSel3) OR (Hrs(1) AND DispMode AND NOT DSel3 AND N_PZ_515) OR (Min(1) AND Min(3) AND N_PZ_576 AND N_PZ_498) OR (Min(1) AND NOT Min(3) AND Min(5) AND N_PZ_498) OR (Sec(1) AND NOT DispMode AND NOT DSel1 AND N_PZ_514)); MuxDisplInstance/Tetr(1) <= ((NOT Min(1) AND N_PZ_407 AND N_PZ_497) OR (NOT Hrs(1) AND DispMode AND N_PZ_446 AND NOT DSel2) OR (Min(1) AND NOT Min(3) AND N_PZ_576 AND N_PZ_497) OR (NOT Sec(1) AND N_PZ_445 AND NOT DispMode AND NOT DSel0) OR (NOT N_PZ_519 AND Min(4) AND NOT N_PZ_407 AND N_PZ_498) OR (NOT Min(4) AND Min(5) AND N_PZ_407 AND N_PZ_498) OR (Hrs(1) AND DispMode AND NOT N_PZ_446 AND NOT DSel2 AND NOT N_PZ_515) OR (Min(1) AND Min(3) AND NOT N_PZ_519 AND NOT N_PZ_576 AND N_PZ_497) OR (Sec(1) AND NOT N_PZ_445 AND NOT DispMode AND NOT DSel0 AND NOT N_PZ_514) OR (Sec(3) AND Sec(4) AND NOT N_PZ_445 AND NOT DispMode AND NOT DSel1) OR (NOT Sec(4) AND Sec(5) AND N_PZ_445 AND NOT DispMode AND NOT DSel1) OR (DispMode AND N_PZ_446 AND NOT Hrs(4) AND Hrs(5) AND NOT DSel3) OR (DispMode AND NOT N_PZ_446 AND Hrs(4) AND Hrs(3) AND NOT DSel3) OR (NOT Sec(3) AND Sec(4) AND NOT Sec(5) AND NOT N_PZ_445 AND NOT DispMode AND NOT DSel1) OR (DispMode AND NOT N_PZ_446 AND Hrs(4) AND NOT Hrs(3) AND NOT Hrs(5) AND NOT DSel3)); MuxDisplInstance/Tetr(2) <= ((Min(3) AND Min(5) AND N_PZ_498) OR (Min(4) AND Min(5) AND N_PZ_498) OR (Sec(4) AND Sec(5) AND NOT DispMode AND NOT DSel1) OR (Sec(5) AND NOT N_PZ_445 AND NOT DispMode AND NOT DSel1) OR (Min(2) AND NOT Min(4) AND NOT N_PZ_407 AND N_PZ_497) OR (DispMode AND NOT N_PZ_446 AND Hrs(5) AND NOT DSel3) OR (DispMode AND Hrs(4) AND Hrs(5) AND NOT DSel3) OR (Min(1) AND Min(3) AND Min(2) AND NOT Min(4) AND N_PZ_497) OR (Min(1) AND Min(2) AND Min(4) AND N_PZ_407 AND N_PZ_497) OR (Min(1) AND NOT Min(2) AND NOT Min(4) AND N_PZ_407 AND N_PZ_497) OR (NOT Min(1) AND NOT Min(2) AND Min(4) AND N_PZ_407 AND N_PZ_497) OR (Sec(2) AND NOT Sec(4) AND NOT N_PZ_445 AND NOT DispMode AND NOT DSel0) OR (DispMode AND NOT N_PZ_446 AND Hrs(2) AND NOT Hrs(4) AND NOT DSel2) OR (Hrs(1) AND DispMode AND N_PZ_446 AND Hrs(2) AND Hrs(4) AND NOT DSel2) OR (Hrs(1) AND DispMode AND N_PZ_446 AND NOT Hrs(2) AND NOT Hrs(4) AND NOT DSel2) OR (Hrs(1) AND DispMode AND Hrs(2) AND NOT Hrs(4) AND Hrs(3) AND NOT DSel2) OR (NOT Hrs(1) AND DispMode AND N_PZ_446 AND NOT Hrs(2) AND Hrs(4) AND NOT DSel2) OR (NOT Hrs(1) AND DispMode AND Hrs(2) AND NOT Hrs(4) AND Hrs(5) AND NOT DSel2) OR (NOT Min(1) AND Min(2) AND NOT Min(4) AND Min(5) AND N_PZ_407 AND N_PZ_497) OR (Sec(1) AND Sec(2) AND Sec(3) AND NOT Sec(4) AND NOT DispMode AND NOT DSel0) OR (Sec(1) AND Sec(2) AND Sec(4) AND N_PZ_445 AND NOT DispMode AND NOT DSel0) OR (Sec(1) AND NOT Sec(2) AND NOT Sec(4) AND N_PZ_445 AND NOT DispMode AND NOT DSel0) OR (NOT Sec(1) AND Sec(2) AND NOT Sec(4) AND Sec(5) AND NOT DispMode AND NOT DSel0) OR (NOT Sec(1) AND NOT Sec(2) AND Sec(4) AND N_PZ_445 AND NOT DispMode AND NOT DSel0) OR (NOT Sec(2) AND Sec(4) AND NOT Sec(5) AND NOT N_PZ_445 AND NOT DispMode AND NOT DSel0) OR (NOT Min(2) AND NOT N_PZ_519 AND Min(4) AND NOT N_PZ_407 AND NOT N_PZ_576 AND N_PZ_497) OR (DispMode AND NOT N_PZ_446 AND NOT Hrs(2) AND Hrs(4) AND NOT Hrs(5) AND NOT DSel2)); MuxDisplInstance/Tetr(3) <= ((NOT Min(1) AND N_PZ_519 AND NOT N_PZ_407 AND N_PZ_497) OR (NOT Hrs(1) AND DispMode AND NOT N_PZ_446 AND NOT DSel2 AND N_PZ_515) OR (Min(1) AND NOT Min(2) AND Min(4) AND N_PZ_407 AND N_PZ_497) OR (NOT Min(1) AND Min(3) AND NOT N_PZ_407 AND N_PZ_576 AND N_PZ_497) OR (NOT Sec(1) AND NOT N_PZ_445 AND NOT DispMode AND NOT DSel0 AND N_PZ_514) OR (Hrs(1) AND DispMode AND N_PZ_446 AND NOT Hrs(2) AND Hrs(4) AND NOT DSel2) OR (Min(1) AND Min(2) AND NOT Min(4) AND Min(5) AND N_PZ_407 AND N_PZ_497) OR (Sec(1) AND NOT Sec(2) AND Sec(4) AND N_PZ_445 AND NOT DispMode AND NOT DSel0) OR (Hrs(1) AND DispMode AND N_PZ_446 AND Hrs(2) AND NOT Hrs(4) AND Hrs(5) AND NOT DSel2) OR (Sec(1) AND Sec(2) AND NOT Sec(4) AND Sec(5) AND N_PZ_445 AND NOT DispMode AND NOT DSel0)); N_PZ_407 <= ((Min(3) AND N_PZ_519) OR (NOT Min(3) AND NOT N_PZ_519 AND NOT N_PZ_576) OR (Min(3) AND Min(2) AND NOT Min(4) AND NOT Min(5))); N_PZ_445 <= (NOT Sec(2) AND Sec(4)) XOR ((NOT Sec(3) AND Sec(5)) OR (Sec(2) AND Sec(3) AND NOT Sec(4) AND NOT Sec(5)) OR (NOT Sec(2) AND Sec(3) AND Sec(4) AND NOT Sec(5))); N_PZ_446 <= (NOT Hrs(2) AND Hrs(4)) XOR ((NOT Hrs(3) AND Hrs(5)) OR (Hrs(2) AND NOT Hrs(4) AND Hrs(3) AND NOT Hrs(5)) OR (NOT Hrs(2) AND Hrs(4) AND Hrs(3) AND NOT Hrs(5))); N_PZ_449 <= ((Context_FFd2 AND NOT Context_FFd1 AND ModeKeyStatus) OR (NOT Context_FFd2 AND NOT Context_FFd1 AND F1HzFF)); N_PZ_452 <= ((Context_FFd2 AND NOT Context_FFd1) OR (NOT Context_FFd2 AND NOT N_PZ_449) OR (NOT ModeKeyStatus AND NOT N_PZ_449)); N_PZ_496 <= ((Context_FFd2 AND Context_FFd1) OR (NOT Context_FFd2 AND NOT Context_FFd1 AND Min(1) AND Min1(0) AND Sec(1) AND Sec1(0) AND NOT Sec(2) AND Sec(3) AND Sec(4) AND Sec(5) AND Min(3) AND N_PZ_519)); N_PZ_497 <= ((DispMode AND NOT DSel0) OR (NOT DispMode AND NOT DSel2)); N_PZ_498 <= ((DispMode AND NOT DSel1) OR (NOT DispMode AND NOT DSel3)); N_PZ_514 <= ((NOT Sec(3) AND Sec(5)) OR (Sec(2) AND Sec(3) AND NOT Sec(5)) OR (Sec(3) AND NOT Sec(4) AND NOT Sec(5))); N_PZ_515 <= ((NOT Hrs(3) AND Hrs(5)) OR (Hrs(2) AND Hrs(3) AND NOT Hrs(5)) OR (NOT Hrs(4) AND Hrs(3) AND NOT Hrs(5))); N_PZ_519 <= (NOT Min(2) AND Min(4) AND Min(5)); N_PZ_570 <= ((Context_FFd2 AND NOT Context_FFd1) OR (NOT Context_FFd1 AND Sec(1) AND Sec1(0) AND NOT Sec(2) AND Sec(3) AND Sec(4) AND Sec(5))); N_PZ_576 <= ((Min(2) AND NOT Min(5)) OR (NOT Min(4) AND NOT Min(5))); FTCPE_Sec10: FTCPE port map (Sec1(0),Sec1_T(0),F1HzFF,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1'); Sec1_T(0) <= (NOT Context_FFd2 AND NOT Context_FFd1); FTCPE_Sec1: FTCPE port map (Sec(1),Sec_T(1),F1HzFF,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1'); Sec_T(1) <= (NOT Context_FFd2 AND NOT Context_FFd1 AND Sec1(0)); FTCPE_Sec2: FTCPE port map (Sec(2),Sec_T(2),F1HzFF,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1'); Sec_T(2) <= ((NOT Context_FFd2 AND NOT Context_FFd1 AND Sec(1) AND Sec1(0) AND NOT Sec(3)) OR (NOT Context_FFd2 AND NOT Context_FFd1 AND Sec(1) AND Sec1(0) AND NOT Sec(5)) OR (NOT Context_FFd2 AND NOT Context_FFd1 AND Sec(1) AND Sec1(0) AND NOT N_PZ_445)); FTCPE_Sec3: FTCPE port map (Sec(3),Sec_T(3),F1HzFF,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1'); Sec_T(3) <= ((NOT Context_FFd2 AND NOT Context_FFd1 AND Sec(1) AND Sec1(0) AND Sec(2)) OR (NOT Context_FFd2 AND NOT Context_FFd1 AND Sec(1) AND Sec1(0) AND Sec(3) AND Sec(4) AND Sec(5))); FTCPE_Sec4: FTCPE port map (Sec(4),Sec_T(4),F1HzFF,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1'); Sec_T(4) <= ((NOT Context_FFd2 AND NOT Context_FFd1 AND Sec(1) AND Sec1(0) AND Sec(2) AND Sec(3)) OR (NOT Context_FFd2 AND NOT Context_FFd1 AND Sec(1) AND Sec1(0) AND Sec(3) AND Sec(4) AND Sec(5))); FTCPE_Sec5: FTCPE port map (Sec(5),Sec_T(5),F1HzFF,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1'); Sec_T(5) <= ((NOT Context_FFd2 AND NOT Context_FFd1 AND Sec(1) AND Sec1(0) AND Sec(2) AND Sec(3) AND Sec(4)) OR (NOT Context_FFd2 AND NOT Context_FFd1 AND Sec(1) AND Sec1(0) AND Sec(3) AND Sec(4) AND Sec(5))); Seg_A <= (NOT MuxDisplInstance/Tetr(1) AND MuxDisplInstance/Tetr(0)) XOR ((NOT MuxDisplInstance/Tetr(1) AND MuxDisplInstance/Tetr(2) AND NOT MuxDisplInstance/Tetr(3)) OR (MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(2) AND MuxDisplInstance/Tetr(3))); Seg_B <= (NOT MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(2)) XOR ((MuxDisplInstance/Tetr(1) AND MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(3)) OR (NOT MuxDisplInstance/Tetr(1) AND MuxDisplInstance/Tetr(2) AND NOT MuxDisplInstance/Tetr(3))); Seg_C <= ((MuxDisplInstance/Tetr(1) AND MuxDisplInstance/Tetr(2) AND MuxDisplInstance/Tetr(3)) OR (NOT MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(2) AND MuxDisplInstance/Tetr(3)) OR (MuxDisplInstance/Tetr(1) AND NOT MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(2) AND NOT MuxDisplInstance/Tetr(3))); Seg_D <= ((MuxDisplInstance/Tetr(1) AND MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(2)) OR (MuxDisplInstance/Tetr(1) AND NOT MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(2) AND MuxDisplInstance/Tetr(3)) OR (NOT MuxDisplInstance/Tetr(1) AND MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(2) AND NOT MuxDisplInstance/Tetr(3)) OR (NOT MuxDisplInstance/Tetr(1) AND NOT MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(2) AND NOT MuxDisplInstance/Tetr(3))); Seg_E <= ((MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(3)) OR (NOT MuxDisplInstance/Tetr(1) AND MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(2)) OR (NOT MuxDisplInstance/Tetr(1) AND MuxDisplInstance/Tetr(2) AND NOT MuxDisplInstance/Tetr(3))); Seg_F <= (MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(3)) XOR ((NOT MuxDisplInstance/Tetr(1) AND MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(2)) OR (MuxDisplInstance/Tetr(1) AND NOT MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(2) AND NOT MuxDisplInstance/Tetr(3))); Seg_G <= ((NOT MuxDisplInstance/Tetr(1) AND NOT MuxDisplInstance/Tetr(2) AND NOT MuxDisplInstance/Tetr(3)) OR (MuxDisplInstance/Tetr(1) AND MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(2) AND NOT MuxDisplInstance/Tetr(3)) OR (NOT MuxDisplInstance/Tetr(1) AND NOT MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(2) AND MuxDisplInstance/Tetr(3))); Seg_K <= NOT (((Context_FFd2 AND Context_FFd1 AND DSel1 AND DSel0) OR (Context_FFd2 AND NOT Context_FFd1 AND DSel2 AND DSel3) OR (DSel2 AND DSel1 AND DSel0 AND DSel3) OR (NOT Context_FFd2 AND NOT Context_FFd1 AND NOT F1HzFF AND DSel1 AND DSel0 AND DSel3))); FDCPE_SetupKeyInstance/ShRegister0: FDCPE port map (SetupKeyInstance/ShRegister(0),SetupKeyInp,FDiv(4),'0',NOT Reset,'1'); FDCPE_SetupKeyInstance/ShRegister1: FDCPE port map (SetupKeyInstance/ShRegister(1),SetupKeyInstance/ShRegister(0),FDiv(4),'0',NOT Reset,'1'); FDCPE_SetupKeyInstance/ShRegister2: FDCPE port map (SetupKeyInstance/ShRegister(2),SetupKeyInstance/ShRegister(1),FDiv(4),'0',NOT Reset,'1'); FDCPE_SetupKeyInstance/ShRegister3: FDCPE port map (SetupKeyInstance/ShRegister(3),SetupKeyInstance/ShRegister(2),FDiv(4),'0',NOT Reset,'1'); LDCP_SetupKeyStatus: LDCP port map (SetupKeyStatus,NOT '0',,SetupKeyStatus_CLR,'0'); SetupKeyStatus_G <= (NOT SetupKeyInstance/ShRegister(0) AND NOT SetupKeyInstance/ShRegister(1) AND NOT SetupKeyInstance/ShRegister(2) AND NOT SetupKeyInstance/ShRegister(3)); SetupKeyStatus_CLR <= (SetupKeyInstance/ShRegister(0) AND SetupKeyInstance/ShRegister(1) AND SetupKeyInstance/ShRegister(2) AND SetupKeyInstance/ShRegister(3)); Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FDDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); FTDCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC2C256-6-TQ144 Pin Signal Pin Signal No. Name No. Name 1 VCC 73 VCCIO-1.8 2 KPR 74 KPR 3 KPR 75 KPR 4 KPR 76 KPR 5 KPR 77 KPR 6 KPR 78 KPR 7 KPR 79 KPR 8 VCCAUX 80 KPR 9 KPR 81 KPR 10 KPR 82 KPR 11 KPR 83 KPR 12 KPR 84 VCC 13 KPR 85 KPR 14 KPR 86 KPR 15 KPR 87 KPR 16 KPR 88 KPR 17 KPR 89 GND 18 KPR 90 GND 19 KPR 91 KPR 20 KPR 92 KPR 21 KPR 93 VCCIO-1.8 22 KPR 94 SetupKeyInp 23 KPR 95 KPR 24 KPR 96 KPR 25 KPR 97 KPR 26 KPR 98 KPR 27 VCCIO-1.8 99 GND 28 KPR 100 KPR 29 GND 101 KPR 30 KPR 102 KPR 31 KPR 103 KPR 32 KPR 104 KPR 33 KPR 105 KPR 34 KPR 106 KPR 35 KPR 107 KPR 36 GND 108 GND 37 VCC 109 VCCIO-1.8 38 Clk 110 KPR 39 Reset 111 KPR 40 KPR 112 KPR 41 KPR 113 KPR 42 KPR 114 KPR 43 KPR 115 KPR 44 KPR 116 KPR 45 KPR 117 KPR 46 KPR 118 KPR 47 GND 119 KPR 48 KPR 120 KPR 49 KPR 121 KPR 50 KPR 122 TDO 51 KPR 123 GND 52 KPR 124 KPR 53 Seg_B 125 KPR 54 Seg_F 126 DSel0 55 VCCIO-1.8 127 VCCIO-1.8 56 Seg_A 128 DSel1 57 Seg_E 129 DSel2 58 Seg_D 130 DSel3 59 Seg_K 131 KPR 60 Seg_C 132 KPR 61 Seg_G 133 KPR 62 GND 134 KPR 63 TDI 135 KPR 64 KPR 136 KPR 65 TMS 137 KPR 66 KPR 138 KPR 67 TCK 139 KPR 68 KPR 140 KPR 69 KPR 141 VCCIO-1.8 70 KPR 142 KPR 71 KPR 143 ModeKeyInp 72 GND 144 GND Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin KPR = Unused I/O with weak keeper (leave unconnected) WPU = Unused I/O with weak pull up (leave unconnected) TIE = Unused I/O floating -- must tie to VCC, GND or other signal VCC = Dedicated Power Pin VCCAUX = Power supply for JTAG pins VCCIO-3.3 = I/O supply voltage for LVTTL, LVCMOS33, SSTL3_I VCCIO-2.5 = I/O supply voltage for LVCMOS25, SSTL2_I VCCIO-1.8 = I/O supply voltage for LVCMOS18 VCCIO-1.5 = I/O supply voltage for LVCMOS15, HSTL_I VREF = Reference voltage for indicated input standard *VREF = Reference voltage pin selected by software GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc2c256-6-TQ144 Optimization Method : DENSITY Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Set Unused I/O Pin Termination : KEEPER Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Enable Input Registers : ON Function Block Fan-in Limit : 38 Use DATA_GATE Attribute : ON Set Tristate Outputs to Termination Mode : KEEPER Default Voltage Standard for All Outputs : LVCMOS18 Input Limit : 32 Pterm Limit : 28