********** Mapped Logic ********** |
FDCPE_Context_FFd1: FDCPE port map (Context_FFd1,Context_FFd2,NOT Clk,NOT Reset,'0',Context_FFd1_CE);
Context_FFd1_CE <= (MachineState_FFd2 AND MachineState_FFd1); |
FDCPE_Context_FFd2: FDCPE port map (Context_FFd2,NOT Context_FFd1,NOT Clk,NOT Reset,'0',Context_FFd2_CE);
Context_FFd2_CE <= (MachineState_FFd2 AND MachineState_FFd1); |
DSel0 <= NOT ((NOT MuxDisplInstance/SelCnt(0) AND
NOT MuxDisplInstance/SelCnt(1))); |
DSel1 <= NOT ((MuxDisplInstance/SelCnt(0) AND
NOT MuxDisplInstance/SelCnt(1))); |
DSel2 <= NOT ((NOT MuxDisplInstance/SelCnt(0) AND
MuxDisplInstance/SelCnt(1))); |
DSel3 <= NOT ((MuxDisplInstance/SelCnt(0) AND
MuxDisplInstance/SelCnt(1))); |
FTCPE_DispMode: FTCPE port map (DispMode,DispMode_T,NOT Clk,NOT Reset,'0','1');
DispMode_T <= ((NOT Context_FFd2 AND NOT Context_FFd1 AND MachineState_FFd2 AND NOT MachineState_FFd1) OR (NOT Context_FFd2 AND NOT Context_FFd1 AND MachineState_FFd2 AND NOT DispMode)); |
FTCPE_F1HzFF: FTCPE port map (F1HzFF,'0',F2HzDiv(18),NOT ModeKeyInstance/ShRegister(0).COMB,'0','1'); |
FTCPE_F2HzDiv0: FTCPE port map (F2HzDiv(0),'0',NOT Clk,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1'); |
FDCPE_F2HzDiv1: FDCPE port map (F2HzDiv(1),F2HzDiv_D(1),NOT Clk,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1');
F2HzDiv_D(1) <= ((NOT F2HzDiv_cmp_eq0000 AND F2HzDiv(0) AND NOT F2HzDiv(1)) OR (NOT F2HzDiv_cmp_eq0000 AND NOT F2HzDiv(0) AND F2HzDiv(1))); |
FTCPE_F2HzDiv2: FTCPE port map (F2HzDiv(2),F2HzDiv_T(2),NOT Clk,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1');
F2HzDiv_T(2) <= ((F2HzDiv_cmp_eq0000 AND F2HzDiv(2)) OR (NOT F2HzDiv_cmp_eq0000 AND F2HzDiv(0) AND F2HzDiv(1))); |
FTCPE_F2HzDiv3: FTCPE port map (F2HzDiv(3),F2HzDiv_T(3),NOT Clk,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1');
F2HzDiv_T(3) <= ((F2HzDiv_cmp_eq0000 AND F2HzDiv(3)) OR (NOT F2HzDiv_cmp_eq0000 AND F2HzDiv(0) AND F2HzDiv(1) AND F2HzDiv(2))); |
FTCPE_F2HzDiv4: FTCPE port map (F2HzDiv(4),F2HzDiv_T(4),NOT Clk,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1');
F2HzDiv_T(4) <= ((F2HzDiv_cmp_eq0000 AND F2HzDiv(4)) OR (NOT F2HzDiv_cmp_eq0000 AND F2HzDiv(0) AND F2HzDiv(1) AND F2HzDiv(2) AND F2HzDiv(3))); |
FTCPE_F2HzDiv5: FTCPE port map (F2HzDiv(5),F2HzDiv_T(5),NOT Clk,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1');
F2HzDiv_T(5) <= ((F2HzDiv_cmp_eq0000 AND F2HzDiv(5)) OR (NOT F2HzDiv_cmp_eq0000 AND F2HzDiv(0) AND F2HzDiv(1) AND F2HzDiv(2) AND F2HzDiv(3) AND F2HzDiv(4))); |
FTCPE_F2HzDiv6: FTCPE port map (F2HzDiv(6),F2HzDiv_T(6),NOT Clk,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1');
F2HzDiv_T(6) <= ((F2HzDiv_cmp_eq0000 AND F2HzDiv(6)) OR (NOT F2HzDiv_cmp_eq0000 AND F2HzDiv(0) AND F2HzDiv(1) AND F2HzDiv(2) AND F2HzDiv(3) AND F2HzDiv(4) AND F2HzDiv(5))); |
FTCPE_F2HzDiv7: FTCPE port map (F2HzDiv(7),F2HzDiv_T(7),NOT Clk,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1');
F2HzDiv_T(7) <= ((F2HzDiv_cmp_eq0000 AND F2HzDiv(7)) OR (NOT F2HzDiv_cmp_eq0000 AND F2HzDiv(0) AND F2HzDiv(1) AND F2HzDiv(2) AND F2HzDiv(3) AND F2HzDiv(4) AND F2HzDiv(5) AND F2HzDiv(6))); |
FTCPE_F2HzDiv8: FTCPE port map (F2HzDiv(8),F2HzDiv_T(8),NOT Clk,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1');
F2HzDiv_T(8) <= ((F2HzDiv_cmp_eq0000 AND F2HzDiv(8)) OR (NOT F2HzDiv_cmp_eq0000 AND F2HzDiv(0) AND F2HzDiv(1) AND F2HzDiv(2) AND F2HzDiv(3) AND F2HzDiv(4) AND F2HzDiv(5) AND F2HzDiv(6) AND F2HzDiv(7))); |
FTCPE_F2HzDiv9: FTCPE port map (F2HzDiv(9),F2HzDiv_T(9),NOT Clk,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1');
F2HzDiv_T(9) <= ((F2HzDiv_cmp_eq0000 AND F2HzDiv(9)) OR (NOT F2HzDiv_cmp_eq0000 AND F2HzDiv(0) AND F2HzDiv(1) AND F2HzDiv(2) AND F2HzDiv(3) AND F2HzDiv(4) AND F2HzDiv(5) AND F2HzDiv(6) AND F2HzDiv(7) AND F2HzDiv(8))); |
FTCPE_F2HzDiv10: FTCPE port map (F2HzDiv(10),F2HzDiv_T(10),NOT Clk,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1');
F2HzDiv_T(10) <= ((F2HzDiv_cmp_eq0000 AND F2HzDiv(10)) OR (NOT F2HzDiv_cmp_eq0000 AND F2HzDiv(0) AND F2HzDiv(1) AND F2HzDiv(2) AND F2HzDiv(3) AND F2HzDiv(4) AND F2HzDiv(5) AND F2HzDiv(6) AND F2HzDiv(7) AND F2HzDiv(8) AND F2HzDiv(9))); |
FTCPE_F2HzDiv11: FTCPE port map (F2HzDiv(11),F2HzDiv_T(11),NOT Clk,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1');
F2HzDiv_T(11) <= ((F2HzDiv_cmp_eq0000 AND F2HzDiv(11)) OR (NOT F2HzDiv_cmp_eq0000 AND F2HzDiv(0) AND F2HzDiv(10) AND F2HzDiv(1) AND F2HzDiv(2) AND F2HzDiv(3) AND F2HzDiv(4) AND F2HzDiv(5) AND F2HzDiv(6) AND F2HzDiv(7) AND F2HzDiv(8) AND F2HzDiv(9))); |
FTCPE_F2HzDiv12: FTCPE port map (F2HzDiv(12),F2HzDiv_T(12),NOT Clk,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1');
F2HzDiv_T(12) <= ((F2HzDiv_cmp_eq0000 AND F2HzDiv(12)) OR (NOT F2HzDiv_cmp_eq0000 AND F2HzDiv(0) AND F2HzDiv(10) AND F2HzDiv(1) AND F2HzDiv(2) AND F2HzDiv(3) AND F2HzDiv(4) AND F2HzDiv(5) AND F2HzDiv(6) AND F2HzDiv(7) AND F2HzDiv(8) AND F2HzDiv(9) AND F2HzDiv(11))); |
FTCPE_F2HzDiv13: FTCPE port map (F2HzDiv(13),F2HzDiv_T(13),NOT Clk,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1');
F2HzDiv_T(13) <= ((F2HzDiv_cmp_eq0000 AND F2HzDiv(13)) OR (NOT F2HzDiv_cmp_eq0000 AND F2HzDiv(0) AND F2HzDiv(10) AND F2HzDiv(1) AND F2HzDiv(2) AND F2HzDiv(3) AND F2HzDiv(4) AND F2HzDiv(5) AND F2HzDiv(6) AND F2HzDiv(7) AND F2HzDiv(8) AND F2HzDiv(9) AND F2HzDiv(11) AND F2HzDiv(12))); |
FTCPE_F2HzDiv14: FTCPE port map (F2HzDiv(14),F2HzDiv_T(14),NOT Clk,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1');
F2HzDiv_T(14) <= ((F2HzDiv_cmp_eq0000 AND F2HzDiv(14)) OR (NOT F2HzDiv_cmp_eq0000 AND F2HzDiv(0) AND F2HzDiv(10) AND F2HzDiv(1) AND F2HzDiv(2) AND F2HzDiv(3) AND F2HzDiv(4) AND F2HzDiv(5) AND F2HzDiv(6) AND F2HzDiv(7) AND F2HzDiv(8) AND F2HzDiv(9) AND F2HzDiv(11) AND F2HzDiv(12) AND F2HzDiv(13))); |
FTCPE_F2HzDiv15: FTCPE port map (F2HzDiv(15),F2HzDiv_T(15),NOT Clk,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1');
F2HzDiv_T(15) <= ((F2HzDiv_cmp_eq0000 AND F2HzDiv(15)) OR (NOT F2HzDiv_cmp_eq0000 AND F2HzDiv(0) AND F2HzDiv(10) AND F2HzDiv(1) AND F2HzDiv(2) AND F2HzDiv(3) AND F2HzDiv(4) AND F2HzDiv(5) AND F2HzDiv(6) AND F2HzDiv(7) AND F2HzDiv(8) AND F2HzDiv(9) AND F2HzDiv(11) AND F2HzDiv(12) AND F2HzDiv(13) AND F2HzDiv(14))); |
FTCPE_F2HzDiv16: FTCPE port map (F2HzDiv(16),F2HzDiv_T(16),NOT Clk,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1');
F2HzDiv_T(16) <= ((F2HzDiv_cmp_eq0000 AND F2HzDiv(16)) OR (NOT F2HzDiv_cmp_eq0000 AND F2HzDiv(0) AND F2HzDiv(10) AND F2HzDiv(1) AND F2HzDiv(2) AND F2HzDiv(3) AND F2HzDiv(4) AND F2HzDiv(5) AND F2HzDiv(6) AND F2HzDiv(7) AND F2HzDiv(8) AND F2HzDiv(9) AND F2HzDiv(11) AND F2HzDiv(12) AND F2HzDiv(13) AND F2HzDiv(14) AND F2HzDiv(15))); |
FTCPE_F2HzDiv17: FTCPE port map (F2HzDiv(17),F2HzDiv_T(17),NOT Clk,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1');
F2HzDiv_T(17) <= ((F2HzDiv_cmp_eq0000 AND F2HzDiv(17)) OR (NOT F2HzDiv_cmp_eq0000 AND F2HzDiv(0) AND F2HzDiv(10) AND F2HzDiv(1) AND F2HzDiv(2) AND F2HzDiv(3) AND F2HzDiv(4) AND F2HzDiv(5) AND F2HzDiv(6) AND F2HzDiv(7) AND F2HzDiv(8) AND F2HzDiv(9) AND F2HzDiv(11) AND F2HzDiv(12) AND F2HzDiv(13) AND F2HzDiv(14) AND F2HzDiv(15) AND F2HzDiv(16))); |
FTCPE_F2HzDiv18: FTCPE port map (F2HzDiv(18),F2HzDiv_T(18),NOT Clk,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1');
F2HzDiv_T(18) <= ((F2HzDiv(18) AND F2HzDiv_cmp_eq0000) OR (NOT F2HzDiv_cmp_eq0000 AND F2HzDiv(0) AND F2HzDiv(10) AND F2HzDiv(1) AND F2HzDiv(2) AND F2HzDiv(3) AND F2HzDiv(4) AND F2HzDiv(5) AND F2HzDiv(6) AND F2HzDiv(7) AND F2HzDiv(8) AND F2HzDiv(9) AND F2HzDiv(11) AND F2HzDiv(12) AND F2HzDiv(13) AND F2HzDiv(14) AND F2HzDiv(15) AND F2HzDiv(16) AND F2HzDiv(17))); |
F2HzDiv_cmp_eq0000 <= (F2HzDiv(18) AND F2HzDiv(0) AND NOT F2HzDiv(10) AND
F2HzDiv(1) AND F2HzDiv(2) AND F2HzDiv(3) AND F2HzDiv(4) AND NOT F2HzDiv(5) AND NOT F2HzDiv(6) AND NOT F2HzDiv(7) AND F2HzDiv(8) AND NOT F2HzDiv(9) AND NOT F2HzDiv(11) AND NOT F2HzDiv(12) AND F2HzDiv(13) AND NOT F2HzDiv(14) AND F2HzDiv(15) AND F2HzDiv(16) AND F2HzDiv(17)); |
FTCPE_FClk: FTCPE port map (FClk,FClk_T,NOT Clk,NOT Reset,'0','1');
FClk_T <= (FDivInstance/FDivCnt(0) AND FDivInstance/FDivCnt(1) AND FDivInstance/FDivCnt(2) AND FDivInstance/FDivCnt(3) AND FDivInstance/FDivCnt(4) AND FDivInstance/FDivCnt(5) AND FDivInstance/FDivCnt(6)); |
FTCPE_FDiv0: FTCPE port map (FDiv(0),'0',FClk,NOT Reset,'0','1'); |
FTCPE_FDiv1: FTCPE port map (FDiv(1),FDiv(0),FClk,NOT Reset,'0','1'); |
FTCPE_FDiv2: FTCPE port map (FDiv(2),FDiv_T(2),FClk,NOT Reset,'0','1');
FDiv_T(2) <= (FDiv(0) AND FDiv(1)); |
FTCPE_FDiv3: FTCPE port map (FDiv(3),FDiv_T(3),FClk,NOT Reset,'0','1');
FDiv_T(3) <= (FDiv(0) AND FDiv(1) AND FDiv(2)); |
FTCPE_FDiv4: FTCPE port map (FDiv(4),FDiv_T(4),FClk,NOT Reset,'0','1');
FDiv_T(4) <= (FDiv(3) AND FDiv(0) AND FDiv(1) AND FDiv(2)); |
FTCPE_FDivInstance/FDivCnt0: FTCPE port map (FDivInstance/FDivCnt(0),'0',NOT Clk,NOT Reset,'0','1'); |
FTCPE_FDivInstance/FDivCnt1: FTCPE port map (FDivInstance/FDivCnt(1),FDivInstance/FDivCnt(0),NOT Clk,NOT Reset,'0','1'); |
FTCPE_FDivInstance/FDivCnt2: FTCPE port map (FDivInstance/FDivCnt(2),FDivInstance/FDivCnt_T(2),NOT Clk,NOT Reset,'0','1');
FDivInstance/FDivCnt_T(2) <= (FDivInstance/FDivCnt(0) AND FDivInstance/FDivCnt(1)); |
FTCPE_FDivInstance/FDivCnt3: FTCPE port map (FDivInstance/FDivCnt(3),FDivInstance/FDivCnt_T(3),NOT Clk,NOT Reset,'0','1');
FDivInstance/FDivCnt_T(3) <= (FDivInstance/FDivCnt(0) AND FDivInstance/FDivCnt(1) AND FDivInstance/FDivCnt(2)); |
FTCPE_FDivInstance/FDivCnt4: FTCPE port map (FDivInstance/FDivCnt(4),FDivInstance/FDivCnt_T(4),NOT Clk,NOT Reset,'0','1');
FDivInstance/FDivCnt_T(4) <= (FDivInstance/FDivCnt(0) AND FDivInstance/FDivCnt(1) AND FDivInstance/FDivCnt(2) AND FDivInstance/FDivCnt(3)); |
FTCPE_FDivInstance/FDivCnt5: FTCPE port map (FDivInstance/FDivCnt(5),FDivInstance/FDivCnt_T(5),NOT Clk,NOT Reset,'0','1');
FDivInstance/FDivCnt_T(5) <= (FDivInstance/FDivCnt(0) AND FDivInstance/FDivCnt(1) AND FDivInstance/FDivCnt(2) AND FDivInstance/FDivCnt(3) AND FDivInstance/FDivCnt(4)); |
FTCPE_FDivInstance/FDivCnt6: FTCPE port map (FDivInstance/FDivCnt(6),FDivInstance/FDivCnt_T(6),NOT Clk,NOT Reset,'0','1');
FDivInstance/FDivCnt_T(6) <= (FDivInstance/FDivCnt(0) AND FDivInstance/FDivCnt(1) AND FDivInstance/FDivCnt(2) AND FDivInstance/FDivCnt(3) AND FDivInstance/FDivCnt(4) AND FDivInstance/FDivCnt(5)); |
FTCPE_Hrs10: FTCPE port map (Hrs1(0),N_PZ_496,N_PZ_452,NOT Reset,'0','1'); |
FTCPE_Hrs1: FTCPE port map (Hrs(1),Hrs_T(1),N_PZ_452,NOT Reset,'0','1');
Hrs_T(1) <= (Hrs1(0) AND N_PZ_496); |
FTCPE_Hrs2: FTCPE port map (Hrs(2),Hrs_T(2),N_PZ_452,NOT Reset,'0','1');
Hrs_T(2) <= (Hrs(1) AND Hrs1(0) AND N_PZ_496); |
FTCPE_Hrs3: FTCPE port map (Hrs(3),Hrs_T(3),N_PZ_452,NOT Reset,'0','1');
Hrs_T(3) <= ((Hrs(1) AND Hrs1(0) AND N_PZ_496 AND Hrs(2) AND NOT Hrs(4)) OR (Hrs(1) AND Hrs1(0) AND N_PZ_496 AND Hrs(2) AND Hrs(3)) OR (Hrs(1) AND Hrs1(0) AND N_PZ_496 AND Hrs(2) AND Hrs(5))); |
FTCPE_Hrs4: FTCPE port map (Hrs(4),Hrs_T(4),N_PZ_452,NOT Reset,'0','1');
Hrs_T(4) <= ((Hrs(1) AND Hrs1(0) AND N_PZ_496 AND Hrs(2) AND Hrs(3)) OR (Hrs(1) AND Hrs1(0) AND N_PZ_496 AND Hrs(2) AND Hrs(4) AND NOT Hrs(5))); |
FTCPE_Hrs5: FTCPE port map (Hrs(5),Hrs_T(5),N_PZ_452,NOT Reset,'0','1');
Hrs_T(5) <= (Hrs(1) AND Hrs1(0) AND N_PZ_496 AND Hrs(2) AND Hrs(4) AND Hrs(3)); |
FDCPE_MachineState_FFd1: FDCPE port map (MachineState_FFd1,MachineState_FFd1_D,NOT Clk,NOT Reset,'0','1');
MachineState_FFd1_D <= NOT (((NOT MachineState_FFd2 AND NOT MachineState_FFd1 AND ModeKeyStatus) OR (NOT MachineState_FFd2 AND NOT ModeKeyStatus AND NOT SetupKeyStatus))); |
FDCPE_MachineState_FFd2: FDCPE port map (MachineState_FFd2,MachineState_FFd2_D,NOT Clk,NOT Reset,'0','1');
MachineState_FFd2_D <= ((NOT MachineState_FFd2 AND NOT MachineState_FFd1 AND ModeKeyStatus) OR (NOT MachineState_FFd2 AND NOT MachineState_FFd1 AND SetupKeyStatus)); |
FTCPE_Min10: FTCPE port map (Min1(0),N_PZ_570,N_PZ_449,NOT Reset,'0','1'); |
FTCPE_Min1: FTCPE port map (Min(1),Min_T(1),N_PZ_449,NOT Reset,'0','1');
Min_T(1) <= (Min1(0) AND N_PZ_570); |
FTCPE_Min2: FTCPE port map (Min(2),Min_T(2),N_PZ_449,NOT Reset,'0','1');
Min_T(2) <= ((Min(1) AND Min1(0) AND N_PZ_570 AND NOT Min(3)) OR (Min(1) AND Min1(0) AND N_PZ_570 AND NOT N_PZ_519)); |
FTCPE_Min3: FTCPE port map (Min(3),Min_T(3),N_PZ_449,NOT Reset,'0','1');
Min_T(3) <= ((Min(1) AND Min1(0) AND N_PZ_570 AND Min(2)) OR (Min(1) AND Min1(0) AND N_PZ_570 AND Min(3) AND Min(4) AND Min(5))); |
FTCPE_Min4: FTCPE port map (Min(4),Min_T(4),N_PZ_449,NOT Reset,'0','1');
Min_T(4) <= ((Min(1) AND Min1(0) AND N_PZ_570 AND Min(3) AND Min(2)) OR (Min(1) AND Min1(0) AND N_PZ_570 AND Min(3) AND Min(4) AND Min(5))); |
FTCPE_Min5: FTCPE port map (Min(5),Min_T(5),N_PZ_449,NOT Reset,'0','1');
Min_T(5) <= ((Min(1) AND Min1(0) AND N_PZ_570 AND Min(3) AND Min(2) AND Min(4)) OR (Min(1) AND Min1(0) AND N_PZ_570 AND Min(3) AND Min(4) AND Min(5))); |
ModeKeyInstance/ShRegister(0).COMB <= ((Reset AND Context_FFd2)
OR (Reset AND NOT Context_FFd1));FDCPE_ModeKeyInstance/ShRegister0: FDCPE port map (ModeKeyInstance/ShRegister(0),ModeKeyInp,FDiv(4),'0',NOT Reset,'1'); |
FDCPE_ModeKeyInstance/ShRegister1: FDCPE port map (ModeKeyInstance/ShRegister(1),ModeKeyInstance/ShRegister(0),FDiv(4),'0',NOT Reset,'1'); |
FDCPE_ModeKeyInstance/ShRegister2: FDCPE port map (ModeKeyInstance/ShRegister(2),ModeKeyInstance/ShRegister(1),FDiv(4),'0',NOT Reset,'1'); |
FDCPE_ModeKeyInstance/ShRegister3: FDCPE port map (ModeKeyInstance/ShRegister(3),ModeKeyInstance/ShRegister(2),FDiv(4),'0',NOT Reset,'1'); |
LDCP_ModeKeyStatus: LDCP port map (ModeKeyStatus,NOT '0',,ModeKeyStatus_CLR,'0');
ModeKeyStatus_G <= (NOT ModeKeyInstance/ShRegister(0) AND NOT ModeKeyInstance/ShRegister(1) AND NOT ModeKeyInstance/ShRegister(2) AND NOT ModeKeyInstance/ShRegister(3)); ModeKeyStatus_CLR <= (ModeKeyInstance/ShRegister(0) AND ModeKeyInstance/ShRegister(1) AND ModeKeyInstance/ShRegister(2) AND ModeKeyInstance/ShRegister(3)); |
FTCPE_MuxDisplInstance/SelCnt0: FTCPE port map (MuxDisplInstance/SelCnt(0),'0',FDiv(3),NOT Reset,'0','1'); |
FTCPE_MuxDisplInstance/SelCnt1: FTCPE port map (MuxDisplInstance/SelCnt(1),MuxDisplInstance/SelCnt(0),FDiv(3),NOT Reset,'0','1'); |
MuxDisplInstance/Tetr(0) <= ((Min1(0) AND N_PZ_497)
OR (N_PZ_407 AND N_PZ_498) OR (Hrs1(0) AND DispMode AND NOT DSel2) OR (Sec1(0) AND NOT DispMode AND NOT DSel0) OR (N_PZ_445 AND NOT DispMode AND NOT DSel1) OR (DispMode AND N_PZ_446 AND NOT DSel3) OR (Hrs(1) AND DispMode AND NOT DSel3 AND N_PZ_515) OR (Min(1) AND Min(3) AND N_PZ_576 AND N_PZ_498) OR (Min(1) AND NOT Min(3) AND Min(5) AND N_PZ_498) OR (Sec(1) AND NOT DispMode AND NOT DSel1 AND N_PZ_514)); |
MuxDisplInstance/Tetr(1) <= ((NOT Min(1) AND N_PZ_407 AND N_PZ_497)
OR (NOT Hrs(1) AND DispMode AND N_PZ_446 AND NOT DSel2) OR (Min(1) AND NOT Min(3) AND N_PZ_576 AND N_PZ_497) OR (NOT Sec(1) AND N_PZ_445 AND NOT DispMode AND NOT DSel0) OR (NOT N_PZ_519 AND Min(4) AND NOT N_PZ_407 AND N_PZ_498) OR (NOT Min(4) AND Min(5) AND N_PZ_407 AND N_PZ_498) OR (Hrs(1) AND DispMode AND NOT N_PZ_446 AND NOT DSel2 AND NOT N_PZ_515) OR (Min(1) AND Min(3) AND NOT N_PZ_519 AND NOT N_PZ_576 AND N_PZ_497) OR (Sec(1) AND NOT N_PZ_445 AND NOT DispMode AND NOT DSel0 AND NOT N_PZ_514) OR (Sec(3) AND Sec(4) AND NOT N_PZ_445 AND NOT DispMode AND NOT DSel1) OR (NOT Sec(4) AND Sec(5) AND N_PZ_445 AND NOT DispMode AND NOT DSel1) OR (DispMode AND N_PZ_446 AND NOT Hrs(4) AND Hrs(5) AND NOT DSel3) OR (DispMode AND NOT N_PZ_446 AND Hrs(4) AND Hrs(3) AND NOT DSel3) OR (NOT Sec(3) AND Sec(4) AND NOT Sec(5) AND NOT N_PZ_445 AND NOT DispMode AND NOT DSel1) OR (DispMode AND NOT N_PZ_446 AND Hrs(4) AND NOT Hrs(3) AND NOT Hrs(5) AND NOT DSel3)); |
MuxDisplInstance/Tetr(2) <= ((Min(3) AND Min(5) AND N_PZ_498)
OR (Min(4) AND Min(5) AND N_PZ_498) OR (Sec(4) AND Sec(5) AND NOT DispMode AND NOT DSel1) OR (Sec(5) AND NOT N_PZ_445 AND NOT DispMode AND NOT DSel1) OR (Min(2) AND NOT Min(4) AND NOT N_PZ_407 AND N_PZ_497) OR (DispMode AND NOT N_PZ_446 AND Hrs(5) AND NOT DSel3) OR (DispMode AND Hrs(4) AND Hrs(5) AND NOT DSel3) OR (Min(1) AND Min(3) AND Min(2) AND NOT Min(4) AND N_PZ_497) OR (Min(1) AND Min(2) AND Min(4) AND N_PZ_407 AND N_PZ_497) OR (Min(1) AND NOT Min(2) AND NOT Min(4) AND N_PZ_407 AND N_PZ_497) OR (NOT Min(1) AND NOT Min(2) AND Min(4) AND N_PZ_407 AND N_PZ_497) OR (Sec(2) AND NOT Sec(4) AND NOT N_PZ_445 AND NOT DispMode AND NOT DSel0) OR (DispMode AND NOT N_PZ_446 AND Hrs(2) AND NOT Hrs(4) AND NOT DSel2) OR (Hrs(1) AND DispMode AND N_PZ_446 AND Hrs(2) AND Hrs(4) AND NOT DSel2) OR (Hrs(1) AND DispMode AND N_PZ_446 AND NOT Hrs(2) AND NOT Hrs(4) AND NOT DSel2) OR (Hrs(1) AND DispMode AND Hrs(2) AND NOT Hrs(4) AND Hrs(3) AND NOT DSel2) OR (NOT Hrs(1) AND DispMode AND N_PZ_446 AND NOT Hrs(2) AND Hrs(4) AND NOT DSel2) OR (NOT Hrs(1) AND DispMode AND Hrs(2) AND NOT Hrs(4) AND Hrs(5) AND NOT DSel2) OR (NOT Min(1) AND Min(2) AND NOT Min(4) AND Min(5) AND N_PZ_407 AND N_PZ_497) OR (Sec(1) AND Sec(2) AND Sec(3) AND NOT Sec(4) AND NOT DispMode AND NOT DSel0) OR (Sec(1) AND Sec(2) AND Sec(4) AND N_PZ_445 AND NOT DispMode AND NOT DSel0) OR (Sec(1) AND NOT Sec(2) AND NOT Sec(4) AND N_PZ_445 AND NOT DispMode AND NOT DSel0) OR (NOT Sec(1) AND Sec(2) AND NOT Sec(4) AND Sec(5) AND NOT DispMode AND NOT DSel0) OR (NOT Sec(1) AND NOT Sec(2) AND Sec(4) AND N_PZ_445 AND NOT DispMode AND NOT DSel0) OR (NOT Sec(2) AND Sec(4) AND NOT Sec(5) AND NOT N_PZ_445 AND NOT DispMode AND NOT DSel0) OR (NOT Min(2) AND NOT N_PZ_519 AND Min(4) AND NOT N_PZ_407 AND NOT N_PZ_576 AND N_PZ_497) OR (DispMode AND NOT N_PZ_446 AND NOT Hrs(2) AND Hrs(4) AND NOT Hrs(5) AND NOT DSel2)); |
MuxDisplInstance/Tetr(3) <= ((NOT Min(1) AND N_PZ_519 AND NOT N_PZ_407 AND N_PZ_497)
OR (NOT Hrs(1) AND DispMode AND NOT N_PZ_446 AND NOT DSel2 AND N_PZ_515) OR (Min(1) AND NOT Min(2) AND Min(4) AND N_PZ_407 AND N_PZ_497) OR (NOT Min(1) AND Min(3) AND NOT N_PZ_407 AND N_PZ_576 AND N_PZ_497) OR (NOT Sec(1) AND NOT N_PZ_445 AND NOT DispMode AND NOT DSel0 AND N_PZ_514) OR (Hrs(1) AND DispMode AND N_PZ_446 AND NOT Hrs(2) AND Hrs(4) AND NOT DSel2) OR (Min(1) AND Min(2) AND NOT Min(4) AND Min(5) AND N_PZ_407 AND N_PZ_497) OR (Sec(1) AND NOT Sec(2) AND Sec(4) AND N_PZ_445 AND NOT DispMode AND NOT DSel0) OR (Hrs(1) AND DispMode AND N_PZ_446 AND Hrs(2) AND NOT Hrs(4) AND Hrs(5) AND NOT DSel2) OR (Sec(1) AND Sec(2) AND NOT Sec(4) AND Sec(5) AND N_PZ_445 AND NOT DispMode AND NOT DSel0)); |
N_PZ_407 <= ((Min(3) AND N_PZ_519)
OR (NOT Min(3) AND NOT N_PZ_519 AND NOT N_PZ_576) OR (Min(3) AND Min(2) AND NOT Min(4) AND NOT Min(5))); |
N_PZ_445 <= (NOT Sec(2) AND Sec(4))
XOR ((NOT Sec(3) AND Sec(5)) OR (Sec(2) AND Sec(3) AND NOT Sec(4) AND NOT Sec(5)) OR (NOT Sec(2) AND Sec(3) AND Sec(4) AND NOT Sec(5))); |
N_PZ_446 <= (NOT Hrs(2) AND Hrs(4))
XOR ((NOT Hrs(3) AND Hrs(5)) OR (Hrs(2) AND NOT Hrs(4) AND Hrs(3) AND NOT Hrs(5)) OR (NOT Hrs(2) AND Hrs(4) AND Hrs(3) AND NOT Hrs(5))); |
N_PZ_449 <= ((Context_FFd2 AND NOT Context_FFd1 AND ModeKeyStatus)
OR (NOT Context_FFd2 AND NOT Context_FFd1 AND F1HzFF)); |
N_PZ_452 <= ((Context_FFd2 AND NOT Context_FFd1)
OR (NOT Context_FFd2 AND NOT N_PZ_449) OR (NOT ModeKeyStatus AND NOT N_PZ_449)); |
N_PZ_496 <= ((Context_FFd2 AND Context_FFd1)
OR (NOT Context_FFd2 AND NOT Context_FFd1 AND Min(1) AND Min1(0) AND Sec(1) AND Sec1(0) AND NOT Sec(2) AND Sec(3) AND Sec(4) AND Sec(5) AND Min(3) AND N_PZ_519)); |
N_PZ_497 <= ((DispMode AND NOT DSel0)
OR (NOT DispMode AND NOT DSel2)); |
N_PZ_498 <= ((DispMode AND NOT DSel1)
OR (NOT DispMode AND NOT DSel3)); |
N_PZ_514 <= ((NOT Sec(3) AND Sec(5))
OR (Sec(2) AND Sec(3) AND NOT Sec(5)) OR (Sec(3) AND NOT Sec(4) AND NOT Sec(5))); |
N_PZ_515 <= ((NOT Hrs(3) AND Hrs(5))
OR (Hrs(2) AND Hrs(3) AND NOT Hrs(5)) OR (NOT Hrs(4) AND Hrs(3) AND NOT Hrs(5))); |
N_PZ_519 <= (NOT Min(2) AND Min(4) AND Min(5)); |
N_PZ_570 <= ((Context_FFd2 AND NOT Context_FFd1)
OR (NOT Context_FFd1 AND Sec(1) AND Sec1(0) AND NOT Sec(2) AND Sec(3) AND Sec(4) AND Sec(5))); |
N_PZ_576 <= ((Min(2) AND NOT Min(5))
OR (NOT Min(4) AND NOT Min(5))); |
FTCPE_Sec10: FTCPE port map (Sec1(0),Sec1_T(0),F1HzFF,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1');
Sec1_T(0) <= (NOT Context_FFd2 AND NOT Context_FFd1); |
FTCPE_Sec1: FTCPE port map (Sec(1),Sec_T(1),F1HzFF,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1');
Sec_T(1) <= (NOT Context_FFd2 AND NOT Context_FFd1 AND Sec1(0)); |
FTCPE_Sec2: FTCPE port map (Sec(2),Sec_T(2),F1HzFF,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1');
Sec_T(2) <= ((NOT Context_FFd2 AND NOT Context_FFd1 AND Sec(1) AND Sec1(0) AND NOT Sec(3)) OR (NOT Context_FFd2 AND NOT Context_FFd1 AND Sec(1) AND Sec1(0) AND NOT Sec(5)) OR (NOT Context_FFd2 AND NOT Context_FFd1 AND Sec(1) AND Sec1(0) AND NOT N_PZ_445)); |
FTCPE_Sec3: FTCPE port map (Sec(3),Sec_T(3),F1HzFF,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1');
Sec_T(3) <= ((NOT Context_FFd2 AND NOT Context_FFd1 AND Sec(1) AND Sec1(0) AND Sec(2)) OR (NOT Context_FFd2 AND NOT Context_FFd1 AND Sec(1) AND Sec1(0) AND Sec(3) AND Sec(4) AND Sec(5))); |
FTCPE_Sec4: FTCPE port map (Sec(4),Sec_T(4),F1HzFF,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1');
Sec_T(4) <= ((NOT Context_FFd2 AND NOT Context_FFd1 AND Sec(1) AND Sec1(0) AND Sec(2) AND Sec(3)) OR (NOT Context_FFd2 AND NOT Context_FFd1 AND Sec(1) AND Sec1(0) AND Sec(3) AND Sec(4) AND Sec(5))); |
FTCPE_Sec5: FTCPE port map (Sec(5),Sec_T(5),F1HzFF,NOT ModeKeyInstance/ShRegister(0).COMB,'0','1');
Sec_T(5) <= ((NOT Context_FFd2 AND NOT Context_FFd1 AND Sec(1) AND Sec1(0) AND Sec(2) AND Sec(3) AND Sec(4)) OR (NOT Context_FFd2 AND NOT Context_FFd1 AND Sec(1) AND Sec1(0) AND Sec(3) AND Sec(4) AND Sec(5))); |
Seg_A <= (NOT MuxDisplInstance/Tetr(1) AND
MuxDisplInstance/Tetr(0)) XOR ((NOT MuxDisplInstance/Tetr(1) AND MuxDisplInstance/Tetr(2) AND NOT MuxDisplInstance/Tetr(3)) OR (MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(2) AND MuxDisplInstance/Tetr(3))); |
Seg_B <= (NOT MuxDisplInstance/Tetr(0) AND
MuxDisplInstance/Tetr(2)) XOR ((MuxDisplInstance/Tetr(1) AND MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(3)) OR (NOT MuxDisplInstance/Tetr(1) AND MuxDisplInstance/Tetr(2) AND NOT MuxDisplInstance/Tetr(3))); |
Seg_C <= ((MuxDisplInstance/Tetr(1) AND
MuxDisplInstance/Tetr(2) AND MuxDisplInstance/Tetr(3)) OR (NOT MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(2) AND MuxDisplInstance/Tetr(3)) OR (MuxDisplInstance/Tetr(1) AND NOT MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(2) AND NOT MuxDisplInstance/Tetr(3))); |
Seg_D <= ((MuxDisplInstance/Tetr(1) AND
MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(2)) OR (MuxDisplInstance/Tetr(1) AND NOT MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(2) AND MuxDisplInstance/Tetr(3)) OR (NOT MuxDisplInstance/Tetr(1) AND MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(2) AND NOT MuxDisplInstance/Tetr(3)) OR (NOT MuxDisplInstance/Tetr(1) AND NOT MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(2) AND NOT MuxDisplInstance/Tetr(3))); |
Seg_E <= ((MuxDisplInstance/Tetr(0) AND
NOT MuxDisplInstance/Tetr(3)) OR (NOT MuxDisplInstance/Tetr(1) AND MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(2)) OR (NOT MuxDisplInstance/Tetr(1) AND MuxDisplInstance/Tetr(2) AND NOT MuxDisplInstance/Tetr(3))); |
Seg_F <= (MuxDisplInstance/Tetr(0) AND
NOT MuxDisplInstance/Tetr(3)) XOR ((NOT MuxDisplInstance/Tetr(1) AND MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(2)) OR (MuxDisplInstance/Tetr(1) AND NOT MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(2) AND NOT MuxDisplInstance/Tetr(3))); |
Seg_G <= ((NOT MuxDisplInstance/Tetr(1) AND
NOT MuxDisplInstance/Tetr(2) AND NOT MuxDisplInstance/Tetr(3)) OR (MuxDisplInstance/Tetr(1) AND MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(2) AND NOT MuxDisplInstance/Tetr(3)) OR (NOT MuxDisplInstance/Tetr(1) AND NOT MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(2) AND MuxDisplInstance/Tetr(3))); |
Seg_K <= NOT (((Context_FFd2 AND Context_FFd1 AND DSel1 AND DSel0)
OR (Context_FFd2 AND NOT Context_FFd1 AND DSel2 AND DSel3) OR (DSel2 AND DSel1 AND DSel0 AND DSel3) OR (NOT Context_FFd2 AND NOT Context_FFd1 AND NOT F1HzFF AND DSel1 AND DSel0 AND DSel3))); |
FDCPE_SetupKeyInstance/ShRegister0: FDCPE port map (SetupKeyInstance/ShRegister(0),SetupKeyInp,FDiv(4),'0',NOT Reset,'1'); |
FDCPE_SetupKeyInstance/ShRegister1: FDCPE port map (SetupKeyInstance/ShRegister(1),SetupKeyInstance/ShRegister(0),FDiv(4),'0',NOT Reset,'1'); |
FDCPE_SetupKeyInstance/ShRegister2: FDCPE port map (SetupKeyInstance/ShRegister(2),SetupKeyInstance/ShRegister(1),FDiv(4),'0',NOT Reset,'1'); |
FDCPE_SetupKeyInstance/ShRegister3: FDCPE port map (SetupKeyInstance/ShRegister(3),SetupKeyInstance/ShRegister(2),FDiv(4),'0',NOT Reset,'1'); |
LDCP_SetupKeyStatus: LDCP port map (SetupKeyStatus,NOT '0',,SetupKeyStatus_CLR,'0');
SetupKeyStatus_G <= (NOT SetupKeyInstance/ShRegister(0) AND NOT SetupKeyInstance/ShRegister(1) AND NOT SetupKeyInstance/ShRegister(2) AND NOT SetupKeyInstance/ShRegister(3)); SetupKeyStatus_CLR <= (SetupKeyInstance/ShRegister(0) AND SetupKeyInstance/ShRegister(1) AND SetupKeyInstance/ShRegister(2) AND SetupKeyInstance/ShRegister(3)); |
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE); FDDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); FTDCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); |