cpldfit:  version J.36                              Xilinx Inc.
                                  Fitter Report
Design Name: Generator                           Date:  4- 4-2010,  1:43AM
Device Used: XC2C256-6-TQ144
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
97 /256 ( 38%) 240 /896  ( 27%) 166 /640  ( 26%) 69 /256 ( 27%) 19 /118 ( 16%)

** Function Block Resources **

Function Mcells   FB Inps  Pterms   IO       CTC      CTR      CTS      CTE     
Block    Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot
FB1      16/16*    17/40    19/56     0/ 6    1/1*     1/1*     1/1*     0/1
FB2      14/16     25/40    56/56*    0/ 8    1/1*     1/1*     1/1*     0/1
FB3      16/16*    32/40    42/56     0/ 6    1/1*     1/1*     1/1*     0/1
FB4      16/16*    20/40    50/56     0/ 8    1/1*     1/1*     0/1      0/1
FB5      16/16*    35/40    33/56     0/ 5    1/1*     1/1*     0/1      0/1
FB6       4/16     12/40     7/56     0/ 8    1/1*     1/1*     0/1      0/1
FB7       0/16      0/40     0/56     0/ 8    0/1      0/1      0/1      0/1
FB8       0/16      0/40     0/56     0/ 8    0/1      0/1      0/1      0/1
FB9       0/16      0/40     0/56     0/ 8    0/1      0/1      0/1      0/1
FB10      0/16      0/40     0/56     0/ 9    0/1      0/1      0/1      0/1
FB11      5/16      4/40     6/56     4/ 8    1/1*     0/1      1/1*     0/1
FB12      0/16      0/40     0/56     0/ 6    0/1      0/1      0/1      0/1
FB13      0/16      0/40     0/56     0/ 8    0/1      0/1      0/1      0/1
FB14      3/16     11/40     8/56     3/ 8    1/1*     1/1*     1/1*     0/1
FB15      0/16      0/40     0/56     0/ 7    0/1      0/1      0/1      0/1
FB16      7/16     10/40    19/56     7/ 7*   0/1      0/1      0/1      0/1
         -----    -------  -------   -----    ---      ---      ---      ---
Total    97/256   166/640  240/896   14/118   8/16     7/16     5/16     0/16

CTC - Control Term Clock
CTR - Control Term Reset
CTS - Control Term Set
CTE - Control Term Output Enable

* - Resource is exhausted

** Global Control Resources **

GCK         GSR         GTS         
Used/Tot    Used/Tot    Used/Tot    
1/3         0/1         0/4

Signal 'Clk' mapped onto global clock net GCK2.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :    4           4    |  I/O              :    16    108
Output        :   14          14    |  GCK/IO           :     1      3
Bidirectional :    0           0    |  GTS/IO           :     0      4
GCK           :    1           1    |  GSR/IO           :     1      1
GTS           :    0           0    |  CDR/IO           :     0      1
GSR           :    0           0    |  DGE/IO           :     1      1
                 ----        ----
        Total     19          19

End of Mapped Resource Summary
*************************  Summary of Mapped Logic  ************************

** 14 Outputs **

Signal                                Total Total Loc     Pin   Pin       Pin     I/O      I/O       Slew Reg     Reg Init
Name                                  Pts   Inps          No.   Type      Use     STD      Style     Rate Use     State
DSel0                                 1     2     FB11_13 126   I/O       O       LVCMOS18           FAST         
DSel1                                 1     2     FB11_14 128   I/O       O       LVCMOS18           FAST         
DSel2                                 1     2     FB11_15 129   I/O       O       LVCMOS18           FAST         
DSel3                                 1     2     FB11_16 130   I/O       O       LVCMOS18           FAST         
OutSig                                3     5     FB14_4  69    I/O       O       LVCMOS18           FAST TFF     RESET
DirLed                                2     3     FB14_6  68    I/O       O       LVCMOS18           FAST TFF/S   SET
Seg_G                                 3     4     FB14_16 61    I/O       O       LVCMOS18           FAST         
Seg_C                                 3     4     FB16_5  60    I/O       O       LVCMOS18           FAST         
Seg_K                                 4     6     FB16_6  59    I/O       O       LVCMOS18           FAST         
Seg_D                                 4     4     FB16_11 58    I/O       O       LVCMOS18           FAST         
Seg_E                                 3     4     FB16_12 57    I/O       O       LVCMOS18           FAST         
Seg_A                                 3     4     FB16_13 56    I/O       O       LVCMOS18           FAST         
Seg_F                                 3     4     FB16_15 54    I/O       O       LVCMOS18           FAST         
Seg_B                                 3     4     FB16_16 53    I/O       O       LVCMOS18           FAST         

** 83 Buried Nodes **

Signal                                Total Total Loc     Reg     Reg Init
Name                                  Pts   Inps          Use     State
FDivInstance/FDivCnt<5>               2     6     FB1_1   TFF     RESET
FDivInstance/FDivCnt<4>               2     5     FB1_2   TFF     RESET
ModeKeyInstance/ShRegister<0>         3     3     FB1_3   DFF     RESET
ModeKeyInstance/ShRegister<3>         3     3     FB1_4   DFF     RESET
FDivInstance/FDivCnt<3>               2     4     FB1_5   TFF     RESET
ModeKeyInstance/ShRegister<2>         3     3     FB1_6   DFF     RESET
FDivInstance/FDivCnt<2>               2     3     FB1_7   TFF     RESET
FDivInstance/FDivCnt<1>               2     2     FB1_8   TFF     RESET
DirKeyStatus                          2     4     FB1_9   LATCH   RESET
DirKeyInstance/ShRegister<3>          3     3     FB1_10  DFF     RESET
DirKeyInstance/ShRegister<2>          3     3     FB1_11  DFF     RESET
ModeKeyInstance/ShRegister<1>         3     3     FB1_12  DFF     RESET
FClk                                  2     8     FB1_13  TFF     RESET
FDivInstance/FDivCnt<6>               2     7     FB1_14  TFF     RESET
DirKeyInstance/ShRegister<1>          3     3     FB1_15  DFF     RESET
FDivInstance/FDivCnt<0>               1     1     FB1_16  TFF     RESET
BinCnt<7>                             6     10    FB2_2   TFF     RESET
MuxDisplInstance/SelCnt<0>            2     2     FB2_4   TFF     RESET
BinCnt<4>                             5     7     FB2_5   DFF     RESET
LCmpReg<2>                            4     6     FB2_6   TFF     RESET
LCmpReg<3>                            4     7     FB2_7   TFF     RESET
LCmpReg<4>                            4     8     FB2_8   TFF     RESET
LCmpReg<5>                            4     9     FB2_9   TFF     RESET
LCmpReg<6>                            4     10    FB2_10  TFF     RESET
LCmpReg<7>                            4     11    FB2_11  TFF     RESET
BinCnt<2>                             5     7     FB2_12  DFF     RESET
BinCnt<3>                             6     9     FB2_13  DFF     RESET
BinCnt<5>                             6     8     FB2_14  DFF     RESET
BinCnt<6>                             6     9     FB2_15  TFF     RESET
Mcompar_BinCnt_cmp_eq0000_AEB_or0000  16    16    FB2_16          
MachineState_FFd2                     3     5     FB3_1   DFF     RESET
MachineState_FFd1                     3     5     FB3_2   DFF     RESET
Context_FFd1                          3     4     FB3_3   DEFF    RESET
BinCnt<0>                             4     6     FB3_4   TFF     RESET
Context_FFd2                          3     5     FB3_5   TFF     RESET
BinCnt<1>                             4     7     FB3_6   TFF     RESET
UCmpReg<1>                            4     5     FB3_7   TFF     RESET
UCmpReg<2>                            4     6     FB3_8   TFF     RESET
UCmpReg<7>                            4     11    FB3_9   TFF     RESET
UCmpReg<6>                            4     10    FB3_10  TFF     RESET

Signal                                Total Total Loc     Reg     Reg Init
Name                                  Pts   Inps          Use     State
UCmpReg<5>                            4     9     FB3_11  TFF     RESET
UCmpReg<4>                            4     8     FB3_12  TFF     RESET
UCmpReg<3>                            4     7     FB3_13  TFF     RESET
LCmpReg<1>                            4     5     FB3_14  TFF     RESET
N_PZ_522                              9     16    FB3_15          
N_PZ_457                              1     4     FB3_16          
FDiv<1>                               3     3     FB4_1   TFF     RESET
FDiv<0>                               2     2     FB4_2   TFF     RESET
UCmpReg<0>                            3     3     FB4_3   TFF     RESET
LCmpReg<0>                            3     3     FB4_4   TFF     RESET
SetupKeyInstance/DelayCnt<0>          3     3     FB4_5   TFF     RESET
SetupKeyInstance/DelayCnt<1>          3     4     FB4_6   TFF     RESET
SetupKeyInstance/DelayCnt<4>          3     7     FB4_7   TFF     RESET
SetKeyStatus                          3     5     FB4_8   DFF     RESET
SetupKeyInstance/DelayCntEnable       3     6     FB4_9   DFF     RESET
SetupKeyInstance/DelayCntClear        3     6     FB4_10  DFF     RESET
SetupKeyInstance/AutomatState_FFd2    4     10    FB4_11  DFF     RESET
SetupKeyInstance/DelayCnt<2>          3     5     FB4_12  TFF     RESET
SetupKeyInstance/AutomatState_FFd1    7     11    FB4_13  DFF     RESET
SetupKeyInstance/DelayCnt<3>          3     6     FB4_14  TFF     RESET
SetupKeyInstance/AutomatState_FFd3    6     11    FB4_15  TFF     RESET
SetupKeyInstance/AutomatState_FFd4    10    11    FB4_16  DFF     RESET
N_PZ_456                              2     2     FB5_1           
FDiv<5>                               3     7     FB5_2   TFF     RESET
OutFF_or000049                        1     2     FB5_3           
FDiv<4>                               3     6     FB5_4   TFF     RESET
MuxDisplInstance/SelCnt<1>            3     3     FB5_5   TFF     RESET
N_PZ_526                              1     3     FB5_6           
OutFF_or000041                        1     2     FB5_7           
OutFF_or000048                        1     2     FB5_8           
OutFF_or000040                        1     2     FB5_9           
OutFF_or000047                        1     2     FB5_10          
OutFF_or000039                        1     2     FB5_11          
MuxDisplInstance/Tetr<3>              4     8     FB5_12          
MuxDisplInstance/Tetr<2>              4     8     FB5_13          
N_PZ_521                              2     2     FB5_14          
MuxDisplInstance/Tetr<1>              4     8     FB5_15          
MuxDisplInstance/Tetr<0>              4     8     FB5_16          
ModeKeyStatus                         2     4     FB6_8   LATCH   RESET
FDiv<6>                               3     8     FB6_9   TFF     RESET

Signal                                Total Total Loc     Reg     Reg Init
Name                                  Pts   Inps          Use     State
FDiv<3>                               3     5     FB6_10  TFF     RESET
FDiv<2>                               3     4     FB6_11  TFF     RESET
DirKeyInstance/ShRegister<0>          2     2     FB11_11 DFF     RESET

** 5 Inputs **

Signal                                Loc     Pin   Pin       Pin     I/O      I/O
Name                                          No.   Type      Use     STD      Style
ModeKeyInp                            FB1_3   143   GSR/I/O   I       LVCMOS18 PU
Clk                                   FB6_4   38    GCK/I/O   GCK     LVCMOS18 PU
Reset                                 FB6_12  39    DGE/I/O   I       LVCMOS18 PU
DirKeyInp                             FB11_11 124   I/O       I       LVCMOS18 PU
SetKeyInp                             FB12_15 94    I/O       I       LVCMOS18 PU

Legend:
Pin No.   - ~     - User Assigned
I/O Style - OD    - OpenDrain
          - PU    - Pullup
          - KPR   - Keeper
          - S     - SchmittTrigger
          - DG    - DataGate
Reg Use   - LATCH - Transparent latch
          - DFF   - D-flip-flop
          - DEFF  - D-flip-flop with clock enable
          - TFF   - T-flip-flop
          - TDFF  - Dual-edge-triggered T-flip-flop
          - DDFF  - Dual-edge-triggered flip-flop
          - DDEFF - Dual-edge-triggered flip-flop with clock enable
          /S (after any above flop/latch type) indicates initial state is Set
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
              VRF - Vref
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               17/23
Number of function block control terms used/remaining:        3/1
Number of PLA product terms used/remaining:                   19/37
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
FDivInstance/FDivCnt<5>       2     FB1_1        (b)     (b)        +      
FDivInstance/FDivCnt<4>       2     FB1_2        (b)     (b)        +      
ModeKeyInstance/ShRegister<0> 3     FB1_3   143  GSR/I/O I      +       +  
ModeKeyInstance/ShRegister<3> 3     FB1_4   142  I/O     (b)    +       +  
FDivInstance/FDivCnt<3>       2     FB1_5        (b)     (b)        +      
ModeKeyInstance/ShRegister<2> 3     FB1_6   140  I/O     (b)    +       +  
FDivInstance/FDivCnt<2>       2     FB1_7        (b)     (b)        +      
FDivInstance/FDivCnt<1>       2     FB1_8        (b)     (b)        +      
DirKeyStatus                  2     FB1_9        (b)     (b)               
DirKeyInstance/ShRegister<3>  3     FB1_10       (b)     (b)    +       +  
DirKeyInstance/ShRegister<2>  3     FB1_11       (b)     (b)    +       +  
ModeKeyInstance/ShRegister<1> 3     FB1_12  139  I/O     (b)    +       +  
FClk                          2     FB1_13  138  I/O     (b)        +      
FDivInstance/FDivCnt<6>       2     FB1_14  137  I/O     (b)        +      
DirKeyInstance/ShRegister<1>  3     FB1_15       (b)     (b)    +       +  
FDivInstance/FDivCnt<0>       1     FB1_16       (b)     (b)        +      

Signals Used by Logic in Function Block
  1: DirKeyInstance/ShRegister<0>   7: FDivInstance/FDivCnt<1>  13: ModeKeyInstance/ShRegister<0> 
  2: DirKeyInstance/ShRegister<1>   8: FDivInstance/FDivCnt<2>  14: ModeKeyInstance/ShRegister<1> 
  3: DirKeyInstance/ShRegister<2>   9: FDivInstance/FDivCnt<3>  15: ModeKeyInstance/ShRegister<2> 
  4: DirKeyInstance/ShRegister<3>  10: FDivInstance/FDivCnt<4>  16: Reset 
  5: FDiv<4>                       11: FDivInstance/FDivCnt<5>  17: SetupKeyInstance/DelayCntClear 
  6: FDivInstance/FDivCnt<0>       12: FDivInstance/FDivCnt<6> 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
FDivInstance/FDivCnt<5> 
                  .....XXXXX.....X........................ 6       
FDivInstance/FDivCnt<4> 
                  .....XXXX......X........................ 5       
ModeKeyInstance/ShRegister<0> 
                  ....X..........XX....................... 3       
ModeKeyInstance/ShRegister<3> 
                  ....X.........XX........................ 3       
FDivInstance/FDivCnt<3> 
                  .....XXX.......X........................ 4       
ModeKeyInstance/ShRegister<2> 
                  ....X........X.X........................ 3       
FDivInstance/FDivCnt<2> 
                  .....XX........X........................ 3       
FDivInstance/FDivCnt<1> 
                  .....X.........X........................ 2       
DirKeyStatus      XXXX.................................... 4       
DirKeyInstance/ShRegister<3> 
                  ..X.X..........X........................ 3       
DirKeyInstance/ShRegister<2> 
                  .X..X..........X........................ 3       
ModeKeyInstance/ShRegister<1> 
                  ....X.......X..X........................ 3       
FClk              .....XXXXXXX...X........................ 8       
FDivInstance/FDivCnt<6> 
                  .....XXXXXX....X........................ 7       
DirKeyInstance/ShRegister<1> 
                  X...X..........X........................ 3       
FDivInstance/FDivCnt<0> 
                  ...............X........................ 1       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB2  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               25/15
Number of function block control terms used/remaining:        3/1
Number of PLA product terms used/remaining:                   56/0
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB2_1   2    GTS/I/O       
BinCnt<7>                     6     FB2_2        (b)     (b)    +   +      
(unused)                      0     FB2_3   3    GTS/I/O       
MuxDisplInstance/SelCnt<0>    2     FB2_4   4    I/O     (b)    +   +      
BinCnt<4>                     5     FB2_5   5    GTS/I/O (b)    +   +      
LCmpReg<2>                    4     FB2_6        (b)     (b)        +      
LCmpReg<3>                    4     FB2_7        (b)     (b)        +      
LCmpReg<4>                    4     FB2_8        (b)     (b)        +      
LCmpReg<5>                    4     FB2_9        (b)     (b)        +      
LCmpReg<6>                    4     FB2_10       (b)     (b)        +      
LCmpReg<7>                    4     FB2_11       (b)     (b)            +  
BinCnt<2>                     5     FB2_12  6    GTS/I/O (b)    +   +      
BinCnt<3>                     6     FB2_13  7    I/O     (b)    +   +      
BinCnt<5>                     6     FB2_14  9    I/O     (b)    +   +      
BinCnt<6>                     6     FB2_15  10   I/O     (b)    +   +      
Mcompar_BinCnt_cmp_eq0000_AEB_or0000
                              16    FB2_16       (b)     (b)               

Signals Used by Logic in Function Block
  1: BinCnt<0>         10: Context_FFd2      18: LCmpReg<5> 
  2: BinCnt<1>         11: DirLed            19: LCmpReg<6> 
  3: BinCnt<2>         12: FDiv<3>           20: LCmpReg<7> 
  4: BinCnt<3>         13: LCmpReg<0>        21: N_PZ_457 
  5: BinCnt<4>         14: LCmpReg<1>        22: N_PZ_522 
  6: BinCnt<5>         15: LCmpReg<2>        23: N_PZ_526 
  7: BinCnt<6>         16: LCmpReg<3>        24: Reset 
  8: BinCnt<7>         17: LCmpReg<4>        25: SetKeyStatus 
  9: Context_FFd1     

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
BinCnt<7>         ....XXXXXX.X.........XXX................ 10      
MuxDisplInstance/SelCnt<0> 
                  ...........X...........X................ 2       
BinCnt<4>         ....X...XX.X.........XXX................ 7       
LCmpReg<2>        .........XX.XX.........XX............... 6       
LCmpReg<3>        .........XX.XXX........XX............... 7       
LCmpReg<4>        .........XX.XXXX.......XX............... 8       
LCmpReg<5>        .........XX.XXXXX......XX............... 9       
LCmpReg<6>        .........XX.XXXXXX.....XX............... 10      
LCmpReg<7>        .........XX.XXXXXXX....XX............... 11      
BinCnt<2>         ..X.....XX.X........XX.X................ 7       
BinCnt<3>         ..XX....XX.X........XXXX................ 9       
BinCnt<5>         ....XX..XX.X.........XXX................ 8       
BinCnt<6>         ....XXX.XX.X.........XXX................ 9       
Mcompar_BinCnt_cmp_eq0000_AEB_or0000 
                  XXXXXXXX....XXXXXXXX.................... 16      
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB3  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               32/8
Number of function block control terms used/remaining:        3/1
Number of PLA product terms used/remaining:                   42/14
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
MachineState_FFd2             3     FB3_1   136  I/O     (b)        +      
MachineState_FFd1             3     FB3_2   135  I/O     (b)        +      
Context_FFd1                  3     FB3_3   134  I/O     (b)        +      
BinCnt<0>                     4     FB3_4        (b)     (b)        +      
Context_FFd2                  3     FB3_5   133  I/O     (b)        +      
BinCnt<1>                     4     FB3_6        (b)     (b)        +      
UCmpReg<1>                    4     FB3_7        (b)     (b)    +   +      
UCmpReg<2>                    4     FB3_8        (b)     (b)    +   +      
UCmpReg<7>                    4     FB3_9        (b)     (b)    +       +  
UCmpReg<6>                    4     FB3_10       (b)     (b)    +   +      
UCmpReg<5>                    4     FB3_11       (b)     (b)    +   +      
UCmpReg<4>                    4     FB3_12       (b)     (b)    +   +      
UCmpReg<3>                    4     FB3_13       (b)     (b)    +   +      
LCmpReg<1>                    4     FB3_14  132  I/O     (b)    +   +      
N_PZ_522                      9     FB3_15       (b)     (b)               
N_PZ_457                      1     FB3_16  131  I/O     (b)               

Signals Used by Logic in Function Block
  1: BinCnt<0>          12: Mcompar_BinCnt_cmp_eq0000_AEB_or0000  23: OutSig 
  2: BinCnt<1>          13: ModeKeyStatus                         24: Reset 
  3: BinCnt<2>          14: N_PZ_456                              25: SetKeyStatus 
  4: Context_FFd1       15: N_PZ_521                              26: UCmpReg<0> 
  5: Context_FFd2       16: N_PZ_522                              27: UCmpReg<1> 
  6: DirKeyStatus       17: OutFF_or000039                        28: UCmpReg<2> 
  7: DirLed             18: OutFF_or000040                        29: UCmpReg<3> 
  8: FDiv<3>            19: OutFF_or000041                        30: UCmpReg<4> 
  9: LCmpReg<0>         20: OutFF_or000047                        31: UCmpReg<5> 
 10: MachineState_FFd1  21: OutFF_or000048                        32: UCmpReg<6> 
 11: MachineState_FFd2  22: OutFF_or000049                       

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
MachineState_FFd2 
                  .....X...XX.X..........X................ 5       
MachineState_FFd1 
                  .....X...XX.X..........X................ 5       
Context_FFd1      ....X....XX............X................ 4       
BinCnt<0>         X..XX..X.......X.......X................ 6       
Context_FFd2      ...XX....XX............X................ 5       
BinCnt<1>         XX.XX..X.......X.......X................ 7       
UCmpReg<1>        ...X..X................XXX.............. 5       
UCmpReg<2>        ...X..X................XXXX............. 6       
UCmpReg<7>        ...X..X................XXXXXXXXX........ 11      
UCmpReg<6>        ...X..X................XXXXXXXX......... 10      
UCmpReg<5>        ...X..X................XXXXXXX.......... 9       
UCmpReg<4>        ...X..X................XXXXXX........... 8       
UCmpReg<3>        ...X..X................XXXXX............ 7       
LCmpReg<1>        ....X.X.X..............XX............... 5       
N_PZ_522          XXX........X.XX.XXXXXXX..XXX............ 16      
N_PZ_457          XX.XX................................... 4       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB4  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               20/20
Number of function block control terms used/remaining:        2/2
Number of PLA product terms used/remaining:                   50/6
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
FDiv<1>                       3     FB4_1   11   I/O     (b)        +      
FDiv<0>                       2     FB4_2   12   I/O     (b)        +      
UCmpReg<0>                    3     FB4_3   13   I/O     (b)        +      
LCmpReg<0>                    3     FB4_4   14   I/O     (b)        +      
SetupKeyInstance/DelayCnt<0>  3     FB4_5   15   I/O     (b)    +          
SetupKeyInstance/DelayCnt<1>  3     FB4_6   16   I/O     (b)    +          
SetupKeyInstance/DelayCnt<4>  3     FB4_7        (b)     (b)    +          
SetKeyStatus                  3     FB4_8        (b)     (b)               
SetupKeyInstance/DelayCntEnable
                              3     FB4_9        (b)     (b)               
SetupKeyInstance/DelayCntClear
                              3     FB4_10       (b)     (b)               
SetupKeyInstance/AutomatState_FFd2
                              4     FB4_11       (b)     (b)        +      
SetupKeyInstance/DelayCnt<2>  3     FB4_12  17   I/O     (b)    +          
SetupKeyInstance/AutomatState_FFd1
                              7     FB4_13       (b)     (b)        +      
SetupKeyInstance/DelayCnt<3>  3     FB4_14  18   I/O     (b)    +          
SetupKeyInstance/AutomatState_FFd3
                              6     FB4_15       (b)     (b)        +      
SetupKeyInstance/AutomatState_FFd4
                              10    FB4_16       (b)     (b)        +      

Signals Used by Logic in Function Block
  1: Context_FFd1                         8: SetKeyInp                           15: SetupKeyInstance/DelayCnt<1> 
  2: Context_FFd2                         9: SetKeyStatus                        16: SetupKeyInstance/DelayCnt<2> 
  3: FClk                                10: SetupKeyInstance/AutomatState_FFd1  17: SetupKeyInstance/DelayCnt<3> 
  4: FDiv<0>                             11: SetupKeyInstance/AutomatState_FFd2  18: SetupKeyInstance/DelayCnt<4> 
  5: FDiv<6>                             12: SetupKeyInstance/AutomatState_FFd3  19: SetupKeyInstance/DelayCntClear 
  6: ModeKeyInstance/ShRegister<0>.COMB  13: SetupKeyInstance/AutomatState_FFd4  20: SetupKeyInstance/DelayCntEnable 
  7: Reset                               14: SetupKeyInstance/DelayCnt<0>       

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
FDiv<1>           ..XX..X................................. 3       
FDiv<0>           ..X...X................................. 2       
UCmpReg<0>        X.....X.X............................... 3       
LCmpReg<0>        .X....X.X............................... 3       
SetupKeyInstance/DelayCnt<0> 
                  ....XX.............X.................... 3       
SetupKeyInstance/DelayCnt<1> 
                  ....XX.......X.....X.................... 4       
SetupKeyInstance/DelayCnt<4> 
                  ....XX.......XXXX..X.................... 7       
SetKeyStatus      ......X.X.XXX........................... 5       
SetupKeyInstance/DelayCntEnable 
                  ......X..XXXX......X.................... 6       
SetupKeyInstance/DelayCntClear 
                  ......X..XXXX.....X..................... 6       
SetupKeyInstance/AutomatState_FFd2 
                  ......X..XXXXXXXXX...................... 10      
SetupKeyInstance/DelayCnt<2> 
                  ....XX.......XX....X.................... 5       
SetupKeyInstance/AutomatState_FFd1 
                  ......XX.XXXXXXXXX...................... 11      
SetupKeyInstance/DelayCnt<3> 
                  ....XX.......XXX...X.................... 6       
SetupKeyInstance/AutomatState_FFd3 
                  ......XX.XXXXXXXXX...................... 11      
SetupKeyInstance/AutomatState_FFd4 
                  ......XX.XXXXXXXXX...................... 11      
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB5  ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               35/5
Number of function block control terms used/remaining:        2/2
Number of PLA product terms used/remaining:                   33/23
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
N_PZ_456                      2     FB5_1        (b)     (b)               
FDiv<5>                       3     FB5_2   33   I/O     (b)    +   +      
OutFF_or000049                1     FB5_3        (b)     (b)               
FDiv<4>                       3     FB5_4   32   GCK/I/O (b)    +   +      
MuxDisplInstance/SelCnt<1>    3     FB5_5   31   I/O     (b)        +      
N_PZ_526                      1     FB5_6   30   GCK/I/O (b)               
OutFF_or000041                1     FB5_7        (b)     (b)               
OutFF_or000048                1     FB5_8        (b)     (b)               
OutFF_or000040                1     FB5_9        (b)     (b)               
OutFF_or000047                1     FB5_10       (b)     (b)               
OutFF_or000039                1     FB5_11       (b)     (b)               
MuxDisplInstance/Tetr<3>      4     FB5_12       (b)     (b)               
MuxDisplInstance/Tetr<2>      4     FB5_13       (b)     (b)               
N_PZ_521                      2     FB5_14  28   I/O     (b)               
MuxDisplInstance/Tetr<1>      4     FB5_15       (b)     (b)               
MuxDisplInstance/Tetr<0>      4     FB5_16       (b)     (b)               

Signals Used by Logic in Function Block
  1: BinCnt<2>         13: FDiv<1>           25: MuxDisplInstance/SelCnt<0> 
  2: BinCnt<3>         14: FDiv<2>           26: N_PZ_457 
  3: BinCnt<4>         15: FDiv<3>           27: Reset 
  4: BinCnt<5>         16: FDiv<4>           28: UCmpReg<0> 
  5: BinCnt<6>         17: LCmpReg<0>        29: UCmpReg<1> 
  6: BinCnt<7>         18: LCmpReg<1>        30: UCmpReg<2> 
  7: DSel0             19: LCmpReg<2>        31: UCmpReg<3> 
  8: DSel1             20: LCmpReg<3>        32: UCmpReg<4> 
  9: DSel2             21: LCmpReg<4>        33: UCmpReg<5> 
 10: DSel3             22: LCmpReg<5>        34: UCmpReg<6> 
 11: FClk              23: LCmpReg<6>        35: UCmpReg<7> 
 12: FDiv<0>           24: LCmpReg<7>       

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
N_PZ_456          .X............................X......... 2       
FDiv<5>           ..........XXXXXX..........X............. 7       
OutFF_or000049    .....X............................X..... 2       
FDiv<4>           ..........XXXXX...........X............. 6       
MuxDisplInstance/SelCnt<1> 
                  ..............X.........X.X............. 3       
N_PZ_526          XX.......................X.............. 3       
OutFF_or000041    .....X............................X..... 2       
OutFF_or000048    ....X............................X...... 2       
OutFF_or000040    ....X............................X...... 2       
OutFF_or000047    ...X............................X....... 2       
OutFF_or000039    ...X............................X....... 2       
MuxDisplInstance/Tetr<3> 
                  ......XXXX.........X...X......X...X..... 8       
MuxDisplInstance/Tetr<2> 
                  ......XXXX........X...X......X...X...... 8       
N_PZ_521          ..X............................X........ 2       
MuxDisplInstance/Tetr<1> 
                  ......XXXX.......X...X......X...X....... 8       
MuxDisplInstance/Tetr<0> 
                  ......XXXX......X...X......X...X........ 8       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB6  ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               12/28
Number of function block control terms used/remaining:        2/2
Number of PLA product terms used/remaining:                   7/49
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB6_1   34   I/O           
(unused)                      0     FB6_2   35   CDR/I/O       
(unused)                      0     FB6_3        (b)           
(unused)                      0     FB6_4   38   GCK/I/O GCK   
(unused)                      0     FB6_5        (b)           
(unused)                      0     FB6_6        (b)           
(unused)                      0     FB6_7        (b)           
ModeKeyStatus                 2     FB6_8        (b)     (b)               
FDiv<6>                       3     FB6_9        (b)     (b)    +   +      
FDiv<3>                       3     FB6_10       (b)     (b)    +   +      
FDiv<2>                       3     FB6_11       (b)     (b)    +   +      
(unused)                      0     FB6_12  39   DGE/I/O I     
(unused)                      0     FB6_13  40   I/O           
(unused)                      0     FB6_14  41   I/O           
(unused)                      0     FB6_15  42   I/O           
(unused)                      0     FB6_16  43   I/O           

Signals Used by Logic in Function Block
  1: FClk               5: FDiv<3>                         9: ModeKeyInstance/ShRegister<1> 
  2: FDiv<0>            6: FDiv<4>                        10: ModeKeyInstance/ShRegister<2> 
  3: FDiv<1>            7: FDiv<5>                        11: ModeKeyInstance/ShRegister<3> 
  4: FDiv<2>            8: ModeKeyInstance/ShRegister<0>  12: Reset 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
ModeKeyStatus     .......XXXX............................. 4       
FDiv<6>           XXXXXXX....X............................ 8       
FDiv<3>           XXXX.......X............................ 5       
FDiv<2>           XXX........X............................ 4       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB7  ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB7_1        (b)           
(unused)                      0     FB7_2        (b)           
(unused)                      0     FB7_3        (b)           
(unused)                      0     FB7_4        (b)           
(unused)                      0     FB7_5   26   I/O           
(unused)                      0     FB7_6   25   I/O           
(unused)                      0     FB7_7        (b)           
(unused)                      0     FB7_8        (b)           
(unused)                      0     FB7_9        (b)           
(unused)                      0     FB7_10       (b)           
(unused)                      0     FB7_11  24   I/O           
(unused)                      0     FB7_12  23   I/O           
(unused)                      0     FB7_13  22   I/O           
(unused)                      0     FB7_14  21   I/O           
(unused)                      0     FB7_15  20   I/O           
(unused)                      0     FB7_16  19   I/O           
*********************************** FB8  ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB8_1   44   I/O           
(unused)                      0     FB8_2   45   I/O           
(unused)                      0     FB8_3   46   I/O           
(unused)                      0     FB8_4        (b)           
(unused)                      0     FB8_5   48   I/O           
(unused)                      0     FB8_6   49   I/O           
(unused)                      0     FB8_7        (b)           
(unused)                      0     FB8_8        (b)           
(unused)                      0     FB8_9        (b)           
(unused)                      0     FB8_10       (b)           
(unused)                      0     FB8_11  50   I/O           
(unused)                      0     FB8_12  51   I/O           
(unused)                      0     FB8_13  52   I/O           
(unused)                      0     FB8_14       (b)           
(unused)                      0     FB8_15       (b)           
(unused)                      0     FB8_16       (b)           
*********************************** FB9  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB9_1   112  I/O           
(unused)                      0     FB9_2   113  I/O           
(unused)                      0     FB9_3        (b)           
(unused)                      0     FB9_4   114  I/O           
(unused)                      0     FB9_5        (b)           
(unused)                      0     FB9_6   115  I/O           
(unused)                      0     FB9_7        (b)           
(unused)                      0     FB9_8        (b)           
(unused)                      0     FB9_9        (b)           
(unused)                      0     FB9_10       (b)           
(unused)                      0     FB9_11       (b)           
(unused)                      0     FB9_12  116  I/O           
(unused)                      0     FB9_13  117  I/O           
(unused)                      0     FB9_14  118  I/O           
(unused)                      0     FB9_15  119  I/O           
(unused)                      0     FB9_16       (b)           
*********************************** FB10 ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB10_1  111  I/O           
(unused)                      0     FB10_2  110  I/O           
(unused)                      0     FB10_3  107  I/O           
(unused)                      0     FB10_4  106  I/O           
(unused)                      0     FB10_5  105  I/O           
(unused)                      0     FB10_6  104  I/O           
(unused)                      0     FB10_7       (b)           
(unused)                      0     FB10_8       (b)           
(unused)                      0     FB10_9       (b)           
(unused)                      0     FB10_10      (b)           
(unused)                      0     FB10_11      (b)           
(unused)                      0     FB10_12 103  I/O           
(unused)                      0     FB10_13      (b)           
(unused)                      0     FB10_14 102  I/O           
(unused)                      0     FB10_15      (b)           
(unused)                      0     FB10_16 101  I/O           
*********************************** FB11 ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               4/36
Number of function block control terms used/remaining:        2/2
Number of PLA product terms used/remaining:                   6/50
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB11_1       (b)           
(unused)                      0     FB11_2       (b)           
(unused)                      0     FB11_3       (b)           
(unused)                      0     FB11_4       (b)           
(unused)                      0     FB11_5  120  I/O           
(unused)                      0     FB11_6  121  I/O           
(unused)                      0     FB11_7       (b)           
(unused)                      0     FB11_8       (b)           
(unused)                      0     FB11_9       (b)           
(unused)                      0     FB11_10      (b)           
DirKeyInstance/ShRegister<0>  2     FB11_11 124  I/O     I      +       +  
(unused)                      0     FB11_12 125  I/O           
DSel0                         1     FB11_13 126  I/O     O                 
DSel1                         1     FB11_14 128  I/O     O                 
DSel2                         1     FB11_15 129  I/O     O                 
DSel3                         1     FB11_16 130  I/O     O                 

Signals Used by Logic in Function Block
  1: FDiv<4>                      3: MuxDisplInstance/SelCnt<1>   4: Reset 
  2: MuxDisplInstance/SelCnt<0> 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
DSel0             .XX..................................... 2       
DSel1             .XX..................................... 2       
DSel2             .XX..................................... 2       
DSel3             .XX..................................... 2       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB12 ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB12_1       (b)           
(unused)                      0     FB12_2  100  I/O           
(unused)                      0     FB12_3       (b)           
(unused)                      0     FB12_4       (b)           
(unused)                      0     FB12_5       (b)           
(unused)                      0     FB12_6       (b)           
(unused)                      0     FB12_7       (b)           
(unused)                      0     FB12_8       (b)           
(unused)                      0     FB12_9       (b)           
(unused)                      0     FB12_10      (b)           
(unused)                      0     FB12_11 98   I/O           
(unused)                      0     FB12_12 97   I/O           
(unused)                      0     FB12_13 96   I/O           
(unused)                      0     FB12_14 95   I/O           
(unused)                      0     FB12_15 94   I/O     I     
(unused)                      0     FB12_16      (b)           
*********************************** FB13 ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB13_1  75   I/O           
(unused)                      0     FB13_2  76   I/O           
(unused)                      0     FB13_3  77   I/O           
(unused)                      0     FB13_4       (b)           
(unused)                      0     FB13_5  78   I/O           
(unused)                      0     FB13_6  79   I/O           
(unused)                      0     FB13_7       (b)           
(unused)                      0     FB13_8       (b)           
(unused)                      0     FB13_9       (b)           
(unused)                      0     FB13_10      (b)           
(unused)                      0     FB13_11      (b)           
(unused)                      0     FB13_12 80   I/O           
(unused)                      0     FB13_13 81   I/O           
(unused)                      0     FB13_14 82   I/O           
(unused)                      0     FB13_15      (b)           
(unused)                      0     FB13_16      (b)           
*********************************** FB14 ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               11/29
Number of function block control terms used/remaining:        3/1
Number of PLA product terms used/remaining:                   8/48
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB14_1  74   I/O           
(unused)                      0     FB14_2  71   I/O           
(unused)                      0     FB14_3  70   I/O           
OutSig                        3     FB14_4  69   I/O     O      +   +      
(unused)                      0     FB14_5       (b)           
DirLed                        2     FB14_6  68   I/O     O              +  
(unused)                      0     FB14_7       (b)           
(unused)                      0     FB14_8       (b)           
(unused)                      0     FB14_9       (b)           
(unused)                      0     FB14_10      (b)           
(unused)                      0     FB14_11      (b)           
(unused)                      0     FB14_12      (b)           
(unused)                      0     FB14_13 66   I/O           
(unused)                      0     FB14_14 64   I/O           
(unused)                      0     FB14_15      (b)           
Seg_G                         3     FB14_16 61   I/O     O                 

Signals Used by Logic in Function Block
  1: Context_FFd1        5: MachineState_FFd2          9: MuxDisplInstance/Tetr<3> 
  2: Context_FFd2        6: MuxDisplInstance/Tetr<0>  10: N_PZ_522 
  3: FDiv<3>             7: MuxDisplInstance/Tetr<1>  11: Reset 
  4: MachineState_FFd1   8: MuxDisplInstance/Tetr<2> 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
OutSig            XXX......XX............................. 5       
DirLed            ...XX.....X............................. 3       
Seg_G             .....XXXX............................... 4       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB15 ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB15_1       (b)           
(unused)                      0     FB15_2  83   I/O           
(unused)                      0     FB15_3       (b)           
(unused)                      0     FB15_4       (b)           
(unused)                      0     FB15_5       (b)           
(unused)                      0     FB15_6       (b)           
(unused)                      0     FB15_7       (b)           
(unused)                      0     FB15_8       (b)           
(unused)                      0     FB15_9       (b)           
(unused)                      0     FB15_10      (b)           
(unused)                      0     FB15_11 85   I/O           
(unused)                      0     FB15_12 86   I/O           
(unused)                      0     FB15_13 87   I/O           
(unused)                      0     FB15_14 88   I/O           
(unused)                      0     FB15_15 91   I/O           
(unused)                      0     FB15_16 92   I/O           
*********************************** FB16 ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               10/30
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   19/37
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB16_1       (b)           
(unused)                      0     FB16_2       (b)           
(unused)                      0     FB16_3       (b)           
(unused)                      0     FB16_4       (b)           
Seg_C                         3     FB16_5  60   I/O     O                 
Seg_K                         4     FB16_6  59   I/O     O                 
(unused)                      0     FB16_7       (b)           
(unused)                      0     FB16_8       (b)           
(unused)                      0     FB16_9       (b)           
(unused)                      0     FB16_10      (b)           
Seg_D                         4     FB16_11 58   I/O     O                 
Seg_E                         3     FB16_12 57   I/O     O                 
Seg_A                         3     FB16_13 56   I/O     O                 
(unused)                      0     FB16_14      (b)           
Seg_F                         3     FB16_15 54   I/O     O                 
Seg_B                         3     FB16_16 53   I/O     O                 

Signals Used by Logic in Function Block
  1: Context_FFd1       5: DSel2                      8: MuxDisplInstance/Tetr<1> 
  2: Context_FFd2       6: DSel3                      9: MuxDisplInstance/Tetr<2> 
  3: DSel0              7: MuxDisplInstance/Tetr<0>  10: MuxDisplInstance/Tetr<3> 
  4: DSel1            

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
Seg_C             ......XXXX.............................. 4       
Seg_K             XXXXXX.................................. 6       
Seg_D             ......XXXX.............................. 4       
Seg_E             ......XXXX.............................. 4       
Seg_A             ......XXXX.............................. 4       
Seg_F             ......XXXX.............................. 4       
Seg_B             ......XXXX.............................. 4       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********

FTCPE_BinCnt0: FTCPE port map (BinCnt(0),BinCnt_T(0),FDiv(3),NOT Reset,'0','1');
BinCnt_T(0) <= ((NOT Context_FFd2 AND NOT Context_FFd1 AND NOT N_PZ_522)
	OR (NOT Context_FFd2 AND NOT Context_FFd1 AND BinCnt(0)));

FTCPE_BinCnt1: FTCPE port map (BinCnt(1),BinCnt_T(1),FDiv(3),NOT Reset,'0','1');
BinCnt_T(1) <= ((NOT Context_FFd2 AND NOT Context_FFd1 AND N_PZ_522 AND 
	BinCnt(1))
	OR (NOT Context_FFd2 AND NOT Context_FFd1 AND NOT N_PZ_522 AND 
	BinCnt(0)));

FDCPE_BinCnt2: FDCPE port map (BinCnt(2),BinCnt_D(2),FDiv(3),NOT Reset,'0','1');
BinCnt_D(2) <= NOT (((BinCnt(2) AND N_PZ_457)
	OR (NOT BinCnt(2) AND NOT N_PZ_457)
	OR (NOT Context_FFd2 AND NOT Context_FFd1 AND N_PZ_522)));

FDCPE_BinCnt3: FDCPE port map (BinCnt(3),BinCnt_D(3),FDiv(3),NOT Reset,'0','1');
BinCnt_D(3) <= NOT (((N_PZ_526)
	OR (NOT BinCnt(2) AND NOT BinCnt(3))
	OR (NOT N_PZ_457 AND NOT BinCnt(3))
	OR (NOT Context_FFd2 AND NOT Context_FFd1 AND N_PZ_522)));

FDCPE_BinCnt4: FDCPE port map (BinCnt(4),BinCnt_D(4),FDiv(3),NOT Reset,'0','1');
BinCnt_D(4) <= NOT (((N_PZ_526 AND BinCnt(4))
	OR (NOT N_PZ_526 AND NOT BinCnt(4))
	OR (NOT Context_FFd2 AND NOT Context_FFd1 AND N_PZ_522)));

FDCPE_BinCnt5: FDCPE port map (BinCnt(5),BinCnt_D(5),FDiv(3),NOT Reset,'0','1');
BinCnt_D(5) <= NOT (((NOT N_PZ_526 AND NOT BinCnt(5))
	OR (NOT BinCnt(4) AND NOT BinCnt(5))
	OR (NOT Context_FFd2 AND NOT Context_FFd1 AND N_PZ_522)
	OR (N_PZ_526 AND BinCnt(4) AND BinCnt(5))));

FTCPE_BinCnt6: FTCPE port map (BinCnt(6),BinCnt_T(6),FDiv(3),NOT Reset,'0','1');
BinCnt_T(6) <= ((Context_FFd2 AND N_PZ_526 AND BinCnt(4) AND BinCnt(5))
	OR (NOT Context_FFd2 AND NOT Context_FFd1 AND N_PZ_522 AND 
	BinCnt(6))
	OR (Context_FFd1 AND N_PZ_526 AND BinCnt(4) AND BinCnt(5))
	OR (NOT N_PZ_522 AND N_PZ_526 AND BinCnt(4) AND BinCnt(5)));

FTCPE_BinCnt7: FTCPE port map (BinCnt(7),BinCnt_T(7),FDiv(3),NOT Reset,'0','1');
BinCnt_T(7) <= ((NOT Context_FFd2 AND NOT Context_FFd1 AND N_PZ_522 AND 
	BinCnt(7))
	OR (Context_FFd2 AND N_PZ_526 AND BinCnt(4) AND BinCnt(5) AND 
	BinCnt(6))
	OR (Context_FFd1 AND N_PZ_526 AND BinCnt(4) AND BinCnt(5) AND 
	BinCnt(6))
	OR (NOT N_PZ_522 AND N_PZ_526 AND BinCnt(4) AND BinCnt(5) AND 
	BinCnt(6)));

FDCPE_Context_FFd1: FDCPE port map (Context_FFd1,Context_FFd2,NOT Clk,NOT Reset,'0',Context_FFd1_CE);
Context_FFd1_CE <= (NOT MachineState_FFd1 AND MachineState_FFd2);

FTCPE_Context_FFd2: FTCPE port map (Context_FFd2,Context_FFd2_T,NOT Clk,NOT Reset,'0','1');
Context_FFd2_T <= ((NOT MachineState_FFd1 AND MachineState_FFd2 AND 
	Context_FFd2)
	OR (NOT MachineState_FFd1 AND MachineState_FFd2 AND 
	NOT Context_FFd1));


DSel0 <= NOT ((NOT MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1)));


DSel1 <= NOT ((MuxDisplInstance/SelCnt(0) AND 
	NOT MuxDisplInstance/SelCnt(1)));


DSel2 <= NOT ((NOT MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1)));


DSel3 <= NOT ((MuxDisplInstance/SelCnt(0) AND 
	MuxDisplInstance/SelCnt(1)));

FDCPE_DirKeyInstance/ShRegister0: FDCPE port map (DirKeyInstance/ShRegister(0),DirKeyInp,FDiv(4),'0',NOT Reset,'1');

FDCPE_DirKeyInstance/ShRegister1: FDCPE port map (DirKeyInstance/ShRegister(1),DirKeyInstance/ShRegister(0),FDiv(4),'0',NOT Reset,'1');

FDCPE_DirKeyInstance/ShRegister2: FDCPE port map (DirKeyInstance/ShRegister(2),DirKeyInstance/ShRegister(1),FDiv(4),'0',NOT Reset,'1');

FDCPE_DirKeyInstance/ShRegister3: FDCPE port map (DirKeyInstance/ShRegister(3),DirKeyInstance/ShRegister(2),FDiv(4),'0',NOT Reset,'1');

LDCP_DirKeyStatus: LDCP port map (DirKeyStatus,NOT '0',,DirKeyStatus_CLR,'0');
DirKeyStatus_G <= (NOT DirKeyInstance/ShRegister(0) AND 
	NOT DirKeyInstance/ShRegister(1) AND NOT DirKeyInstance/ShRegister(2) AND 
	NOT DirKeyInstance/ShRegister(3));
DirKeyStatus_CLR <= (DirKeyInstance/ShRegister(0) AND 
	DirKeyInstance/ShRegister(1) AND DirKeyInstance/ShRegister(2) AND 
	DirKeyInstance/ShRegister(3));

FTCPE_DirLed: FTCPE port map (DirLed,DirLed_T,NOT Clk,'0',NOT Reset,'1');
DirLed_T <= (MachineState_FFd1 AND MachineState_FFd2);

FTCPE_FClk: FTCPE port map (FClk,FClk_T,NOT Clk,NOT Reset,'0','1');
FClk_T <= (FDivInstance/FDivCnt(0) AND FDivInstance/FDivCnt(1) AND 
	FDivInstance/FDivCnt(2) AND FDivInstance/FDivCnt(3) AND FDivInstance/FDivCnt(4) AND 
	FDivInstance/FDivCnt(5) AND FDivInstance/FDivCnt(6));

FTCPE_FDiv0: FTCPE port map (FDiv(0),'0',FClk,NOT Reset,'0','1');

FTCPE_FDiv1: FTCPE port map (FDiv(1),FDiv(0),FClk,NOT Reset,'0','1');

FTCPE_FDiv2: FTCPE port map (FDiv(2),FDiv_T(2),FClk,NOT Reset,'0','1');
FDiv_T(2) <= (FDiv(0) AND FDiv(1));

FTCPE_FDiv3: FTCPE port map (FDiv(3),FDiv_T(3),FClk,NOT Reset,'0','1');
FDiv_T(3) <= (FDiv(0) AND FDiv(1) AND FDiv(2));

FTCPE_FDiv4: FTCPE port map (FDiv(4),FDiv_T(4),FClk,NOT Reset,'0','1');
FDiv_T(4) <= (FDiv(3) AND FDiv(0) AND FDiv(1) AND FDiv(2));

FTCPE_FDiv5: FTCPE port map (FDiv(5),FDiv_T(5),FClk,NOT Reset,'0','1');
FDiv_T(5) <= (FDiv(3) AND FDiv(0) AND FDiv(1) AND FDiv(2) AND 
	FDiv(4));

FTCPE_FDiv6: FTCPE port map (FDiv(6),FDiv_T(6),FClk,NOT Reset,'0','1');
FDiv_T(6) <= (FDiv(3) AND FDiv(0) AND FDiv(1) AND FDiv(2) AND 
	FDiv(4) AND FDiv(5));

FTCPE_FDivInstance/FDivCnt0: FTCPE port map (FDivInstance/FDivCnt(0),'0',NOT Clk,NOT Reset,'0','1');

FTCPE_FDivInstance/FDivCnt1: FTCPE port map (FDivInstance/FDivCnt(1),FDivInstance/FDivCnt(0),NOT Clk,NOT Reset,'0','1');

FTCPE_FDivInstance/FDivCnt2: FTCPE port map (FDivInstance/FDivCnt(2),FDivInstance/FDivCnt_T(2),NOT Clk,NOT Reset,'0','1');
FDivInstance/FDivCnt_T(2) <= (FDivInstance/FDivCnt(0) AND FDivInstance/FDivCnt(1));

FTCPE_FDivInstance/FDivCnt3: FTCPE port map (FDivInstance/FDivCnt(3),FDivInstance/FDivCnt_T(3),NOT Clk,NOT Reset,'0','1');
FDivInstance/FDivCnt_T(3) <= (FDivInstance/FDivCnt(0) AND FDivInstance/FDivCnt(1) AND 
	FDivInstance/FDivCnt(2));

FTCPE_FDivInstance/FDivCnt4: FTCPE port map (FDivInstance/FDivCnt(4),FDivInstance/FDivCnt_T(4),NOT Clk,NOT Reset,'0','1');
FDivInstance/FDivCnt_T(4) <= (FDivInstance/FDivCnt(0) AND FDivInstance/FDivCnt(1) AND 
	FDivInstance/FDivCnt(2) AND FDivInstance/FDivCnt(3));

FTCPE_FDivInstance/FDivCnt5: FTCPE port map (FDivInstance/FDivCnt(5),FDivInstance/FDivCnt_T(5),NOT Clk,NOT Reset,'0','1');
FDivInstance/FDivCnt_T(5) <= (FDivInstance/FDivCnt(0) AND FDivInstance/FDivCnt(1) AND 
	FDivInstance/FDivCnt(2) AND FDivInstance/FDivCnt(3) AND FDivInstance/FDivCnt(4));

FTCPE_FDivInstance/FDivCnt6: FTCPE port map (FDivInstance/FDivCnt(6),FDivInstance/FDivCnt_T(6),NOT Clk,NOT Reset,'0','1');
FDivInstance/FDivCnt_T(6) <= (FDivInstance/FDivCnt(0) AND FDivInstance/FDivCnt(1) AND 
	FDivInstance/FDivCnt(2) AND FDivInstance/FDivCnt(3) AND FDivInstance/FDivCnt(4) AND 
	FDivInstance/FDivCnt(5));

FTCPE_LCmpReg0: FTCPE port map (LCmpReg(0),Context_FFd2,SetKeyStatus,NOT Reset,'0','1');

FTCPE_LCmpReg1: FTCPE port map (LCmpReg(1),LCmpReg_T(1),SetKeyStatus,NOT Reset,'0','1');
LCmpReg_T(1) <= ((Context_FFd2 AND LCmpReg(0) AND DirLed)
	OR (Context_FFd2 AND NOT LCmpReg(0) AND NOT DirLed));

FTCPE_LCmpReg2: FTCPE port map (LCmpReg(2),LCmpReg_T(2),SetKeyStatus,NOT Reset,'0','1');
LCmpReg_T(2) <= ((Context_FFd2 AND LCmpReg(0) AND LCmpReg(1) AND DirLed)
	OR (Context_FFd2 AND NOT LCmpReg(0) AND NOT LCmpReg(1) AND NOT DirLed));

FTCPE_LCmpReg3: FTCPE port map (LCmpReg(3),LCmpReg_T(3),SetKeyStatus,NOT Reset,'0','1');
LCmpReg_T(3) <= ((Context_FFd2 AND LCmpReg(0) AND LCmpReg(1) AND DirLed AND 
	LCmpReg(2))
	OR (Context_FFd2 AND NOT LCmpReg(0) AND NOT LCmpReg(1) AND NOT DirLed AND 
	NOT LCmpReg(2)));

FTCPE_LCmpReg4: FTCPE port map (LCmpReg(4),LCmpReg_T(4),SetKeyStatus,NOT Reset,'0','1');
LCmpReg_T(4) <= ((Context_FFd2 AND LCmpReg(0) AND LCmpReg(1) AND DirLed AND 
	LCmpReg(2) AND LCmpReg(3))
	OR (Context_FFd2 AND NOT LCmpReg(0) AND NOT LCmpReg(1) AND NOT DirLed AND 
	NOT LCmpReg(2) AND NOT LCmpReg(3)));

FTCPE_LCmpReg5: FTCPE port map (LCmpReg(5),LCmpReg_T(5),SetKeyStatus,NOT Reset,'0','1');
LCmpReg_T(5) <= ((Context_FFd2 AND LCmpReg(0) AND LCmpReg(1) AND DirLed AND 
	LCmpReg(2) AND LCmpReg(3) AND LCmpReg(4))
	OR (Context_FFd2 AND NOT LCmpReg(0) AND NOT LCmpReg(1) AND NOT DirLed AND 
	NOT LCmpReg(2) AND NOT LCmpReg(3) AND NOT LCmpReg(4)));

FTCPE_LCmpReg6: FTCPE port map (LCmpReg(6),LCmpReg_T(6),SetKeyStatus,NOT Reset,'0','1');
LCmpReg_T(6) <= ((Context_FFd2 AND LCmpReg(0) AND LCmpReg(1) AND DirLed AND 
	LCmpReg(2) AND LCmpReg(3) AND LCmpReg(4) AND LCmpReg(5))
	OR (Context_FFd2 AND NOT LCmpReg(0) AND NOT LCmpReg(1) AND NOT DirLed AND 
	NOT LCmpReg(2) AND NOT LCmpReg(3) AND NOT LCmpReg(4) AND NOT LCmpReg(5)));

FTCPE_LCmpReg7: FTCPE port map (LCmpReg(7),LCmpReg_T(7),SetKeyStatus,'0',NOT Reset,'1');
LCmpReg_T(7) <= ((Context_FFd2 AND LCmpReg(0) AND LCmpReg(1) AND DirLed AND 
	LCmpReg(2) AND LCmpReg(3) AND LCmpReg(4) AND LCmpReg(5) AND 
	LCmpReg(6))
	OR (Context_FFd2 AND NOT LCmpReg(0) AND NOT LCmpReg(1) AND NOT DirLed AND 
	NOT LCmpReg(2) AND NOT LCmpReg(3) AND NOT LCmpReg(4) AND NOT LCmpReg(5) AND 
	NOT LCmpReg(6)));

FDCPE_MachineState_FFd1: FDCPE port map (MachineState_FFd1,MachineState_FFd1_D,NOT Clk,NOT Reset,'0','1');
MachineState_FFd1_D <= NOT (((NOT MachineState_FFd1 AND NOT MachineState_FFd2 AND 
	ModeKeyStatus)
	OR (NOT MachineState_FFd2 AND NOT ModeKeyStatus AND NOT DirKeyStatus)));

FDCPE_MachineState_FFd2: FDCPE port map (MachineState_FFd2,MachineState_FFd2_D,NOT Clk,NOT Reset,'0','1');
MachineState_FFd2_D <= ((NOT MachineState_FFd1 AND NOT MachineState_FFd2 AND 
	ModeKeyStatus)
	OR (NOT MachineState_FFd1 AND NOT MachineState_FFd2 AND 
	DirKeyStatus));


Mcompar_BinCnt_cmp_eq0000_AEB_or0000 <= ((BinCnt(0) AND NOT LCmpReg(0))
	OR (NOT BinCnt(0) AND LCmpReg(0))
	OR (BinCnt(1) AND NOT LCmpReg(1))
	OR (NOT BinCnt(1) AND LCmpReg(1))
	OR (BinCnt(2) AND NOT LCmpReg(2))
	OR (NOT BinCnt(2) AND LCmpReg(2))
	OR (BinCnt(3) AND NOT LCmpReg(3))
	OR (NOT BinCnt(3) AND LCmpReg(3))
	OR (BinCnt(4) AND NOT LCmpReg(4))
	OR (NOT BinCnt(4) AND LCmpReg(4))
	OR (BinCnt(5) AND NOT LCmpReg(5))
	OR (NOT BinCnt(5) AND LCmpReg(5))
	OR (BinCnt(6) AND NOT LCmpReg(6))
	OR (NOT BinCnt(6) AND LCmpReg(6))
	OR (BinCnt(7) AND NOT LCmpReg(7))
	OR (NOT BinCnt(7) AND LCmpReg(7)));


ModeKeyInstance/ShRegister(0).COMB <= (Reset AND SetupKeyInstance/DelayCntClear);FDCPE_ModeKeyInstance/ShRegister0: FDCPE port map (ModeKeyInstance/ShRegister(0),ModeKeyInp,FDiv(4),'0',NOT Reset,'1');

FDCPE_ModeKeyInstance/ShRegister1: FDCPE port map (ModeKeyInstance/ShRegister(1),ModeKeyInstance/ShRegister(0),FDiv(4),'0',NOT Reset,'1');

FDCPE_ModeKeyInstance/ShRegister2: FDCPE port map (ModeKeyInstance/ShRegister(2),ModeKeyInstance/ShRegister(1),FDiv(4),'0',NOT Reset,'1');

FDCPE_ModeKeyInstance/ShRegister3: FDCPE port map (ModeKeyInstance/ShRegister(3),ModeKeyInstance/ShRegister(2),FDiv(4),'0',NOT Reset,'1');

LDCP_ModeKeyStatus: LDCP port map (ModeKeyStatus,NOT '0',,ModeKeyStatus_CLR,'0');
ModeKeyStatus_G <= (NOT ModeKeyInstance/ShRegister(0) AND 
	NOT ModeKeyInstance/ShRegister(1) AND NOT ModeKeyInstance/ShRegister(2) AND 
	NOT ModeKeyInstance/ShRegister(3));
ModeKeyStatus_CLR <= (ModeKeyInstance/ShRegister(0) AND 
	ModeKeyInstance/ShRegister(1) AND ModeKeyInstance/ShRegister(2) AND 
	ModeKeyInstance/ShRegister(3));

FTCPE_MuxDisplInstance/SelCnt0: FTCPE port map (MuxDisplInstance/SelCnt(0),'0',FDiv(3),NOT Reset,'0','1');

FTCPE_MuxDisplInstance/SelCnt1: FTCPE port map (MuxDisplInstance/SelCnt(1),MuxDisplInstance/SelCnt(0),FDiv(3),NOT Reset,'0','1');


MuxDisplInstance/Tetr(0) <= ((LCmpReg(0) AND NOT DSel0)
	OR (LCmpReg(4) AND NOT DSel1)
	OR (UCmpReg(0) AND NOT DSel2)
	OR (UCmpReg(4) AND NOT DSel3));


MuxDisplInstance/Tetr(1) <= ((LCmpReg(1) AND NOT DSel0)
	OR (LCmpReg(5) AND NOT DSel1)
	OR (UCmpReg(1) AND NOT DSel2)
	OR (UCmpReg(5) AND NOT DSel3));


MuxDisplInstance/Tetr(2) <= ((LCmpReg(2) AND NOT DSel0)
	OR (LCmpReg(6) AND NOT DSel1)
	OR (UCmpReg(2) AND NOT DSel2)
	OR (UCmpReg(6) AND NOT DSel3));


MuxDisplInstance/Tetr(3) <= ((LCmpReg(3) AND NOT DSel0)
	OR (LCmpReg(7) AND NOT DSel1)
	OR (UCmpReg(3) AND NOT DSel2)
	OR (UCmpReg(7) AND NOT DSel3));


N_PZ_456 <= ((BinCnt(3) AND NOT UCmpReg(3))
	OR (NOT BinCnt(3) AND UCmpReg(3)));


N_PZ_457 <= (NOT Context_FFd2 AND NOT Context_FFd1 AND BinCnt(0) AND 
	BinCnt(1));


N_PZ_521 <= ((BinCnt(4) AND NOT UCmpReg(4))
	OR (NOT BinCnt(4) AND UCmpReg(4)));


N_PZ_522 <= ((NOT OutSig AND NOT Mcompar_BinCnt_cmp_eq0000_AEB_or0000)
	OR (OutSig AND BinCnt(0) AND BinCnt(1) AND BinCnt(2) AND 
	UCmpReg(0) AND UCmpReg(1) AND UCmpReg(2) AND NOT OutFF_or000039 AND 
	NOT OutFF_or000040 AND NOT OutFF_or000041 AND NOT OutFF_or000047 AND NOT OutFF_or000048 AND 
	NOT OutFF_or000049 AND NOT N_PZ_456 AND NOT N_PZ_521)
	OR (OutSig AND BinCnt(0) AND BinCnt(1) AND NOT BinCnt(2) AND 
	UCmpReg(0) AND UCmpReg(1) AND NOT UCmpReg(2) AND NOT OutFF_or000039 AND 
	NOT OutFF_or000040 AND NOT OutFF_or000041 AND NOT OutFF_or000047 AND NOT OutFF_or000048 AND 
	NOT OutFF_or000049 AND NOT N_PZ_456 AND NOT N_PZ_521)
	OR (OutSig AND BinCnt(0) AND NOT BinCnt(1) AND BinCnt(2) AND 
	UCmpReg(0) AND NOT UCmpReg(1) AND UCmpReg(2) AND NOT OutFF_or000039 AND 
	NOT OutFF_or000040 AND NOT OutFF_or000041 AND NOT OutFF_or000047 AND NOT OutFF_or000048 AND 
	NOT OutFF_or000049 AND NOT N_PZ_456 AND NOT N_PZ_521)
	OR (OutSig AND BinCnt(0) AND NOT BinCnt(1) AND NOT BinCnt(2) AND 
	UCmpReg(0) AND NOT UCmpReg(1) AND NOT UCmpReg(2) AND NOT OutFF_or000039 AND 
	NOT OutFF_or000040 AND NOT OutFF_or000041 AND NOT OutFF_or000047 AND NOT OutFF_or000048 AND 
	NOT OutFF_or000049 AND NOT N_PZ_456 AND NOT N_PZ_521)
	OR (OutSig AND NOT BinCnt(0) AND BinCnt(1) AND BinCnt(2) AND 
	NOT UCmpReg(0) AND UCmpReg(1) AND UCmpReg(2) AND NOT OutFF_or000039 AND 
	NOT OutFF_or000040 AND NOT OutFF_or000041 AND NOT OutFF_or000047 AND NOT OutFF_or000048 AND 
	NOT OutFF_or000049 AND NOT N_PZ_456 AND NOT N_PZ_521)
	OR (OutSig AND NOT BinCnt(0) AND BinCnt(1) AND NOT BinCnt(2) AND 
	NOT UCmpReg(0) AND UCmpReg(1) AND NOT UCmpReg(2) AND NOT OutFF_or000039 AND 
	NOT OutFF_or000040 AND NOT OutFF_or000041 AND NOT OutFF_or000047 AND NOT OutFF_or000048 AND 
	NOT OutFF_or000049 AND NOT N_PZ_456 AND NOT N_PZ_521)
	OR (OutSig AND NOT BinCnt(0) AND NOT BinCnt(1) AND BinCnt(2) AND 
	NOT UCmpReg(0) AND NOT UCmpReg(1) AND UCmpReg(2) AND NOT OutFF_or000039 AND 
	NOT OutFF_or000040 AND NOT OutFF_or000041 AND NOT OutFF_or000047 AND NOT OutFF_or000048 AND 
	NOT OutFF_or000049 AND NOT N_PZ_456 AND NOT N_PZ_521)
	OR (OutSig AND NOT BinCnt(0) AND NOT BinCnt(1) AND NOT BinCnt(2) AND 
	NOT UCmpReg(0) AND NOT UCmpReg(1) AND NOT UCmpReg(2) AND NOT OutFF_or000039 AND 
	NOT OutFF_or000040 AND NOT OutFF_or000041 AND NOT OutFF_or000047 AND NOT OutFF_or000048 AND 
	NOT OutFF_or000049 AND NOT N_PZ_456 AND NOT N_PZ_521));


N_PZ_526 <= (BinCnt(2) AND N_PZ_457 AND BinCnt(3));


OutFF_or000039 <= (BinCnt(5) AND NOT UCmpReg(5));


OutFF_or000040 <= (BinCnt(6) AND NOT UCmpReg(6));


OutFF_or000041 <= (BinCnt(7) AND NOT UCmpReg(7));


OutFF_or000047 <= (NOT BinCnt(5) AND UCmpReg(5));


OutFF_or000048 <= (NOT BinCnt(6) AND UCmpReg(6));


OutFF_or000049 <= (NOT BinCnt(7) AND UCmpReg(7));

FTCPE_OutSig: FTCPE port map (OutSig,OutSig_T,FDiv(3),NOT Reset,'0','1');
OutSig_T <= (NOT Context_FFd2 AND NOT Context_FFd1 AND N_PZ_522);


Seg_A <= (NOT MuxDisplInstance/Tetr(1) AND 
	MuxDisplInstance/Tetr(0))
	XOR ((NOT MuxDisplInstance/Tetr(1) AND 
	NOT MuxDisplInstance/Tetr(3) AND MuxDisplInstance/Tetr(2))
	OR (MuxDisplInstance/Tetr(0) AND 
	MuxDisplInstance/Tetr(3) AND NOT MuxDisplInstance/Tetr(2)));


Seg_B <= (NOT MuxDisplInstance/Tetr(0) AND 
	MuxDisplInstance/Tetr(2))
	XOR ((MuxDisplInstance/Tetr(1) AND 
	MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(3))
	OR (NOT MuxDisplInstance/Tetr(1) AND 
	NOT MuxDisplInstance/Tetr(3) AND MuxDisplInstance/Tetr(2)));


Seg_C <= ((MuxDisplInstance/Tetr(1) AND 
	MuxDisplInstance/Tetr(3) AND MuxDisplInstance/Tetr(2))
	OR (NOT MuxDisplInstance/Tetr(0) AND 
	MuxDisplInstance/Tetr(3) AND MuxDisplInstance/Tetr(2))
	OR (MuxDisplInstance/Tetr(1) AND 
	NOT MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(3) AND 
	NOT MuxDisplInstance/Tetr(2)));


Seg_D <= ((MuxDisplInstance/Tetr(1) AND 
	MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(2))
	OR (MuxDisplInstance/Tetr(1) AND 
	NOT MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(3) AND 
	NOT MuxDisplInstance/Tetr(2))
	OR (NOT MuxDisplInstance/Tetr(1) AND 
	MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(3) AND 
	NOT MuxDisplInstance/Tetr(2))
	OR (NOT MuxDisplInstance/Tetr(1) AND 
	NOT MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(3) AND 
	MuxDisplInstance/Tetr(2)));


Seg_E <= ((MuxDisplInstance/Tetr(0) AND 
	NOT MuxDisplInstance/Tetr(3))
	OR (NOT MuxDisplInstance/Tetr(1) AND 
	MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(2))
	OR (NOT MuxDisplInstance/Tetr(1) AND 
	NOT MuxDisplInstance/Tetr(3) AND MuxDisplInstance/Tetr(2)));


Seg_F <= (MuxDisplInstance/Tetr(0) AND 
	NOT MuxDisplInstance/Tetr(3))
	XOR ((NOT MuxDisplInstance/Tetr(1) AND 
	MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(2))
	OR (MuxDisplInstance/Tetr(1) AND 
	NOT MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(3) AND 
	NOT MuxDisplInstance/Tetr(2)));


Seg_G <= ((NOT MuxDisplInstance/Tetr(1) AND 
	NOT MuxDisplInstance/Tetr(3) AND NOT MuxDisplInstance/Tetr(2))
	OR (MuxDisplInstance/Tetr(1) AND 
	MuxDisplInstance/Tetr(0) AND NOT MuxDisplInstance/Tetr(3) AND 
	MuxDisplInstance/Tetr(2))
	OR (NOT MuxDisplInstance/Tetr(1) AND 
	NOT MuxDisplInstance/Tetr(0) AND MuxDisplInstance/Tetr(3) AND 
	MuxDisplInstance/Tetr(2)));


Seg_K <= NOT (((Context_FFd2 AND Context_FFd1)
	OR (Context_FFd2 AND DSel2 AND DSel3)
	OR (Context_FFd1 AND DSel1 AND DSel0)
	OR (DSel2 AND DSel1 AND DSel0 AND DSel3)));

FDCPE_SetKeyStatus: FDCPE port map (SetKeyStatus,SetKeyStatus_D,Clk,'0','0','1');
SetKeyStatus_D <= ((NOT Reset AND SetKeyStatus)
	OR (Reset AND SetupKeyInstance/AutomatState_FFd4 AND 
	SetupKeyInstance/AutomatState_FFd2 AND NOT SetupKeyInstance/AutomatState_FFd3)
	OR (Reset AND NOT SetupKeyInstance/AutomatState_FFd4 AND 
	NOT SetupKeyInstance/AutomatState_FFd2 AND SetupKeyInstance/AutomatState_FFd3));

FDCPE_SetupKeyInstance/AutomatState_FFd1: FDCPE port map (SetupKeyInstance/AutomatState_FFd1,SetupKeyInstance/AutomatState_FFd1_D,Clk,NOT Reset,'0','1');
SetupKeyInstance/AutomatState_FFd1_D <= ((SetupKeyInstance/AutomatState_FFd4 AND 
	SetupKeyInstance/AutomatState_FFd2 AND NOT SetupKeyInstance/AutomatState_FFd3)
	OR (NOT SetKeyInp AND SetupKeyInstance/AutomatState_FFd1 AND 
	SetupKeyInstance/DelayCnt(0))
	OR (NOT SetKeyInp AND SetupKeyInstance/AutomatState_FFd1 AND 
	SetupKeyInstance/DelayCnt(1))
	OR (NOT SetKeyInp AND SetupKeyInstance/AutomatState_FFd1 AND 
	NOT SetupKeyInstance/DelayCnt(2))
	OR (NOT SetKeyInp AND SetupKeyInstance/AutomatState_FFd1 AND 
	SetupKeyInstance/DelayCnt(3))
	OR (NOT SetKeyInp AND SetupKeyInstance/AutomatState_FFd1 AND 
	SetupKeyInstance/DelayCnt(4)));

FDCPE_SetupKeyInstance/AutomatState_FFd2: FDCPE port map (SetupKeyInstance/AutomatState_FFd2,SetupKeyInstance/AutomatState_FFd2_D,Clk,NOT Reset,'0','1');
SetupKeyInstance/AutomatState_FFd2_D <= NOT (((SetupKeyInstance/AutomatState_FFd4 AND 
	NOT SetupKeyInstance/AutomatState_FFd2 AND NOT SetupKeyInstance/AutomatState_FFd1)
	OR (NOT SetupKeyInstance/AutomatState_FFd2 AND 
	NOT SetupKeyInstance/AutomatState_FFd1 AND NOT SetupKeyInstance/AutomatState_FFd3)
	OR (NOT SetupKeyInstance/AutomatState_FFd4 AND 
	NOT SetupKeyInstance/AutomatState_FFd1 AND NOT SetupKeyInstance/AutomatState_FFd3 AND 
	SetupKeyInstance/DelayCnt(0) AND SetupKeyInstance/DelayCnt(1) AND 
	NOT SetupKeyInstance/DelayCnt(2) AND NOT SetupKeyInstance/DelayCnt(3) AND 
	NOT SetupKeyInstance/DelayCnt(4))));

FTCPE_SetupKeyInstance/AutomatState_FFd3: FTCPE port map (SetupKeyInstance/AutomatState_FFd3,SetupKeyInstance/AutomatState_FFd3_T,Clk,NOT Reset,'0','1');
SetupKeyInstance/AutomatState_FFd3_T <= ((SetupKeyInstance/AutomatState_FFd4 AND 
	NOT SetupKeyInstance/AutomatState_FFd2 AND NOT SetupKeyInstance/AutomatState_FFd3)
	OR (SetKeyInp AND SetupKeyInstance/AutomatState_FFd1 AND 
	NOT SetupKeyInstance/AutomatState_FFd3)
	OR (SetupKeyInstance/AutomatState_FFd4 AND SetKeyInp AND 
	NOT SetupKeyInstance/AutomatState_FFd1 AND SetupKeyInstance/AutomatState_FFd3)
	OR (SetupKeyInstance/AutomatState_FFd4 AND NOT SetKeyInp AND 
	SetupKeyInstance/AutomatState_FFd2 AND SetupKeyInstance/AutomatState_FFd3)
	OR (NOT SetKeyInp AND SetupKeyInstance/AutomatState_FFd2 AND 
	SetupKeyInstance/AutomatState_FFd3 AND NOT SetupKeyInstance/DelayCnt(0) AND 
	NOT SetupKeyInstance/DelayCnt(1) AND SetupKeyInstance/DelayCnt(2) AND 
	SetupKeyInstance/DelayCnt(3) AND SetupKeyInstance/DelayCnt(4)));

FDCPE_SetupKeyInstance/AutomatState_FFd4: FDCPE port map (SetupKeyInstance/AutomatState_FFd4,SetupKeyInstance/AutomatState_FFd4_D,Clk,NOT Reset,'0','1');
SetupKeyInstance/AutomatState_FFd4_D <= (SetupKeyInstance/AutomatState_FFd4 AND NOT SetKeyInp AND 
	NOT SetupKeyInstance/AutomatState_FFd2)
	XOR ((SetKeyInp AND SetupKeyInstance/AutomatState_FFd1)
	OR (SetupKeyInstance/AutomatState_FFd4 AND SetKeyInp AND 
	NOT SetupKeyInstance/AutomatState_FFd2 AND NOT SetupKeyInstance/AutomatState_FFd3)
	OR (NOT SetupKeyInstance/AutomatState_FFd4 AND SetKeyInp AND 
	SetupKeyInstance/AutomatState_FFd2 AND SetupKeyInstance/AutomatState_FFd3)
	OR (NOT SetupKeyInstance/AutomatState_FFd4 AND NOT SetKeyInp AND 
	NOT SetupKeyInstance/AutomatState_FFd2 AND NOT SetupKeyInstance/AutomatState_FFd3)
	OR (NOT SetupKeyInstance/AutomatState_FFd4 AND 
	SetupKeyInstance/AutomatState_FFd1 AND NOT SetupKeyInstance/DelayCnt(0) AND 
	NOT SetupKeyInstance/DelayCnt(1) AND SetupKeyInstance/DelayCnt(2) AND 
	NOT SetupKeyInstance/DelayCnt(3) AND NOT SetupKeyInstance/DelayCnt(4))
	OR (SetupKeyInstance/AutomatState_FFd2 AND 
	SetupKeyInstance/AutomatState_FFd1 AND NOT SetupKeyInstance/DelayCnt(0) AND 
	NOT SetupKeyInstance/DelayCnt(1) AND SetupKeyInstance/DelayCnt(2) AND 
	NOT SetupKeyInstance/DelayCnt(3) AND NOT SetupKeyInstance/DelayCnt(4))
	OR (NOT SetupKeyInstance/AutomatState_FFd4 AND 
	SetupKeyInstance/AutomatState_FFd2 AND SetupKeyInstance/AutomatState_FFd3 AND 
	NOT SetupKeyInstance/DelayCnt(0) AND NOT SetupKeyInstance/DelayCnt(1) AND 
	SetupKeyInstance/DelayCnt(2) AND SetupKeyInstance/DelayCnt(3) AND 
	SetupKeyInstance/DelayCnt(4))
	OR (SetupKeyInstance/AutomatState_FFd4 AND NOT SetKeyInp AND 
	NOT SetupKeyInstance/AutomatState_FFd2 AND SetupKeyInstance/AutomatState_FFd3 AND 
	SetupKeyInstance/DelayCnt(0) AND SetupKeyInstance/DelayCnt(1) AND 
	NOT SetupKeyInstance/DelayCnt(2) AND NOT SetupKeyInstance/DelayCnt(3) AND 
	NOT SetupKeyInstance/DelayCnt(4)));

FTCPE_SetupKeyInstance/DelayCnt0: FTCPE port map (SetupKeyInstance/DelayCnt(0),SetupKeyInstance/DelayCntEnable,FDiv(6),NOT ModeKeyInstance/ShRegister(0).COMB,'0','1');

FTCPE_SetupKeyInstance/DelayCnt1: FTCPE port map (SetupKeyInstance/DelayCnt(1),SetupKeyInstance/DelayCnt_T(1),FDiv(6),NOT ModeKeyInstance/ShRegister(0).COMB,'0','1');
SetupKeyInstance/DelayCnt_T(1) <= (SetupKeyInstance/DelayCnt(0) AND 
	SetupKeyInstance/DelayCntEnable);

FTCPE_SetupKeyInstance/DelayCnt2: FTCPE port map (SetupKeyInstance/DelayCnt(2),SetupKeyInstance/DelayCnt_T(2),FDiv(6),NOT ModeKeyInstance/ShRegister(0).COMB,'0','1');
SetupKeyInstance/DelayCnt_T(2) <= (SetupKeyInstance/DelayCnt(0) AND 
	SetupKeyInstance/DelayCntEnable AND SetupKeyInstance/DelayCnt(1));

FTCPE_SetupKeyInstance/DelayCnt3: FTCPE port map (SetupKeyInstance/DelayCnt(3),SetupKeyInstance/DelayCnt_T(3),FDiv(6),NOT ModeKeyInstance/ShRegister(0).COMB,'0','1');
SetupKeyInstance/DelayCnt_T(3) <= (SetupKeyInstance/DelayCnt(0) AND 
	SetupKeyInstance/DelayCntEnable AND SetupKeyInstance/DelayCnt(1) AND 
	SetupKeyInstance/DelayCnt(2));

FTCPE_SetupKeyInstance/DelayCnt4: FTCPE port map (SetupKeyInstance/DelayCnt(4),SetupKeyInstance/DelayCnt_T(4),FDiv(6),NOT ModeKeyInstance/ShRegister(0).COMB,'0','1');
SetupKeyInstance/DelayCnt_T(4) <= (SetupKeyInstance/DelayCnt(0) AND 
	SetupKeyInstance/DelayCntEnable AND SetupKeyInstance/DelayCnt(1) AND 
	SetupKeyInstance/DelayCnt(2) AND SetupKeyInstance/DelayCnt(3));

FDCPE_SetupKeyInstance/DelayCntClear: FDCPE port map (SetupKeyInstance/DelayCntClear,SetupKeyInstance/DelayCntClear_D,Clk,'0','0','1');
SetupKeyInstance/DelayCntClear_D <= NOT (((NOT Reset AND NOT SetupKeyInstance/DelayCntClear)
	OR (Reset AND SetupKeyInstance/AutomatState_FFd4 AND 
	SetupKeyInstance/AutomatState_FFd2 AND NOT SetupKeyInstance/AutomatState_FFd1)
	OR (Reset AND SetupKeyInstance/AutomatState_FFd4 AND 
	NOT SetupKeyInstance/AutomatState_FFd1 AND NOT SetupKeyInstance/AutomatState_FFd3)));

FDCPE_SetupKeyInstance/DelayCntEnable: FDCPE port map (SetupKeyInstance/DelayCntEnable,SetupKeyInstance/DelayCntEnable_D,Clk,'0','0','1');
SetupKeyInstance/DelayCntEnable_D <= NOT (((NOT Reset AND NOT SetupKeyInstance/DelayCntEnable)
	OR (Reset AND SetupKeyInstance/AutomatState_FFd4 AND 
	SetupKeyInstance/AutomatState_FFd2 AND NOT SetupKeyInstance/AutomatState_FFd1)
	OR (Reset AND NOT SetupKeyInstance/AutomatState_FFd2 AND 
	NOT SetupKeyInstance/AutomatState_FFd1 AND NOT SetupKeyInstance/AutomatState_FFd3)));

FTCPE_UCmpReg0: FTCPE port map (UCmpReg(0),Context_FFd1,SetKeyStatus,NOT Reset,'0','1');

FTCPE_UCmpReg1: FTCPE port map (UCmpReg(1),UCmpReg_T(1),SetKeyStatus,NOT Reset,'0','1');
UCmpReg_T(1) <= ((Context_FFd1 AND DirLed AND UCmpReg(0))
	OR (Context_FFd1 AND NOT DirLed AND NOT UCmpReg(0)));

FTCPE_UCmpReg2: FTCPE port map (UCmpReg(2),UCmpReg_T(2),SetKeyStatus,NOT Reset,'0','1');
UCmpReg_T(2) <= ((Context_FFd1 AND DirLed AND UCmpReg(0) AND UCmpReg(1))
	OR (Context_FFd1 AND NOT DirLed AND NOT UCmpReg(0) AND NOT UCmpReg(1)));

FTCPE_UCmpReg3: FTCPE port map (UCmpReg(3),UCmpReg_T(3),SetKeyStatus,NOT Reset,'0','1');
UCmpReg_T(3) <= ((Context_FFd1 AND DirLed AND UCmpReg(0) AND UCmpReg(1) AND 
	UCmpReg(2))
	OR (Context_FFd1 AND NOT DirLed AND NOT UCmpReg(0) AND NOT UCmpReg(1) AND 
	NOT UCmpReg(2)));

FTCPE_UCmpReg4: FTCPE port map (UCmpReg(4),UCmpReg_T(4),SetKeyStatus,NOT Reset,'0','1');
UCmpReg_T(4) <= ((Context_FFd1 AND DirLed AND UCmpReg(0) AND UCmpReg(1) AND 
	UCmpReg(2) AND UCmpReg(3))
	OR (Context_FFd1 AND NOT DirLed AND NOT UCmpReg(0) AND NOT UCmpReg(1) AND 
	NOT UCmpReg(2) AND NOT UCmpReg(3)));

FTCPE_UCmpReg5: FTCPE port map (UCmpReg(5),UCmpReg_T(5),SetKeyStatus,NOT Reset,'0','1');
UCmpReg_T(5) <= ((Context_FFd1 AND DirLed AND UCmpReg(0) AND UCmpReg(1) AND 
	UCmpReg(2) AND UCmpReg(3) AND UCmpReg(4))
	OR (Context_FFd1 AND NOT DirLed AND NOT UCmpReg(0) AND NOT UCmpReg(1) AND 
	NOT UCmpReg(2) AND NOT UCmpReg(3) AND NOT UCmpReg(4)));

FTCPE_UCmpReg6: FTCPE port map (UCmpReg(6),UCmpReg_T(6),SetKeyStatus,NOT Reset,'0','1');
UCmpReg_T(6) <= ((Context_FFd1 AND DirLed AND UCmpReg(0) AND UCmpReg(1) AND 
	UCmpReg(2) AND UCmpReg(5) AND UCmpReg(3) AND UCmpReg(4))
	OR (Context_FFd1 AND NOT DirLed AND NOT UCmpReg(0) AND NOT UCmpReg(1) AND 
	NOT UCmpReg(2) AND NOT UCmpReg(5) AND NOT UCmpReg(3) AND NOT UCmpReg(4)));

FTCPE_UCmpReg7: FTCPE port map (UCmpReg(7),UCmpReg_T(7),SetKeyStatus,'0',NOT Reset,'1');
UCmpReg_T(7) <= ((Context_FFd1 AND DirLed AND UCmpReg(0) AND UCmpReg(1) AND 
	UCmpReg(2) AND UCmpReg(5) AND UCmpReg(3) AND UCmpReg(4) AND 
	UCmpReg(6))
	OR (Context_FFd1 AND NOT DirLed AND NOT UCmpReg(0) AND NOT UCmpReg(1) AND 
	NOT UCmpReg(2) AND NOT UCmpReg(5) AND NOT UCmpReg(3) AND NOT UCmpReg(4) AND 
	NOT UCmpReg(6)));


Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE); 
 FDDCPE (Q,D,C,CLR,PRE,CE); 
 FTCPE (Q,D,C,CLR,PRE,CE); 
 FTDCPE (Q,D,C,CLR,PRE,CE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC2C256-6-TQ144


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 VCC                              73 VCCIO-1.8                     
  2 WPU                              74 WPU                           
  3 WPU                              75 WPU                           
  4 WPU                              76 WPU                           
  5 WPU                              77 WPU                           
  6 WPU                              78 WPU                           
  7 WPU                              79 WPU                           
  8 VCCAUX                           80 WPU                           
  9 WPU                              81 WPU                           
 10 WPU                              82 WPU                           
 11 WPU                              83 WPU                           
 12 WPU                              84 VCC                           
 13 WPU                              85 WPU                           
 14 WPU                              86 WPU                           
 15 WPU                              87 WPU                           
 16 WPU                              88 WPU                           
 17 WPU                              89 GND                           
 18 WPU                              90 GND                           
 19 WPU                              91 WPU                           
 20 WPU                              92 WPU                           
 21 WPU                              93 VCCIO-1.8                     
 22 WPU                              94 SetKeyInp                     
 23 WPU                              95 WPU                           
 24 WPU                              96 WPU                           
 25 WPU                              97 WPU                           
 26 WPU                              98 WPU                           
 27 VCCIO-1.8                        99 GND                           
 28 WPU                             100 WPU                           
 29 GND                             101 WPU                           
 30 WPU                             102 WPU                           
 31 WPU                             103 WPU                           
 32 WPU                             104 WPU                           
 33 WPU                             105 WPU                           
 34 WPU                             106 WPU                           
 35 WPU                             107 WPU                           
 36 GND                             108 GND                           
 37 VCC                             109 VCCIO-1.8                     
 38 Clk                             110 WPU                           
 39 Reset                           111 WPU                           
 40 WPU                             112 WPU                           
 41 WPU                             113 WPU                           
 42 WPU                             114 WPU                           
 43 WPU                             115 WPU                           
 44 WPU                             116 WPU                           
 45 WPU                             117 WPU                           
 46 WPU                             118 WPU                           
 47 GND                             119 WPU                           
 48 WPU                             120 WPU                           
 49 WPU                             121 WPU                           
 50 WPU                             122 TDO                           
 51 WPU                             123 GND                           
 52 WPU                             124 DirKeyInp                     
 53 Seg_B                           125 WPU                           
 54 Seg_F                           126 DSel0                         
 55 VCCIO-1.8                       127 VCCIO-1.8                     
 56 Seg_A                           128 DSel1                         
 57 Seg_E                           129 DSel2                         
 58 Seg_D                           130 DSel3                         
 59 Seg_K                           131 WPU                           
 60 Seg_C                           132 WPU                           
 61 Seg_G                           133 WPU                           
 62 GND                             134 WPU                           
 63 TDI                             135 WPU                           
 64 WPU                             136 WPU                           
 65 TMS                             137 WPU                           
 66 WPU                             138 WPU                           
 67 TCK                             139 WPU                           
 68 DirLed                          140 WPU                           
 69 OutSig                          141 VCCIO-1.8                     
 70 WPU                             142 WPU                           
 71 WPU                             143 ModeKeyInp                    
 72 GND                             144 GND                           


Legend :  NC  = Not Connected, unbonded pin
        PGND  = Unused I/O configured as additional Ground pin
         KPR  = Unused I/O with weak keeper (leave unconnected)
         WPU  = Unused I/O with weak pull up (leave unconnected)
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
      VCCAUX  = Power supply for JTAG pins
   VCCIO-3.3  = I/O supply voltage for LVTTL, LVCMOS33, SSTL3_I
   VCCIO-2.5  = I/O supply voltage for LVCMOS25, SSTL2_I
   VCCIO-1.8  = I/O supply voltage for LVCMOS18
   VCCIO-1.5  = I/O supply voltage for LVCMOS15, HSTL_I
        VREF  = Reference voltage for indicated input standard
       *VREF  = Reference voltage pin selected by software
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc2c256-6-TQ144
Optimization Method                         : DENSITY
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Set Unused I/O Pin Termination              : PULLUP
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
Enable Input Registers                      : ON
Function Block Fan-in Limit                 : 38
Use DATA_GATE Attribute                     : ON
Set Tristate Outputs to Termination Mode    : PULLUP
Default Voltage Standard for All Outputs    : LVCMOS18
Input Limit                                 : 32
Pterm Limit                                 : 28